1 ## SPDX-License-Identifier: GPL-2.0-only
3 config INTEL_LYNXPOINT_LP
5 select ACPI_COMMON_MADT_IOAPIC
6 select ACPI_COMMON_MADT_LAPIC
7 select ACPI_INTEL_HARDWARE_SLEEP_VALUES
9 select AZALIA_HDA_CODEC_SUPPORT
10 select BOOT_DEVICE_SUPPORTS_WRITES
11 select HAVE_EM100PRO_SPI_CONSOLE_SUPPORT
12 select HAVE_POWER_STATE_AFTER_FAILURE
13 select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
14 select HAVE_SMI_HANDLER
16 select INTEL_DESCRIPTOR_MODE_CAPABLE
18 select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS
19 select SOUTHBRIDGE_INTEL_COMMON_RESET
20 select SOUTHBRIDGE_INTEL_COMMON_RTC
21 select SOUTHBRIDGE_INTEL_COMMON_SMBUS
22 select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
24 select TCO_SPACE_NOT_YET_SPLIT
30 config SERIRQ_CONTINUOUS_MODE
34 If you set this option to y, the serial IRQ machine will be
35 operated in continuous mode.
45 config PCIEXP_COMMON_CLOCK
53 config PCIEXP_L1_SUB_STATE
57 config SERIALIO_UART_CONSOLE
60 select DRIVERS_UART_8250MEM_32
62 Selected by mainboards where SerialIO UARTs can be used to retrieve
63 coreboot logs. Boards also need to set UART_FOR_CONSOLE accordingly.
65 config CONSOLE_UART_BASE_ADDRESS
66 default 0xd6000000 if SERIALIO_UART_CONSOLE
69 bool "Disable Intel ME PCI interface (MEI1)"
72 Disable and hide the ME PCI interface during finalize stage of boot.
73 This will prevent the OS (and userspace apps) from interacting with
74 the ME via the PCI interface after boot.