2 * This file is part of the coreboot project.
4 * Copyright (C) 2011, 2017 Advanced Micro Devices, Inc.
5 * Copyright (C) 2013 Sage Electronic Engineering, LLC
6 * Copyright (C) 2017 Google Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <device/device.h>
20 #include <device/pci_def.h>
21 #include <amdblocks/BiosCallOuts.h>
22 #include <soc/southbridge.h>
23 #include <soc/pci_devs.h>
26 #include <amdblocks/agesawrapper.h>
28 #include <amdblocks/dimm_spd.h>
30 #include <amdblocks/car.h>
32 void __weak
platform_FchParams_reset(
33 FCH_RESET_DATA_BLOCK
*FchParams_reset
) {}
35 AGESA_STATUS
agesa_fch_initreset(UINT32 Func
, UINTN FchData
, VOID
*ConfigPtr
)
37 AMD_CONFIG_PARAMS
*StdHeader
= ConfigPtr
;
39 if (StdHeader
->Func
== AMD_INIT_RESET
) {
40 FCH_RESET_DATA_BLOCK
*FchParams_reset
;
41 FchParams_reset
= (FCH_RESET_DATA_BLOCK
*)FchData
;
42 printk(BIOS_DEBUG
, "Fch OEM config in INIT RESET ");
44 /* Get platform specific configuration changes */
45 platform_FchParams_reset(FchParams_reset
);
47 printk(BIOS_DEBUG
, "Done\n");
53 AGESA_STATUS
agesa_fch_initenv(UINT32 Func
, UINTN FchData
, VOID
*ConfigPtr
)
55 AMD_CONFIG_PARAMS
*StdHeader
= ConfigPtr
;
57 if (StdHeader
->Func
== AMD_INIT_ENV
) {
58 FCH_DATA_BLOCK
*FchParams_env
= (FCH_DATA_BLOCK
*)FchData
;
59 printk(BIOS_DEBUG
, "Fch OEM config in INIT ENV ");
61 if (IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM
))
62 oem_fan_control(FchParams_env
);
64 /* XHCI configuration */
65 if (IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE
))
66 FchParams_env
->Usb
.Xhci0Enable
= TRUE
;
68 FchParams_env
->Usb
.Xhci0Enable
= FALSE
;
69 FchParams_env
->Usb
.Xhci1Enable
= FALSE
;
71 /* SATA configuration */
72 FchParams_env
->Sata
.SataClass
= CONFIG_STONEYRIDGE_SATA_MODE
;
73 switch ((SATA_CLASS
)CONFIG_STONEYRIDGE_SATA_MODE
) {
78 FchParams_env
->Sata
.SataIdeMode
= FALSE
;
81 case SataIde2Ahci7804
:
82 default: /* SataNativeIde */
83 FchParams_env
->Sata
.SataIdeMode
= TRUE
;
87 /* Platform updates */
88 platform_FchParams_env(FchParams_env
);
90 printk(BIOS_DEBUG
, "Done\n");
96 AGESA_STATUS
agesa_ReadSpd(UINT32 Func
, UINTN Data
, VOID
*ConfigPtr
)
100 DEVTREE_CONST
struct device
*dev
;
101 DEVTREE_CONST
struct soc_amd_stoneyridge_config
*conf
;
102 AGESA_READ_SPD_PARAMS
*info
= ConfigPtr
;
105 return AGESA_UNSUPPORTED
;
107 dev
= dev_find_slot(0, DCT_DEVFN
);
111 conf
= dev
->chip_info
;
115 if (info
->SocketId
>= ARRAY_SIZE(conf
->spd_addr_lookup
))
117 if (info
->MemChannelId
>= ARRAY_SIZE(conf
->spd_addr_lookup
[0]))
119 if (info
->DimmId
>= ARRAY_SIZE(conf
->spd_addr_lookup
[0][0]))
122 spd_address
= conf
->spd_addr_lookup
123 [info
->SocketId
][info
->MemChannelId
][info
->DimmId
];
124 if (spd_address
== 0)
127 err
= mainboard_read_spd(spd_address
, (void *)info
->Buffer
,
128 CONFIG_DIMM_SPD_SIZE
);
130 /* Read the SPD if the mainboard didn't fill the buffer */
131 if (err
|| (*info
->Buffer
== 0))
132 err
= sb_read_spd(spd_address
, (void *)info
->Buffer
,
133 CONFIG_DIMM_SPD_SIZE
);
138 return AGESA_SUCCESS
;
141 AGESA_STATUS
agesa_HaltThisAp(UINT32 Func
, UINTN Data
, VOID
*ConfigPtr
)
143 AGESA_HALT_THIS_AP_PARAMS
*info
= ConfigPtr
;
146 if (info
->PrimaryCore
== TRUE
)
147 return AGESA_UNSUPPORTED
; /* force normal path */
148 if (info
->ExecWbinvd
== TRUE
)
150 if (info
->CacheEn
== TRUE
)
153 ap_teardown_car(flags
); /* does not return */
155 /* Should never reach here */
156 return AGESA_UNSUPPORTED
;
159 /* Allow mainboards to fill the SPD buffer */
160 __weak
int mainboard_read_spd(uint8_t spdAddress
, char *buf
,
163 printk(BIOS_DEBUG
, "WEAK: %s/%s called\n", __FILE__
, __func__
);
164 return -1; /* SPD not read */