| commit | 4821789e7cfb090fcc0bf9814852ffa7258ac96d | |
| author | Martin Roth <martinroth@chromium.org> | |
| Wed, 2 May 2018 21:15:45 +0000 (2 15:15 -0600) | ||
| committer | Martin Roth <martinroth@google.com> | |
| Fri, 4 May 2018 01:04:15 +0000 (4 01:04 +0000) | ||
| tree | 8c2087f3c61603b891abc6c56f6f22c32323be8c | treesnapshot (tar.gz zip) |
| parent | 59114579a24c3371b98f3205fd668e3a0257ab34 | commitdiff |
soc/amd/stoneyridge: Remove USB30PortInit setting
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
| src/soc/amd/stoneyridge/BiosCallOuts.c | diffblobblamehistory |