src/soc/intel/skylake/Kconfig

   1 config SOC_INTEL_SKYLAKE
   2         bool
   3         help
   4           Intel Skylake support
   5
   6 config SOC_INTEL_KABYLAKE
   7         bool
   8         default n
   9         select SOC_INTEL_SKYLAKE
  10         help
  11           Intel Kabylake support
  12
  13 if SOC_INTEL_SKYLAKE
  14
  15 config CPU_SPECIFIC_OPTIONS
  16         def_bool y
  17         select ACPI_INTEL_HARDWARE_SLEEP_VALUES
  18         select ACPI_NHLT
  19         select ARCH_BOOTBLOCK_X86_32
  20         select ARCH_RAMSTAGE_X86_32
  21         select ARCH_ROMSTAGE_X86_32
  22         select ARCH_VERSTAGE_X86_32
  23         select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
  24         select BOOT_DEVICE_SUPPORTS_WRITES
  25         select CACHE_MRC_SETTINGS
  26         select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
  27         select COLLECT_TIMESTAMPS
  28         select COMMON_FADT
  29         select CPU_INTEL_COMMON
  30         select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
  31         select C_ENVIRONMENT_BOOTBLOCK
  32         select FSP_M_XIP if MAINBOARD_USES_FSP2_0
  33         select FSP_T_XIP if FSP_CAR
  34         select GENERIC_GPIO_LIB
  35         select HAVE_FSP_GOP
  36         select INTEL_DESCRIPTOR_MODE_CAPABLE
  37         select HAVE_MONOTONIC_TIMER
  38         select HAVE_SMI_HANDLER
  39         select INTEL_CAR_NEM_ENHANCED
  40         select INTEL_GMA_ACPI
  41         select IOAPIC
  42         select MRC_SETTINGS_PROTECT
  43         select NO_FIXED_XIP_ROM_SIZE
  44         select PARALLEL_MP
  45         select PARALLEL_MP_AP_WORK
  46         select PCIEX_LENGTH_64MB
  47         select REG_SCRIPT
  48         select SA_ENABLE_DPR
  49         select SMM_TSEG
  50         select SMP
  51         select PMC_GLOBAL_RESET_ENABLE_LOCK
  52         select SOC_INTEL_COMMON
  53         select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
  54         select SOC_INTEL_COMMON_BLOCK
  55         select SOC_INTEL_COMMON_BLOCK_CAR
  56         select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
  57         select SOC_INTEL_COMMON_BLOCK_CPU
  58         select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
  59         select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT
  60         select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS
  61         select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
  62         select SOC_INTEL_COMMON_BLOCK_GSPI
  63         select SOC_INTEL_COMMON_BLOCK_HDA
  64         select SOC_INTEL_COMMON_BLOCK_SA
  65         select SOC_INTEL_COMMON_BLOCK_SGX
  66         select SOC_INTEL_COMMON_BLOCK_SMM
  67         select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
  68         select SOC_INTEL_COMMON_BLOCK_UART
  69         select SOC_INTEL_COMMON_PCH_BASE
  70         select SOC_INTEL_COMMON_NHLT
  71         select SOC_INTEL_COMMON_RESET
  72         select SSE2
  73         select SUPPORT_CPU_UCODE_IN_CBFS
  74         select TSC_CONSTANT_RATE
  75         select TSC_MONOTONIC_TIMER
  76         select TSC_SYNC_MFENCE
  77         select UDELAY_TSC
  78
  79 config CPU_INTEL_NUM_FIT_ENTRIES
  80         int
  81         default 10
  82
  83 config MAINBOARD_USES_FSP2_0
  84         bool
  85         default n
  86
  87 config USE_FSP2_0_DRIVER
  88         def_bool y
  89         depends on MAINBOARD_USES_FSP2_0
  90         select PLATFORM_USES_FSP2_0
  91         select UDK_2015_BINDING
  92         select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
  93         select POSTCAR_CONSOLE
  94         select POSTCAR_STAGE
  95
  96 config USE_FSP1_1_DRIVER
  97         def_bool y
  98         depends on !MAINBOARD_USES_FSP2_0
  99         select PLATFORM_USES_FSP1_1
 100         select DISPLAY_FSP_ENTRY_POINTS
 101         select SKIP_FSP_CAR
 102
 103 config CHROMEOS
 104         select CHROMEOS_RAMOOPS_DYNAMIC
 105
 106 config VBOOT
 107         select VBOOT_EC_SLOW_UPDATE if VBOOT_EC_SOFTWARE_SYNC
 108         select VBOOT_SEPARATE_VERSTAGE
 109         select VBOOT_OPROM_MATTERS
 110         select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT
 111         select VBOOT_STARTS_IN_BOOTBLOCK
 112         select VBOOT_VBNV_CMOS
 113         select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
 114
 115 config CBFS_SIZE
 116         hex
 117         default 0x200000
 118
 119 config CPU_ADDR_BITS
 120         int
 121         default 36
 122
 123 config DCACHE_RAM_BASE
 124         hex
 125         default 0xfef00000
 126
 127 config DCACHE_RAM_SIZE
 128         hex
 129         default 0x40000
 130         help
 131           The size of the cache-as-ram region required during bootblock
 132           and/or romstage.
 133
 134 config DCACHE_BSP_STACK_SIZE
 135         hex
 136         default 0x4000
 137         help
 138           The amount of anticipated stack usage in CAR by bootblock and
 139           other stages.
 140
 141 config C_ENV_BOOTBLOCK_SIZE
 142         hex
 143         default 0xC000
 144
 145 config EXCLUDE_NATIVE_SD_INTERFACE
 146         bool
 147         default n
 148         help
 149           If you set this option to n, will not use native SD controller.
 150
 151 config HEAP_SIZE
 152         hex
 153         default 0x80000
 154
 155 config IED_REGION_SIZE
 156         hex
 157         default 0x400000
 158
 159 config PCR_BASE_ADDRESS
 160         hex
 161         default 0xfd000000
 162         help
 163           This option allows you to select MMIO Base Address of sideband bus.
 164
 165 config SMM_RESERVED_SIZE
 166         hex
 167         default 0x200000
 168
 169 config SMM_TSEG_SIZE
 170         hex
 171         default 0x800000
 172
 173 config VGA_BIOS_ID
 174         string
 175         default "8086,0406"
 176
 177 config SKYLAKE_SOC_PCH_H
 178         bool
 179         default n
 180         help
 181           Choose this option if you have a PCH-H chipset.
 182
 183 config NHLT_DMIC_2CH
 184         bool
 185         default n
 186         help
 187           Include DSP firmware settings for 2 channel DMIC array.
 188
 189 config NHLT_DMIC_4CH
 190         bool
 191         default n
 192         help
 193           Include DSP firmware settings for 4 channel DMIC array.
 194
 195 config NHLT_NAU88L25
 196         bool
 197         default n
 198         help
 199           Include DSP firmware settings for nau88l25 headset codec.
 200
 201 config NHLT_MAX98357
 202         bool
 203         default n
 204         help
 205           Include DSP firmware settings for max98357 amplifier.
 206
 207 config NHLT_MAX98373
 208         bool
 209         default n
 210         help
 211           Include DSP firmware settings for max98373 amplifier.
 212
 213 config NHLT_SSM4567
 214         bool
 215         default n
 216         help
 217           Include DSP firmware settings for ssm4567 smart amplifier.
 218
 219 config NHLT_RT5514
 220         bool
 221         default n
 222         help
 223           Include DSP firmware settings for rt5514 DSP.
 224
 225 config NHLT_RT5663
 226         bool
 227         default n
 228         help
 229           Include DSP firmware settings for rt5663 headset codec.
 230
 231 config NHLT_MAX98927
 232         bool
 233         default n
 234         help
 235           Include DSP firmware settings for max98927 amplifier.
 236
 237 config NHLT_DA7219
 238         bool
 239         default n
 240         help
 241           Include DSP firmware settings for DA7219 headset codec.
 242
 243 config FSP_HEADER_PATH
 244         string "Location of FSP headers"
 245         depends on MAINBOARD_USES_FSP2_0
 246         # Use KabylakeFsp for both Skylake and Kabylake as it supports both.
 247         # SkylakeFsp is FSP 1.1 and therefore incompatible.
 248         default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE
 249         default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE
 250
 251 config FSP_FD_PATH
 252         string
 253         depends on FSP_USE_REPO
 254         default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE
 255         default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE
 256
 257 config SPI_FLASH_INCLUDE_ALL_DRIVERS
 258         bool
 259         default n
 260
 261 config MAX_ROOT_PORTS
 262         int
 263         default 24 if PLATFORM_USES_FSP2_0
 264         default 20 if PLATFORM_USES_FSP1_1
 265
 266 config NO_FADT_8042
 267         bool
 268         default n
 269         help
 270           Choose this option if you want to disable 8042 Keyboard
 271
 272 config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 273         int
 274         default 120
 275
 276 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 277         int
 278         default SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ
 279
 280 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 281         int
 282         default 2
 283
 284 config SOC_INTEL_I2C_DEV_MAX
 285         int
 286         default 6
 287
 288 config CPU_BCLK_MHZ
 289         int
 290         default 100
 291
 292 # Clock divider parameters for 115200 baud rate
 293 config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL
 294         hex
 295         default 0x30
 296
 297 config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
 298         hex
 299         default 0xc35
 300
 301 config IFD_CHIPSET
 302         string
 303         default "sklkbl"
 304
 305 endif