src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable deep Sx states
   4         register "deep_s3_enable_ac" = "0"
   5         register "deep_s3_enable_dc" = "0"
   6         register "deep_s5_enable_ac" = "0"
   7         register "deep_s5_enable_dc" = "0"
   8         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
   9
  10         register "eist_enable" = "1"
  11
  12         # Set the Thermal Control Circuit (TCC) activaction value to 95C
  13         # even though FSP integration guide says to set it to 100C for SKL-U
  14         # (offset at 0), because when the TCC activates at 100C, the CPU
  15         # will have already shut itself down from overheating protection.
  16         register "tcc_offset" = "5" # TCC of 95C
  17
  18         # GPE configuration
  19         # Note that GPE events called out in ASL code rely on this
  20         # route. i.e. If this route changes then the affected GPE
  21         # offset bits also need to be changed.
  22         register "gpe0_dw0" = "GPP_C"
  23         register "gpe0_dw1" = "GPP_D"
  24         register "gpe0_dw2" = "GPP_E"
  25
  26         # EC host command ranges are in 0x380-0x383 & 0x80-0x8f
  27         register "gen1_dec" = "0x00000381"
  28         register "gen2_dec" = "0x000c0081"
  29
  30         # Enable "Intel Speed Shift Technology"
  31         register "speed_shift_enable" = "1"
  32
  33         # Disable DPTF
  34         register "dptf_enable" = "0"
  35
  36         # FSP Configuration
  37         register "ProbelessTrace" = "0"
  38         register "EnableLan" = "0"
  39         register "EnableSata" = "1"
  40         register "SataSalpSupport" = "0"
  41         register "SataMode" = "0"
  42         register "SataPortsEnable[0]" = "1"
  43         register "SataPortsEnable[1]" = "0"
  44         register "SataPortsEnable[2]" = "1"
  45         register "SataPortsDevSlp[0]" = "0"
  46         register "SataPortsDevSlp[2]" = "0"
  47         register "SataSpeedLimit" = "2"
  48         register "EnableAzalia" = "1"
  49         register "DspEnable" = "0"
  50         register "IoBufferOwnership" = "0"
  51         register "EnableTraceHub" = "0"
  52         register "SsicPortEnable" = "0"
  53         register "SmbusEnable" = "1"
  54         register "Cio2Enable" = "0"
  55         register "ScsEmmcEnabled" = "0"
  56         register "ScsEmmcHs400Enabled" = "0"
  57         register "ScsSdCardEnabled" = "0"
  58         register "PttSwitch" = "0"
  59         register "InternalGfx" = "1"
  60         register "SkipExtGfxScan" = "1"
  61         register "Device4Enable" = "1"
  62         register "HeciEnabled" = "0"
  63         register "SaGv" = "3"
  64         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  65         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  66         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  67         register "PmConfigSlpAMinAssert" = "3"          # 2s
  68         register "PmTimerDisabled" = "0"
  69
  70         # EC/KBC requires continuous mode
  71         register "serirq_mode" = "SERIRQ_CONTINUOUS"
  72
  73         register "pirqa_routing" = "PCH_IRQ11"
  74         register "pirqb_routing" = "PCH_IRQ10"
  75         register "pirqc_routing" = "PCH_IRQ11"
  76         register "pirqd_routing" = "PCH_IRQ11"
  77         register "pirqe_routing" = "PCH_IRQ11"
  78         register "pirqf_routing" = "PCH_IRQ11"
  79         register "pirqg_routing" = "PCH_IRQ11"
  80         register "pirqh_routing" = "PCH_IRQ11"
  81
  82         # VR Settings Configuration for 4 Domains
  83         #+----------------+-----------+-----------+-------------+----------+
  84         #| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
  85         #+----------------+-----------+-----------+-------------+----------+
  86         #| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
  87         #| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
  88         #| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
  89         #| Psi3Enable     | 1         | 1         | 1           | 1        |
  90         #| Psi4Enable     | 1         | 1         | 1           | 1        |
  91         #| ImonSlope      | 0         | 0         | 0           | 0        |
  92         #| ImonOffset     | 0         | 0         | 0           | 0        |
  93         #| IccMax         | 7A        | 34A       | 35A         | 35A      |
  94         #| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
  95         #| AC LoadLine    | 15 mOhm   | 5.7 mOhm  | 5.2 mOhm    | 5.2 mOhm |
  96         #| DC LoadLine    | 14.3 mOhm | 4.83 mOhm | 4.2 mOhm    | 4.2 mOhm |
  97         #+----------------+-----------+-----------+-------------+----------+
  98         register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
  99                 .vr_config_enable = 1,
 100                 .psi1threshold = VR_CFG_AMP(20),
 101                 .psi2threshold = VR_CFG_AMP(4),
 102                 .psi3threshold = VR_CFG_AMP(1),
 103                 .psi3enable = 1,
 104                 .psi4enable = 1,
 105                 .imon_slope = 0x0,
 106                 .imon_offset = 0x0,
 107                 .icc_max = VR_CFG_AMP(7),
 108                 .voltage_limit = 1520,
 109                 .ac_loadline = 1500,
 110                 .dc_loadline = 1430,
 111         }"
 112
 113         register "domain_vr_config[VR_IA_CORE]" = "{
 114                 .vr_config_enable = 1,
 115                 .psi1threshold = VR_CFG_AMP(20),
 116                 .psi2threshold = VR_CFG_AMP(5),
 117                 .psi3threshold = VR_CFG_AMP(1),
 118                 .psi3enable = 1,
 119                 .psi4enable = 1,
 120                 .imon_slope = 0x0,
 121                 .imon_offset = 0x0,
 122                 .icc_max = VR_CFG_AMP(34),
 123                 .voltage_limit = 1520,
 124                 .ac_loadline = 570,
 125                 .dc_loadline = 483,
 126         }"
 127
 128         register "domain_vr_config[VR_GT_UNSLICED]" = "{
 129                 .vr_config_enable = 1,
 130                 .psi1threshold = VR_CFG_AMP(20),
 131                 .psi2threshold = VR_CFG_AMP(5),
 132                 .psi3threshold = VR_CFG_AMP(1),
 133                 .psi3enable = 1,
 134                 .psi4enable = 1,
 135                 .imon_slope = 0x0,
 136                 .imon_offset = 0x0,
 137                 .icc_max = VR_CFG_AMP(35),
 138                 .voltage_limit = 1520,
 139                 .ac_loadline = 520,
 140                 .dc_loadline = 420,
 141         }"
 142
 143         register "domain_vr_config[VR_GT_SLICED]" = "{
 144                 .vr_config_enable = 1,
 145                 .psi1threshold = VR_CFG_AMP(20),
 146                 .psi2threshold = VR_CFG_AMP(5),
 147                 .psi3threshold = VR_CFG_AMP(1),
 148                 .psi3enable = 1,
 149                 .psi4enable = 1,
 150                 .imon_slope = 0x0,
 151                 .imon_offset = 0x0,
 152                 .icc_max = VR_CFG_AMP(35),
 153                 .voltage_limit = 1520,
 154                 .ac_loadline = 520,
 155                 .dc_loadline = 420,
 156         }"
 157
 158         # Enable Root Ports 5 and 9
 159         register "PcieRpEnable[4]" = "1"
 160         register "PcieRpEnable[8]" = "1"
 161         # Enable CLKREQ# for RP9
 162         register "PcieRpClkReqSupport[8]" = "0"
 163         # ClkReq for NVMe - Bruteforced (no other value works)
 164         register "PcieRpClkReqNumber[8]" = "2"
 165
 166         register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)"  # Type-C Port
 167         register "usb2_ports[1]" = "USB2_PORT_MID(OC1)"         # Type-A Port (right)
 168         register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"         # Type-A Port (right)
 169         register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)"        # Type-A Port (left)
 170         register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)"        # Type-A Port (left)
 171         register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)"     # Bluetooth
 172         register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)"    # Camera
 173         register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)"    # SD
 174
 175         # OC0 should be for Type-C but it seems to not have been wired, according to
 176         # the available schematics, even though it is labeled as USB_OC_TYPEC.
 177         register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
 178         register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Port (right)
 179         register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"     # Type-A Port (right)
 180         register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
 181
 182         # PL2 override 25W
 183         register "tdp_pl2_override" = "25"
 184
 185         # Send an extra VR mailbox command for the PS4 exit issue
 186         register "SendVrMbxCmd" = "2"
 187
 188         # Lock Down
 189         register "common_soc_config" = "{
 190                 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
 191         }"
 192
 193         device cpu_cluster 0 on
 194                 device lapic 0 on end
 195         end
 196         device domain 0 on
 197                 device pci 00.0 on  end # Host Bridge
 198                 device pci 02.0 on  end # Integrated Graphics Device
 199                 device pci 14.0 on  end # USB xHCI
 200                 device pci 14.1 on  end # USB xDCI (OTG)
 201                 device pci 14.2 on  end # Thermal Subsystem
 202                 device pci 16.0 on  end # Management Engine Interface 1
 203                 device pci 16.1 off end # Management Engine Interface 2
 204                 device pci 16.2 off end # Management Engine IDE-R
 205                 device pci 16.3 off end # Management Engine KT Redirection
 206                 device pci 16.4 off end # Management Engine Interface 3
 207                 device pci 17.0 on  end # SATA
 208                 device pci 1c.0 on  end # PCI Express Port 1
 209                 device pci 1c.1 off end # PCI Express Port 2
 210                 device pci 1c.2 off end # PCI Express Port 3
 211                 device pci 1c.3 off end # PCI Express Port 4
 212                 device pci 1c.4 on  end # PCI Express Port 5
 213                 device pci 1c.5 off end # PCI Express Port 6
 214                 device pci 1c.6 off end # PCI Express Port 7
 215                 device pci 1c.7 off end # PCI Express Port 8
 216                 device pci 1d.0 on  end # PCI Express Port 9
 217                 device pci 1d.1 off end # PCI Express Port 10
 218                 device pci 1d.2 off end # PCI Express Port 11
 219                 device pci 1d.3 off end # PCI Express Port 12
 220                 device pci 1f.0 on
 221                         chip ec/purism/librem
 222                                 device pnp 0c09.0 on end
 223                         end
 224                         chip drivers/pc80/tpm
 225                                 device pnp 0c31.0 on end
 226                         end
 227                 end # LPC Interface
 228                 device pci 1f.1 on  end # P2SB
 229                 device pci 1f.2 on  end # Power Management Controller
 230                 device pci 1f.3 on  end # Intel HDA
 231                 device pci 1f.4 on  end # SMBus
 232                 device pci 1f.5 on  end # PCH SPI
 233                 device pci 1f.6 off end # GbE
 234         end
 235 end