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soc/intel/skylake: Unify serial IRQ options
[coreboot.git] / src / mainboard / intel / saddlebrook / devicetree.cb
blob8f78249b3b2c02c7c7bfb335184bdeb64bdf21a2
1 ##
2 ## This file is part of the coreboot project.
3 ##
4 ## Copyright (C) 2017 Intel Corporation.
5 ##
6 ## This program is free software; you can redistribute it and/or modify
7 ## it under the terms of the GNU General Public License as published by
8 ## the Free Software Foundation; version 2 of the License.
9 ##
10 ## This program is distributed in the hope that it will be useful,
11 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
12 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 ## GNU General Public License for more details.
14 ##
15
16 chip soc/intel/skylake
17
18 # Enable deep Sx states
19 register "deep_s5_enable_ac" = "0"
20 register "deep_s5_enable_dc" = "0"
21 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
22
23 # GPE configuration
24 # Note that GPE events called out in ASL code rely on this
25 # route. i.e. If this route changes then the affected GPE
26 # offset bits also need to be changed.
27 register "gpe0_dw0" = "GPP_B"
28 register "gpe0_dw1" = "GPP_D"
29 register "gpe0_dw2" = "GPP_E"
30
31 # Enable "Intel Speed Shift Technology"
32 register "speed_shift_enable" = "1"
33
34 # FSP Configuration
35 register "EnableAzalia" = "1"
36 register "DspEnable" = "1"
37 register "IoBufferOwnership" = "3"
38 register "SmbusEnable" = "1"
39 register "ScsEmmcEnabled" = "0"
40 register "ScsEmmcHs400Enabled" = "0"
41 register "ScsSdCardEnabled" = "0"
42 register "InternalGfx" = "1"
43 register "SkipExtGfxScan" = "1"
44 register "Device4Enable" = "0"
45 register "Heci3Enabled" = "0"
46
47 register "SaGv" = "3"
48 register "PmTimerDisabled" = "0"
49
50 # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
51 # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
52 register "PmConfigSlpS3MinAssert" = "0x02"
53
54 # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
55 register "PmConfigSlpS4MinAssert" = "0x04"
56
57 # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
58 register "PmConfigSlpSusMinAssert" = "0x03"
59
60 # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
61 register "PmConfigSlpAMinAssert" = "0x03"
62
63 register "serirq_mode" = "SERIRQ_CONTINUOUS"
64
65 # VR Settings Configuration for 5 Domains
66 #+----------------+-------+-------+-------------+-------------+-------+
67 #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
68 #+----------------+-------+-------+-------------+-------------+-------+
69 #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
70 #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
71 #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
72 #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
73 #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
74 #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
75 #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
76 #| IccMax | 7A | 34A | 34A | 35A | 35A |
77 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
78 #+----------------+-------+-------+-------------+-------------+-------+
79 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
80 .vr_config_enable = 1, \
81 .psi1threshold = 0x50, \
82 .psi2threshold = 0x10, \
83 .psi3threshold = 0x4, \
84 .psi3enable = 1, \
85 .psi4enable = 1, \
86 .imon_slope = 0x0, \
87 .imon_offset = 0x0, \
88 .icc_max = 0x1C, \
89 .voltage_limit = 0x5F0 \
90 }"
91
92 register "domain_vr_config[VR_IA_CORE]" = "{
93 .vr_config_enable = 1, \
94 .psi1threshold = 0x50, \
95 .psi2threshold = 0x14, \
96 .psi3threshold = 0x4, \
97 .psi3enable = 1, \
98 .psi4enable = 1, \
99 .imon_slope = 0x0, \
100 .imon_offset = 0x0, \
101 .icc_max = 0x88, \
102 .voltage_limit = 0x5F0 \
103 }"
104 register "domain_vr_config[VR_RING]" = "{
105 .vr_config_enable = 1, \
106 .psi1threshold = 0x50, \
107 .psi2threshold = 0x14, \
108 .psi3threshold = 0x4, \
109 .psi3enable = 1, \
110 .psi4enable = 1, \
111 .imon_slope = 0x0, \
112 .imon_offset = 0x0, \
113 .icc_max = 0x88, \
114 .voltage_limit = 0x5F0, \
115 }"
116
117 register "domain_vr_config[VR_GT_UNSLICED]" = "{
118 .vr_config_enable = 1, \
119 .psi1threshold = 0x50, \
120 .psi2threshold = 0x14, \
121 .psi3threshold = 0x4, \
122 .psi3enable = 1, \
123 .psi4enable = 1, \
124 .imon_slope = 0x0, \
125 .imon_offset = 0x0, \
126 .icc_max = 0x8C ,\
127 .voltage_limit = 0x5F0 \
128 }"
129
130 register "domain_vr_config[VR_GT_SLICED]" = "{
131 .vr_config_enable = 1, \
132 .psi1threshold = 0x50, \
133 .psi2threshold = 0x14, \
134 .psi3threshold = 0x4, \
135 .psi3enable = 1, \
136 .psi4enable = 1, \
137 .imon_slope = 0x0, \
138 .imon_offset = 0x0, \
139 .icc_max = 0x8C, \
140 .voltage_limit = 0x5F0 \
141 }"
142
143 # Skip coreboot MP Init
144 register "common_soc_config" = "{
145 .use_fsp_mp_init = 1,
146 }"
147
148 # Enable x1 slot
149 register "PcieRpEnable[7]" = "1"
150 register "PcieRpClkReqSupport[7]" = "1"
151 register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3
152
153 # Enable x4 slot
154 register "PcieRpEnable[8]" = "1"
155 register "PcieRpClkReqSupport[8]" = "1"
156 register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4
157
158 # Enable Root port 6 and 13.
159 register "PcieRpEnable[5]" = "1"
160 register "PcieRpEnable[12]" = "1"
161
162 # Enable CLKREQ#
163 register "PcieRpClkReqSupport[5]" = "1"
164 register "PcieRpClkReqSupport[12]" = "1"
165
166 # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#
167 register "PcieRpClkReqNumber[5]" = "0"
168 register "PcieRpClkReqNumber[12]" = "1"
169
170 register "EnableLan" = "1"
171
172 # USB related
173 register "SsicPortEnable" = "1"
174
175 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG
176 register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad
177 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT
178 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel
179 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
180 register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel
181 register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel
182 register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
183 register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)
184 register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
185 register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK
186 register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor
187 register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
188 register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn
189
190 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG
191 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
192 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex
193 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM
194 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
195 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
196 register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel
197 register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
198 register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn
199 register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK
200
201 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
202
203 # Must leave UART0 enabled or SD/eMMC will not work as PCI
204
205 register "pirqa_routing" = "0x0b"
206 register "pirqb_routing" = "0x0a"
207 register "pirqc_routing" = "0x0b"
208 register "pirqd_routing" = "0x0b"
209 register "pirqe_routing" = "0x0b"
210 register "pirqf_routing" = "0x0b"
211 register "pirqg_routing" = "0x0b"
212 register "pirqh_routing" = "0x0b"
213
214 register "PmTimerDisabled" = "0"
215
216 register "EnableSata" = "1"
217 register "SataSalpSupport" = "1"
218 register "SataPortsEnable" = "{ \
219 [0] = 1, \
220 [1] = 1, \
221 [2] = 1, \
222 [3] = 1, \
223 [4] = 1, \
224 [5] = 1, \
225 [6] = 1, \
226 [7] = 1, \
227 }"
228 register "SerialIoDevMode" = "{ \
229 [PchSerialIoIndexI2C0] = PchSerialIoPci, \
230 [PchSerialIoIndexI2C1] = PchSerialIoPci, \
231 [PchSerialIoIndexI2C2] = PchSerialIoPci, \
232 [PchSerialIoIndexI2C3] = PchSerialIoPci, \
233 [PchSerialIoIndexI2C4] = PchSerialIoPci, \
234 [PchSerialIoIndexI2C5] = PchSerialIoPci, \
235 [PchSerialIoIndexSpi0] = PchSerialIoPci, \
236 [PchSerialIoIndexSpi1] = PchSerialIoPci, \
237 [PchSerialIoIndexUart0] = PchSerialIoPci, \
238 [PchSerialIoIndexUart1] = PchSerialIoPci, \
239 [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
240 }"
241
242 # PL2 override 25W
243 register "tdp_pl2_override" = "25"
244
245 # Send an extra VR mailbox command for the PS4 exit issue
246 register "SendVrMbxCmd" = "2"
247
248 # Use default SD card detect GPIO configuration
249 #register "sdcard_cd_gpio_default" = "GPP_A7"
250
251 device cpu_cluster 0 on
252 device lapic 0 on end
253 end
254 device domain 0 on
255 device pci 00.0 on end # Host Bridge
256 device pci 02.0 on end # Integrated Graphics Device
257 device pci 14.0 on end # USB xHCI
258 device pci 14.1 off end # USB xDCI (OTG)
259 device pci 14.2 on end # Thermal Subsystem
260 device pci 15.0 on end # I2C #0
261 device pci 15.1 on end # I2C #1
262 device pci 15.2 on end # I2C #2
263 device pci 15.3 on end # I2C #3
264 device pci 16.0 on end # Management Engine Interface 1
265 device pci 16.1 off end # Management Engine Interface 2
266 device pci 16.2 off end # Management Engine IDE-R
267 device pci 16.3 off end # Management Engine KT Redirection
268 device pci 16.4 off end # Management Engine Interface 3
269 device pci 17.0 on end # SATA
270 device pci 19.0 on end # UART #2
271 device pci 19.1 on end # I2C #5
272 device pci 19.2 on end # I2C #4
273 device pci 1c.0 on end # PCI Express Port 1
274 device pci 1c.1 off end # PCI Express Port 2
275 device pci 1c.2 off end # PCI Express Port 3
276 device pci 1c.3 off end # PCI Express Port 4
277 device pci 1c.4 off end # PCI Express Port 5
278 device pci 1c.5 off end # PCI Express Port 6
279 device pci 1c.6 off end # PCI Express Port 7
280 device pci 1c.7 off end # PCI Express Port 8
281 device pci 1d.0 off end # PCI Express Port 9
282 device pci 1d.1 off end # PCI Express Port 10
283 device pci 1d.2 off end # PCI Express Port 11
284 device pci 1d.3 off end # PCI Express Port 12
285 device pci 1e.0 on end # UART #0
286 device pci 1e.1 on end # UART #1
287 device pci 1e.2 on end # GSPI #0
288 device pci 1e.3 on end # GSPI #1
289 device pci 1e.4 off end # eMMC
290 device pci 1e.5 off end # SDIO
291 device pci 1e.6 off end # SDCard
292 device pci 1f.0 on
293 end # LPC Interface
294 device pci 1f.1 on end # P2SB
295 device pci 1f.2 on end # Power Management Controller
296 device pci 1f.3 on end # Intel HDA
297 device pci 1f.4 on end # SMBus
298 device pci 1f.5 on end # PCH SPI
299 device pci 1f.6 on end # GbE
300 end
301 end
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