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soc/intel/skylake: Unify serial IRQ options
[coreboot.git] / src / mainboard / google / glados / variants / asuka / devicetree.cb
blobe0a792d532d977279b7ad2db8e183fa6e2cdcfbf
1 chip soc/intel/skylake
2
3 # Enable deep Sx states
4 register "deep_s3_enable_ac" = "0"
5 register "deep_s3_enable_dc" = "0"
6 register "deep_s5_enable_ac" = "1"
7 register "deep_s5_enable_dc" = "1"
8 register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
9
10 # GPE configuration
11 # Note that GPE events called out in ASL code rely on this
12 # route. i.e. If this route changes then the affected GPE
13 # offset bits also need to be changed.
14 register "gpe0_dw0" = "GPP_B"
15 register "gpe0_dw1" = "GPP_D"
16 register "gpe0_dw2" = "GPP_E"
17
18 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
19 register "gen1_dec" = "0x00fc0801"
20 register "gen2_dec" = "0x000c0201"
21
22 # Enable "Intel Speed Shift Technology"
23 register "speed_shift_enable" = "1"
24
25 # Enable DPTF
26 register "dptf_enable" = "1"
27
28 # FSP Configuration
29 register "EnableAzalia" = "1"
30 register "DspEnable" = "1"
31 register "IoBufferOwnership" = "3"
32 register "SmbusEnable" = "1"
33 register "ScsEmmcEnabled" = "1"
34 register "ScsEmmcHs400Enabled" = "1"
35 register "ScsSdCardEnabled" = "0"
36 register "InternalGfx" = "1"
37 register "SkipExtGfxScan" = "1"
38 register "Device4Enable" = "1"
39 register "HeciEnabled" = "0"
40 register "SaGv" = "3"
41 register "PmConfigSlpS3MinAssert" = "2" # 50ms
42 register "PmConfigSlpS4MinAssert" = "4" # 4s
43 register "PmConfigSlpSusMinAssert" = "3" # 4s
44 register "PmConfigSlpAMinAssert" = "3" # 2s
45 register "PmTimerDisabled" = "1"
46
47 register "pirqa_routing" = "PCH_IRQ11"
48 register "pirqb_routing" = "PCH_IRQ10"
49 register "pirqc_routing" = "PCH_IRQ11"
50 register "pirqd_routing" = "PCH_IRQ11"
51 register "pirqe_routing" = "PCH_IRQ11"
52 register "pirqf_routing" = "PCH_IRQ11"
53 register "pirqg_routing" = "PCH_IRQ11"
54 register "pirqh_routing" = "PCH_IRQ11"
55
56 # VR Settings Configuration for 5 Domains
57 #+----------------+-------+-------+-------------+-------------+-------+
58 #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
59 #+----------------+-------+-------+-------------+-------------+-------+
60 #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
61 #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
62 #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
63 #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
64 #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
65 #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
66 #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
67 #| IccMax | 7A | 34A | 34A | 35A | 35A |
68 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
69 #+----------------+-------+-------+-------------+-------------+-------+
70 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
71 .vr_config_enable = 1,
72 .psi1threshold = VR_CFG_AMP(20),
73 .psi2threshold = VR_CFG_AMP(4),
74 .psi3threshold = VR_CFG_AMP(1),
75 .psi3enable = 1,
76 .psi4enable = 1,
77 .imon_slope = 0x0,
78 .imon_offset = 0x0,
79 .icc_max = VR_CFG_AMP(7),
80 .voltage_limit = 1520,
81 }"
82
83 register "domain_vr_config[VR_IA_CORE]" = "{
84 .vr_config_enable = 1,
85 .psi1threshold = VR_CFG_AMP(20),
86 .psi2threshold = VR_CFG_AMP(5),
87 .psi3threshold = VR_CFG_AMP(1),
88 .psi3enable = 1,
89 .psi4enable = 1,
90 .imon_slope = 0x0,
91 .imon_offset = 0x0,
92 .icc_max = VR_CFG_AMP(34),
93 .voltage_limit = 1520,
94 }"
95
96 register "domain_vr_config[VR_RING]" = "{
97 .vr_config_enable = 1,
98 .psi1threshold = VR_CFG_AMP(20),
99 .psi2threshold = VR_CFG_AMP(5),
100 .psi3threshold = VR_CFG_AMP(1),
101 .psi3enable = 1,
102 .psi4enable = 1,
103 .imon_slope = 0x0,
104 .imon_offset = 0x0,
105 .icc_max = VR_CFG_AMP(34),
106 .voltage_limit = 1520,
107 }"
108
109 register "domain_vr_config[VR_GT_UNSLICED]" = "{
110 .vr_config_enable = 1,
111 .psi1threshold = VR_CFG_AMP(20),
112 .psi2threshold = VR_CFG_AMP(5),
113 .psi3threshold = VR_CFG_AMP(1),
114 .psi3enable = 1,
115 .psi4enable = 1,
116 .imon_slope = 0x0,
117 .imon_offset = 0x0,
118 .icc_max = VR_CFG_AMP(35),
119 .voltage_limit = 1520,
120 }"
121
122 register "domain_vr_config[VR_GT_SLICED]" = "{
123 .vr_config_enable = 1,
124 .psi1threshold = VR_CFG_AMP(20),
125 .psi2threshold = VR_CFG_AMP(5),
126 .psi3threshold = VR_CFG_AMP(1),
127 .psi3enable = 1,
128 .psi4enable = 1,
129 .imon_slope = 0x0,
130 .imon_offset = 0x0,
131 .icc_max = VR_CFG_AMP(35),
132 .voltage_limit = 1520,
133 }"
134
135 # Enable Root port 1
136 register "PcieRpEnable[0]" = "1"
137 # Enable CLKREQ#
138 register "PcieRpClkReqSupport[0]" = "1"
139 # RP 1 uses SRCCLKREQ1#
140 register "PcieRpClkReqNumber[0]" = "1"
141
142 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # Type-C Port 1
143 register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Card Reader
144 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
145 register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" # Type-A Port (board)
146 register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
147 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # PIC MCU
148 register "usb2_ports[8]" = "USB2_PORT_LONG(OC3)" # Type-A Port (board)
149
150 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
151 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card Reader
152 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port (board)
153 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port (board)
154
155 register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
156
157 # Must leave UART0 enabled or SD/eMMC will not work as PCI
158 register "SerialIoDevMode" = "{
159 [PchSerialIoIndexI2C0] = PchSerialIoPci,
160 [PchSerialIoIndexI2C1] = PchSerialIoPci,
161 [PchSerialIoIndexI2C2] = PchSerialIoDisabled,
162 [PchSerialIoIndexI2C3] = PchSerialIoDisabled,
163 [PchSerialIoIndexI2C4] = PchSerialIoPci,
164 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
165 [PchSerialIoIndexSpi0] = PchSerialIoDisabled,
166 [PchSerialIoIndexSpi1] = PchSerialIoDisabled,
167 [PchSerialIoIndexUart0] = PchSerialIoPci,
168 [PchSerialIoIndexUart1] = PchSerialIoDisabled,
169 [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
170 }"
171
172 # PL2 override 25W
173 register "tdp_pl2_override" = "25"
174
175 # Send an extra VR mailbox command for the PS4 exit issue
176 register "SendVrMbxCmd" = "2"
177
178 # Lock Down
179 register "common_soc_config" = "{
180 .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
181 }"
182
183 device cpu_cluster 0 on
184 device lapic 0 on end
185 end
186 device domain 0 on
187 device pci 00.0 on end # Host Bridge
188 device pci 02.0 on end # Integrated Graphics Device
189 device pci 14.0 on end # USB xHCI
190 device pci 14.1 off end # USB xDCI (OTG)
191 device pci 14.2 on end # Thermal Subsystem
192 device pci 15.0 on
193 chip drivers/i2c/generic
194 register "hid" = ""ELAN0001""
195 register "desc" = ""ELAN Touchscreen""
196 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
197 device i2c 10 on end
198 end
199 end # I2C #0
200 device pci 15.1 on
201 chip drivers/i2c/generic
202 register "hid" = ""ELAN0000""
203 register "desc" = ""ELAN Touchpad""
204 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)"
205 register "wake" = "GPE0_DW0_05"
206 device i2c 15 on end
207 end
208 end # I2C #1
209 device pci 15.2 off end # I2C #2
210 device pci 15.3 off end # I2C #3
211 device pci 16.0 on end # Management Engine Interface 1
212 device pci 16.1 off end # Management Engine Interface 2
213 device pci 16.2 off end # Management Engine IDE-R
214 device pci 16.3 off end # Management Engine KT Redirection
215 device pci 16.4 off end # Management Engine Interface 3
216 device pci 17.0 off end # SATA
217 device pci 19.0 on end # UART #2
218 device pci 19.1 off end # I2C #5
219 device pci 19.2 on
220 chip drivers/i2c/nau8825
221 register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F10_IRQ)"
222 register "jkdet_enable" = "1"
223 register "jkdet_pull_enable" = "0" # R389
224 register "jkdet_polarity" = "1" # ActiveLow
225 register "vref_impedance" = "2" # 125kOhm
226 register "micbias_voltage" = "6" # 2.754
227 register "sar_threshold_num" = "4"
228 register "sar_threshold[0]" = "0x08"
229 register "sar_threshold[1]" = "0x12"
230 register "sar_threshold[2]" = "0x26"
231 register "sar_threshold[3]" = "0x73"
232 register "sar_hysteresis" = "0"
233 register "sar_voltage" = "6"
234 register "sar_compare_time" = "1" # 1us
235 register "sar_sampling_time" = "1" # 4us
236 register "short_key_debounce" = "3" # 30ms
237 register "jack_insert_debounce" = "7" # 512ms
238 register "jack_eject_debounce" = "0"
239 device i2c 1a on end
240 end
241 end # I2C #4
242 device pci 1c.0 on
243 chip drivers/intel/wifi
244 register "wake" = "GPE0_DW0_16"
245 device pci 00.0 on end
246 end
247 end # PCI Express Port 1
248 device pci 1c.1 off end # PCI Express Port 2
249 device pci 1c.2 off end # PCI Express Port 3
250 device pci 1c.3 off end # PCI Express Port 4
251 device pci 1c.4 off end # PCI Express Port 5
252 device pci 1c.5 off end # PCI Express Port 6
253 device pci 1c.6 off end # PCI Express Port 7
254 device pci 1c.7 off end # PCI Express Port 8
255 device pci 1d.0 off end # PCI Express Port 9
256 device pci 1d.1 off end # PCI Express Port 10
257 device pci 1d.2 off end # PCI Express Port 11
258 device pci 1d.3 off end # PCI Express Port 12
259 device pci 1e.0 on end # UART #0
260 device pci 1e.1 off end # UART #1
261 device pci 1e.2 off end # GSPI #0
262 device pci 1e.3 off end # GSPI #1
263 device pci 1e.4 on end # eMMC
264 device pci 1e.5 off end # SDIO
265 device pci 1e.6 off end # SDCard
266 device pci 1f.0 on
267 chip drivers/pc80/tpm
268 device pnp 0c31.0 on end
269 end
270 chip ec/google/chromeec
271 device pnp 0c09.0 on end
272 end
273 end # LPC Interface
274 device pci 1f.1 on end # P2SB
275 device pci 1f.2 on end # Power Management Controller
276 device pci 1f.3 on
277 chip drivers/generic/max98357a
278 register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
279 register "sdmode_delay" = "5"
280 device generic 0 on end
281 end
282 end # Intel HDA
283 device pci 1f.4 on end # SMBus
284 device pci 1f.5 on end # PCH SPI
285 device pci 1f.6 off end # GbE
286 end
287 end
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