util/msrtool/intel_core2_later.c

   1 /*
   2  * This file is part of msrtool.
   3  *
   4  * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  18  */
  19
  20 #include "msrtool.h"
  21
  22 int intel_core2_later_probe(const struct targetdef *target) {
  23         struct cpuid_t *id = cpuid();
  24         return ((0x6 == id->family)&(0x17 == id->model));
  25 }
  26
  27 const struct msrdef intel_core2_later_msrs[] = {
  28         {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", {
  29                 { 63, 11, RESERVED },
  30                 { 52, 3, RESERVED },
  31                 { 49, 37, RESERVED },
  32                 { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", PRESENT_DEC, {
  33                         { BITVAL_EOT }
  34                 }},
  35                 { 7, 8, RESERVED },
  36                 { BITS_EOT }
  37         }},
  38         { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", {
  39                 { 63, 41, RESERVED },
  40                 { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, {
  41                         { BITVAL_EOT }
  42                 }},
  43                 { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, {
  44                         { BITVAL_EOT }
  45                 }},
  46                 { 19, 1, RESERVED },
  47                 { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, {
  48                         { MSR1(0), "Integer ratio" },
  49                         { MSR1(1), "Non-integer ratio" },
  50                         { BITVAL_EOT }
  51                 }},
  52                 { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, {
  53                         { BITVAL_EOT }
  54                 }},
  55                 { 15, 1, RESERVED },
  56                 { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, {
  57                         { MSR1(0), "4 GBytes Power on Reset Vector" },
  58                         { MSR1(1), "1 Mbyte Power on Reset Vector" },
  59                         { BITVAL_EOT }
  60                 }},
  61                 { 13, 1, RESERVED },
  62                 { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, {
  63                         { MSR1(0), "BINIT# Observation disabled" },
  64                         { MSR1(1), "BINIT# Observation enabled" },
  65                         { BITVAL_EOT }
  66                 }},
  67                 { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, {
  68                         { MSR1(0), "Intel TXT Capable Chipset not present" },
  69                         { MSR1(1), "Intel TXT Capable Chipset present" },
  70                         { BITVAL_EOT }
  71                 }},
  72                 { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, {
  73                         { MSR1(0), "MCERR# Observation disabled" },
  74                         { MSR1(1), "MCERR# Observation enabled" },
  75                         { BITVAL_EOT }
  76                 }},
  77                 { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, {
  78                         { MSR1(0), "Execute BIST disabled" },
  79                         { MSR1(1), "Execute BIST enabled" },
  80                         { BITVAL_EOT }
  81                 }},
  82                 { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, {
  83                         { MSR1(0), "Output Tri-state disabled" },
  84                         { MSR1(1), "Output Tri-state enabled" },
  85                         { BITVAL_EOT }
  86                 }},
  87                 { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, {
  88                         { MSR1(0), "BINIT# Driver disabled" },
  89                         { MSR1(1), "BINIT# Driver enabled" },
  90                         { BITVAL_EOT }
  91                 }},
  92                 { 6, 2, RESERVED },
  93                 { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, {
  94                         { MSR1(0), "Address parity disabled" },
  95                         { MSR1(1), "Address parity enabled" },
  96                         { BITVAL_EOT }
  97                 }},
  98                 { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, {
  99                         { MSR1(0), "MCERR# Driver disabled" },
 100                         { MSR1(1), "MCERR# Driver enabled" },
 101                         { BITVAL_EOT }
 102                 }},
 103                 { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, {
 104                         { MSR1(0), "Response Error Checking disabled" },
 105                         { MSR1(1), "Response Error Checking enabled" },
 106                         { BITVAL_EOT }
 107                 }},
 108                 { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, {
 109                         { MSR1(0), "Data error checking disabled" },
 110                         { MSR1(1), "Data error checking enabled" },
 111                         { BITVAL_EOT }
 112                 }},
 113                 { 0, 1, RESERVED },
 114                 { BITS_EOT }
 115         }},
 116         {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", {
 117                 { BITS_EOT }
 118         }},
 119         {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", {
 120                 { BITS_EOT }
 121         }},
 122         {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
 123                 { BITS_EOT }
 124         }},
 125         {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
 126                 { BITS_EOT }
 127         }},
 128
 129         // Per core msrs
 130
 131         {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
 132                 { BITS_EOT }
 133         }},
 134         {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
 135                 { BITS_EOT }
 136         }},
 137         {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", {
 138                 { BITS_EOT }
 139         }},
 140         {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", {
 141                 { BITS_EOT }
 142         }},
 143         {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
 144                 { BITS_EOT }
 145         }},
 146         {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
 147                 { BITS_EOT }
 148         }},
 149         {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
 150                 { BITS_EOT }
 151         }},
 152         {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", {
 153                 { BITS_EOT }
 154         }},
 155         {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
 156                 { BITS_EOT }
 157         }},
 158         {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", {
 159                 { BITS_EOT }
 160         }},
 161         {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", {
 162                 { BITS_EOT }
 163         }},
 164         {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", {
 165                 { BITS_EOT }
 166         }},
 167         {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", {
 168                 { BITS_EOT }
 169         }},
 170         {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", {
 171                 { BITS_EOT }
 172         }},
 173         {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", {
 174                 { BITS_EOT }
 175         }},
 176         {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
 177                 { BITS_EOT }
 178         }},
 179         {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", {
 180                 { BITS_EOT }
 181         }},
 182         {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", {
 183                 { BITS_EOT }
 184         }},
 185         {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", {
 186                 { BITS_EOT }
 187         }},
 188         {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", {
 189                 { BITS_EOT }
 190         }},
 191         {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
 192                 { BITS_EOT }
 193         }},
 194         {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
 195                 { BITS_EOT }
 196         }},
 197         {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
 198                 { BITS_EOT }
 199         }},
 200         {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
 201                 { BITS_EOT }
 202         }},
 203         {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
 204                 { BITS_EOT }
 205         }},
 206         {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
 207                 { BITS_EOT }
 208         }},
 209         {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
 210                 { BITS_EOT }
 211         }},
 212         {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
 213                 { BITS_EOT }
 214         }},
 215         {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", {
 216                 { BITS_EOT }
 217         }},
 218         {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", {
 219                 { BITS_EOT }
 220         }},
 221         {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
 222                 { BITS_EOT }
 223         }},
 224         {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
 225                 { BITS_EOT }
 226         }},
 227         {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
 228                 { BITS_EOT }
 229         }},
 230         {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
 231                 { BITS_EOT }
 232         }},
 233         {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
 234                 { BITS_EOT }
 235         }},
 236         {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
 237                 { BITS_EOT }
 238         }},
 239         {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
 240                 { BITS_EOT }
 241         }},
 242         {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
 243                 { BITS_EOT }
 244         }},
 245         {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
 246                 { BITS_EOT }
 247         }},
 248         {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
 249                 { BITS_EOT }
 250         }},
 251         {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
 252                 { BITS_EOT }
 253         }},
 254         {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", {
 255                 { BITS_EOT }
 256         }},
 257         {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", {
 258                 { BITS_EOT }
 259         }},
 260         {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", {
 261                 { BITS_EOT }
 262         }},
 263         {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", {
 264                 { BITS_EOT }
 265         }},
 266         {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", {
 267                 { BITS_EOT }
 268         }},
 269         {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", {
 270                 { BITS_EOT }
 271         }},
 272         {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", {
 273                 { BITS_EOT }
 274         }},
 275         {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", {
 276                 { BITS_EOT }
 277         }},
 278         {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", {
 279                 { BITS_EOT }
 280         }},
 281         {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", {
 282                 { BITS_EOT }
 283         }},
 284         {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", {
 285                 { BITS_EOT }
 286         }},
 287         {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", {
 288                 { BITS_EOT }
 289         }},
 290         {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", {
 291                 { BITS_EOT }
 292         }},
 293         {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", {
 294                 { BITS_EOT }
 295         }},
 296         {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", {
 297                 { BITS_EOT }
 298         }},
 299         {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", {
 300                 { BITS_EOT }
 301         }},
 302         {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
 303                 { BITS_EOT }
 304         }},
 305         {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
 306                 { BITS_EOT }
 307         }},
 308         {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
 309                 { BITS_EOT }
 310         }},
 311         {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
 312                 { BITS_EOT }
 313         }},
 314         {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
 315                 { BITS_EOT }
 316         }},
 317         {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
 318                 { BITS_EOT }
 319         }},
 320         {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
 321                 { BITS_EOT }
 322         }},
 323         {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
 324                 { BITS_EOT }
 325         }},
 326         {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
 327                 { BITS_EOT }
 328         }},
 329         {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
 330                 { BITS_EOT }
 331         }},
 332         {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
 333                 { BITS_EOT }
 334         }},
 335         {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
 336                 { BITS_EOT }
 337         }},
 338         {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
 339                 { BITS_EOT }
 340         }},
 341         {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "", {
 342                 { BITS_EOT }
 343         }},
 344         {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "", {
 345                 { BITS_EOT }
 346         }},
 347         {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "", {
 348                 { BITS_EOT }
 349         }},
 350         {0x345, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
 351                 { BITS_EOT }
 352         }},
 353         {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", "", {
 354                 { BITS_EOT }
 355         }},
 356         {0x38e, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", "", {
 357                 { BITS_EOT }
 358         }},
 359         {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", "", {
 360                 { BITS_EOT }
 361         }},
 362         {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", "", {
 363                 { BITS_EOT }
 364         }},
 365         {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "", {
 366                 { BITS_EOT }
 367         }},
 368         {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
 369                 { BITS_EOT }
 370         }},
 371         {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
 372                 { BITS_EOT }
 373         }},
 374         {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
 375                 { BITS_EOT }
 376         }},
 377         {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
 378                 { BITS_EOT }
 379         }},
 380         {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
 381                 { BITS_EOT }
 382         }},
 383         {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
 384                 { BITS_EOT }
 385         }},
 386         {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
 387                 { BITS_EOT }
 388         }},
 389         {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
 390                 { BITS_EOT }
 391         }},
 392         {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
 393                 { BITS_EOT }
 394         }},
 395         {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
 396                 { BITS_EOT }
 397         }},
 398         {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
 399                 { BITS_EOT }
 400         }},
 401         {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
 402                 { BITS_EOT }
 403         }},
 404         {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
 405                 { BITS_EOT }
 406         }},
 407         {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
 408                 { BITS_EOT }
 409         }},
 410         {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
 411                 { BITS_EOT }
 412         }},
 413         {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
 414                 { BITS_EOT }
 415         }},
 416         {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
 417                 { BITS_EOT }
 418         }},
 419         {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
 420                 { BITS_EOT }
 421         }},
 422         {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
 423                 { BITS_EOT }
 424         }},
 425         {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
 426                 { BITS_EOT }
 427         }},
 428         {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
 429                 { BITS_EOT }
 430         }},
 431         {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", {
 432                 { BITS_EOT }
 433         }},
 434         {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", {
 435                 { BITS_EOT }
 436         }},
 437         {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", {
 438                 { BITS_EOT }
 439         }},
 440         {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", {
 441                 { BITS_EOT }
 442         }},
 443         {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", {
 444                 { BITS_EOT }
 445         }},
 446         {0x480, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_BASIC", "", {
 447                 { BITS_EOT }
 448         }},
 449         {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_PINBASED_CTLS", "", {
 450                 { BITS_EOT }
 451         }},
 452         {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_PROCBASED_CTLS", "", {
 453                 { BITS_EOT }
 454         }},
 455         {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", {
 456                 { BITS_EOT }
 457         }},
 458         {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", {
 459                 { BITS_EOT }
 460         }},
 461         {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", {
 462                 { BITS_EOT }
 463         }},
 464         {0x486, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED0", "", {
 465                 { BITS_EOT }
 466         }},
 467         {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", {
 468                 { BITS_EOT }
 469         }},
 470         {0x488, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED0", "", {
 471                 { BITS_EOT }
 472         }},
 473         {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", {
 474                 { BITS_EOT }
 475         }},
 476         {0x48a, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_VMCS_ENUM", "", {
 477                 { BITS_EOT }
 478         }},
 479         {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", {
 480                 { BITS_EOT }
 481         }},
 482         {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
 483                 { BITS_EOT }
 484         }},
 485         {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", {
 486                 { BITS_EOT }
 487         }},
 488         {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", {
 489                 { BITS_EOT }
 490         }},
 491         {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", {
 492                 { BITS_EOT }
 493         }},
 494         {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", {
 495                 { BITS_EOT }
 496         }},
 497         {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", {
 498                 { BITS_EOT }
 499         }},
 500         {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", {
 501                 { BITS_EOT }
 502         }},
 503         {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", {
 504                 { BITS_EOT }
 505         }},
 506         {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", {
 507                 { BITS_EOT }
 508         }},
 509         {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", {
 510                 { BITS_EOT }
 511         }},
 512         {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", {
 513                 { BITS_EOT }
 514         }},
 515         {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", {
 516                 { BITS_EOT }
 517         }},
 518         {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", {
 519                 { BITS_EOT }
 520         }},
 521         {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", {
 522                 { BITS_EOT }
 523         }},
 524         {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", {
 525                 { BITS_EOT }
 526         }},
 527         {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", {
 528                 { BITS_EOT }
 529         }},
 530         {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", {
 531                 { BITS_EOT }
 532         }},
 533         { MSR_EOT }
 534 };
 535
 536