| commit | 3aff1a32087137169fb4165eb2dd11655de27f45 | |
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | |
| Wed, 11 Apr 2012 09:19:03 +0000 (11 12:19 +0300) | ||
| committer | Patrick Georgi <patrick@georgi-clan.de> | |
| Thu, 12 Apr 2012 08:27:34 +0000 (12 10:27 +0200) | ||
| tree | f355095bdb44c137fb2de9eece16e8f366ebe9ff | treesnapshot (tar.gz zip) |
| parent | eb59636cc5875bac98a949f206e5f8c0462be238 | commitdiff |
Convert AOpen DXPL Plus mainboard to CAR
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.
Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.
Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>