util/inteltool/pcie.c

   1 /*
   2  * inteltool - dump all registers on an Intel CPU + chipset based system.
   3  *
   4  * Copyright (C) 2008-2010 by coresystems GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; version 2 of the License.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 #include <stdio.h>
  21 #include <stdlib.h>
  22 #include <inttypes.h>
  23 #include "inteltool.h"
  24
  25 /*
  26  * Egress Port Root Complex MMIO configuration space
  27  */
  28 int print_epbar(struct pci_dev *nb)
  29 {
  30         int i, size = (4 * 1024);
  31         volatile uint8_t *epbar;
  32         uint64_t epbar_phys;
  33
  34         printf("\n============= EPBAR =============\n\n");
  35
  36         switch (nb->device_id) {
  37         case PCI_DEVICE_ID_INTEL_82915:
  38         case PCI_DEVICE_ID_INTEL_82945GM:
  39         case PCI_DEVICE_ID_INTEL_82945GSE:
  40         case PCI_DEVICE_ID_INTEL_82945P:
  41         case PCI_DEVICE_ID_INTEL_82975X:
  42                 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
  43                 break;
  44         case PCI_DEVICE_ID_INTEL_PM965:
  45         case PCI_DEVICE_ID_INTEL_Q965:
  46         case PCI_DEVICE_ID_INTEL_82Q35:
  47         case PCI_DEVICE_ID_INTEL_82G33:
  48         case PCI_DEVICE_ID_INTEL_82Q33:
  49         case PCI_DEVICE_ID_INTEL_X44:
  50         case PCI_DEVICE_ID_INTEL_32X0:
  51         case PCI_DEVICE_ID_INTEL_GS45:
  52         case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
  53         case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
  54                 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
  55                 epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
  56                 break;
  57         case PCI_DEVICE_ID_INTEL_82810:
  58         case PCI_DEVICE_ID_INTEL_82810DC:
  59         case PCI_DEVICE_ID_INTEL_82810E_MC:
  60         case PCI_DEVICE_ID_INTEL_82830M:
  61         case PCI_DEVICE_ID_INTEL_82865:
  62                 printf("This northbridge does not have EPBAR.\n");
  63                 return 1;
  64         default:
  65                 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
  66                 return 1;
  67         }
  68
  69         epbar = map_physical(epbar_phys, size);
  70
  71         if (epbar == NULL) {
  72                 perror("Error mapping EPBAR");
  73                 exit(1);
  74         }
  75
  76         printf("EPBAR = 0x%08" PRIx64 " (MEM)\n\n", epbar_phys);
  77         for (i = 0; i < size; i += 4) {
  78                 if (*(uint32_t *)(epbar + i))
  79                         printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
  80         }
  81
  82         unmap_physical((void *)epbar, size);
  83         return 0;
  84 }
  85
  86 /*
  87  * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
  88  */
  89 int print_dmibar(struct pci_dev *nb)
  90 {
  91         int i, size = (4 * 1024);
  92         volatile uint8_t *dmibar;
  93         uint64_t dmibar_phys;
  94
  95         printf("\n============= DMIBAR ============\n\n");
  96
  97         switch (nb->device_id) {
  98         case PCI_DEVICE_ID_INTEL_82915:
  99         case PCI_DEVICE_ID_INTEL_82945GM:
 100         case PCI_DEVICE_ID_INTEL_82945GSE:
 101         case PCI_DEVICE_ID_INTEL_82945P:
 102         case PCI_DEVICE_ID_INTEL_82975X:
 103                 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
 104                 break;
 105         case PCI_DEVICE_ID_INTEL_PM965:
 106         case PCI_DEVICE_ID_INTEL_Q965:
 107         case PCI_DEVICE_ID_INTEL_82Q35:
 108         case PCI_DEVICE_ID_INTEL_82G33:
 109         case PCI_DEVICE_ID_INTEL_82Q33:
 110         case PCI_DEVICE_ID_INTEL_X44:
 111         case PCI_DEVICE_ID_INTEL_32X0:
 112         case PCI_DEVICE_ID_INTEL_GS45:
 113         case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 114         case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
 115                 dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
 116                 dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_82810:
 119         case PCI_DEVICE_ID_INTEL_82810DC:
 120         case PCI_DEVICE_ID_INTEL_82810E_MC:
 121         case PCI_DEVICE_ID_INTEL_82865:
 122                 printf("This northbridge does not have DMIBAR.\n");
 123                 return 1;
 124         case PCI_DEVICE_ID_INTEL_X58:
 125                 dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
 126                 break;
 127         default:
 128                 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
 129                 return 1;
 130         }
 131
 132         dmibar = map_physical(dmibar_phys, size);
 133
 134         if (dmibar == NULL) {
 135                 perror("Error mapping DMIBAR");
 136                 exit(1);
 137         }
 138
 139         printf("DMIBAR = 0x%08" PRIx64 " (MEM)\n\n", dmibar_phys);
 140         for (i = 0; i < size; i += 4) {
 141                 if (*(uint32_t *)(dmibar + i))
 142                         printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
 143         }
 144
 145         unmap_physical((void *)dmibar, size);
 146         return 0;
 147 }
 148
 149 /*
 150  * PCIe MMIO configuration space
 151  */
 152 int print_pciexbar(struct pci_dev *nb)
 153 {
 154         uint64_t pciexbar_reg;
 155         uint64_t pciexbar_phys;
 156         volatile uint8_t *pciexbar;
 157         int max_busses, devbase, i;
 158         int bus, dev, fn;
 159
 160         printf("========= PCIEXBAR ========\n\n");
 161
 162         switch (nb->device_id) {
 163         case PCI_DEVICE_ID_INTEL_82915:
 164         case PCI_DEVICE_ID_INTEL_82945GM:
 165         case PCI_DEVICE_ID_INTEL_82945GSE:
 166         case PCI_DEVICE_ID_INTEL_82945P:
 167         case PCI_DEVICE_ID_INTEL_82975X:
 168                 pciexbar_reg = pci_read_long(nb, 0x48);
 169                 break;
 170         case PCI_DEVICE_ID_INTEL_PM965:
 171         case PCI_DEVICE_ID_INTEL_Q965:
 172         case PCI_DEVICE_ID_INTEL_82Q35:
 173         case PCI_DEVICE_ID_INTEL_82G33:
 174         case PCI_DEVICE_ID_INTEL_82Q33:
 175         case PCI_DEVICE_ID_INTEL_X44:
 176         case PCI_DEVICE_ID_INTEL_32X0:
 177         case PCI_DEVICE_ID_INTEL_GS45:
 178         case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
 179         case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
 180                 pciexbar_reg = pci_read_long(nb, 0x60);
 181                 pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
 182                 break;
 183         case PCI_DEVICE_ID_INTEL_82810:
 184         case PCI_DEVICE_ID_INTEL_82810DC:
 185         case PCI_DEVICE_ID_INTEL_82810E_MC:
 186         case PCI_DEVICE_ID_INTEL_82865:
 187                 printf("Error: This northbridge does not have PCIEXBAR.\n");
 188                 return 1;
 189         default:
 190                 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
 191                 return 1;
 192         }
 193
 194         if (!(pciexbar_reg & (1 << 0))) {
 195                 printf("PCIEXBAR register is disabled.\n");
 196                 return 0;
 197         }
 198
 199         switch ((pciexbar_reg >> 1) & 3) {
 200         case 0: // 256MB
 201                 pciexbar_phys = pciexbar_reg & (0xff << 28);
 202                 max_busses = 256;
 203                 break;
 204         case 1: // 128M
 205                 pciexbar_phys = pciexbar_reg & (0x1ff << 27);
 206                 max_busses = 128;
 207                 break;
 208         case 2: // 64M
 209                 pciexbar_phys = pciexbar_reg & (0x3ff << 26);
 210                 max_busses = 64;
 211                 break;
 212         default: // RSVD
 213                 printf("Undefined address base. Bailing out.\n");
 214                 return 1;
 215         }
 216
 217         printf("PCIEXBAR: 0x%08" PRIx64 "\n", pciexbar_phys);
 218
 219         pciexbar = map_physical(pciexbar_phys, (max_busses * 1024 * 1024));
 220
 221         if (pciexbar == NULL) {
 222                 perror("Error mapping PCIEXBAR");
 223                 exit(1);
 224         }
 225
 226         for (bus = 0; bus < max_busses; bus++) {
 227                 for (dev = 0; dev < 32; dev++) {
 228                         for (fn = 0; fn < 8; fn++) {
 229                                 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
 230
 231                                 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
 232                                         continue;
 233
 234                                 /* This is a heuristics. Anyone got a better check? */
 235                                 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
 236                                         (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
 237 #if DEBUG
 238                                         printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
 239 #endif
 240                                         continue;
 241                                 }
 242
 243                                 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
 244                                 for (i = 0; i < 4096; i++) {
 245                                         if((i % 0x10) == 0)
 246                                                 printf("\n%04x:", i);
 247                                         printf(" %02x", *(pciexbar+devbase+i));
 248                                 }
 249                                 printf("\n");
 250                         }
 251                 }
 252         }
 253
 254         unmap_physical((void *)pciexbar, (max_busses * 1024 * 1024));
 255
 256         return 0;
 257 }