src/soc/intel/broadwell/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <console/console.h>
   5 #include <console/post_codes.h>
   6 #include <reg_script.h>
   7 #include <spi-generic.h>
   8 #include <soc/pci_devs.h>
   9 #include <soc/lpc.h>
  10 #include <soc/me.h>
  11 #include <soc/rcba.h>
  12 #include <soc/spi.h>
  13 #include <soc/systemagent.h>
  14 #include <southbridge/intel/common/spi.h>
  15
  16 const struct reg_script system_agent_finalize_script[] = {
  17         REG_PCI_OR16(0x50, 1 << 0),                             /* GGC */
  18         REG_PCI_OR32(0x5c, 1 << 0),                             /* DPR */
  19         REG_PCI_OR32(0x78, 1 << 10),                            /* ME */
  20         REG_PCI_OR32(0x90, 1 << 0),                             /* REMAPBASE */
  21         REG_PCI_OR32(0x98, 1 << 0),                             /* REMAPLIMIT */
  22         REG_PCI_OR32(0xa0, 1 << 0),                             /* TOM */
  23         REG_PCI_OR32(0xa8, 1 << 0),                             /* TOUUD */
  24         REG_PCI_OR32(0xb0, 1 << 0),                             /* BDSM */
  25         REG_PCI_OR32(0xb4, 1 << 0),                             /* BGSM */
  26         REG_PCI_OR32(0xb8, 1 << 0),                             /* TSEGMB */
  27         REG_PCI_OR32(0xbc, 1 << 0),                             /* TOLUD */
  28         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0),       /* PAVP */
  29         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31),      /* SA PM */
  30         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0),       /* UMA GFX */
  31         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0),       /* VTDTRK */
  32         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
  33         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
  34         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
  35         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
  36         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
  37         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
  38         REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f),       /* MC */
  39
  40         REG_SCRIPT_END
  41 };
  42
  43 const struct reg_script pch_finalize_script[] = {
  44 #if !CONFIG(SPI_CONSOLE)
  45         /* Lock SPIBAR */
  46         REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
  47                       SPIBAR_HSFS_FLOCKDN),
  48 #endif
  49
  50         /* TC Lockdown */
  51         REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
  52
  53         /* BIOS Interface Lockdown */
  54         REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
  55
  56         /* Function Disable SUS Well Lockdown */
  57         REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
  58
  59         /* Global SMI Lock */
  60         REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
  61
  62         /* GEN_PMCON Lock */
  63         REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
  64
  65         /* PMSYNC */
  66         REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
  67
  68         REG_SCRIPT_END
  69 };
  70
  71 static void broadwell_finalize(void *unused)
  72 {
  73         struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  74
  75         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  76
  77         reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
  78
  79         spi_finalize_ops();
  80         reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
  81
  82         /* Lock */
  83         RCBA32_OR(0x3a6c, 0x00000001);
  84
  85         /* Read+Write the following registers */
  86         MCHBAR32(0x6030) = MCHBAR32(0x6030);
  87         MCHBAR32(0x6034) = MCHBAR32(0x6034);
  88         MCHBAR32(0x6008) = MCHBAR32(0x6008);
  89         RCBA32(0x21a4) = RCBA32(0x21a4);
  90
  91         /* Indicate finalize step with post code */
  92         post_code(POST_OS_BOOT);
  93 }
  94
  95 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
  96 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);