src/soc/intel/broadwell/finalize.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootstate.h>
   4 #include <commonlib/console/post_codes.h>
   5 #include <console/console.h>
   6 #include <device/pci_ops.h>
   7 #include <soc/pch.h>
   8 #include <soc/pci_devs.h>
   9 #include <soc/systemagent.h>
  10
  11 /*
  12  * 16.6 System Agent Configuration Locking
  13  * "5th Generation Intel Core Processor Family BIOS Specification"
  14  * Document Number 535094
  15  * Revision 2.2.0, August 2014
  16  *
  17  * To ease reading, first lock PCI registers, then MCHBAR registers.
  18  * Write the MC Lock register first, since more than one bit gets set.
  19  */
  20 static void broadwell_systemagent_finalize(void)
  21 {
  22         struct device *const host_bridge = pcidev_path_on_root(SA_DEVFN_ROOT);
  23
  24         pci_or_config16(host_bridge, GGC,         1 << 0);
  25         pci_or_config32(host_bridge, DPR,         1 << 0);
  26         pci_or_config32(host_bridge, MESEG_LIMIT, 1 << 10);
  27         pci_or_config32(host_bridge, REMAPBASE,   1 << 0);
  28         pci_or_config32(host_bridge, REMAPLIMIT,  1 << 0);
  29         pci_or_config32(host_bridge, TOM,         1 << 0);
  30         pci_or_config32(host_bridge, TOUUD,       1 << 0);
  31         pci_or_config32(host_bridge, BDSM,        1 << 0);
  32         pci_or_config32(host_bridge, BGSM,        1 << 0);
  33         pci_or_config32(host_bridge, TSEG,        1 << 0);
  34         pci_or_config32(host_bridge, TOLUD,       1 << 0);
  35
  36         mchbar_setbits32(0x50fc, 0x8f);         /* MC */
  37         mchbar_setbits32(0x5500, 1 << 0);       /* PAVP */
  38         mchbar_setbits32(0x5880, 1 << 5);       /* DDR PTM */
  39         mchbar_setbits32(0x7000, 1 << 31);
  40         mchbar_setbits32(0x77fc, 1 << 0);
  41         mchbar_setbits32(0x7ffc, 1 << 0);
  42         mchbar_setbits32(0x6800, 1 << 31);
  43         mchbar_setbits32(0x6020, 1 << 0);               /* UMA GFX */
  44         mchbar_setbits32(0x63fc, 1 << 0);               /* VTDTRK */
  45
  46         /* Read+write the following */
  47         mchbar_setbits32(0x6030, 0);
  48         mchbar_setbits32(0x6034, 0);
  49         mchbar_setbits32(0x6008, 0);
  50 }
  51
  52 static void broadwell_finalize(void *unused)
  53 {
  54         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  55
  56         broadwell_systemagent_finalize();
  57
  58         broadwell_pch_finalize();
  59
  60         /* Indicate finalize step with post code */
  61         post_code(POSTCODE_OS_BOOT);
  62 }
  63
  64 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
  65 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);