src/soc/intel/broadwell/finalize.c

   1 /*
   2  * This file is part of the coreboot project.
   3  *
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; version 2 of the License.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <bootstate.h>
  16 #include <console/console.h>
  17 #include <console/post_codes.h>
  18 #include <cpu/x86/smm.h>
  19 #include <reg_script.h>
  20 #include <spi-generic.h>
  21 #include <soc/pci_devs.h>
  22 #include <soc/lpc.h>
  23 #include <soc/me.h>
  24 #include <soc/rcba.h>
  25 #include <soc/spi.h>
  26 #include <soc/systemagent.h>
  27 #include <southbridge/intel/common/spi.h>
  28
  29 const struct reg_script system_agent_finalize_script[] = {
  30         REG_PCI_OR16(0x50, 1 << 0),                             /* GGC */
  31         REG_PCI_OR32(0x5c, 1 << 0),                             /* DPR */
  32         REG_PCI_OR32(0x78, 1 << 10),                            /* ME */
  33         REG_PCI_OR32(0x90, 1 << 0),                             /* REMAPBASE */
  34         REG_PCI_OR32(0x98, 1 << 0),                             /* REMAPLIMIT */
  35         REG_PCI_OR32(0xa0, 1 << 0),                             /* TOM */
  36         REG_PCI_OR32(0xa8, 1 << 0),                             /* TOUUD */
  37         REG_PCI_OR32(0xb0, 1 << 0),                             /* BDSM */
  38         REG_PCI_OR32(0xb4, 1 << 0),                             /* BGSM */
  39         REG_PCI_OR32(0xb8, 1 << 0),                             /* TSEGMB */
  40         REG_PCI_OR32(0xbc, 1 << 0),                             /* TOLUD */
  41         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5500, 1 << 0),       /* PAVP */
  42         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5f00, 1 << 31),      /* SA PM */
  43         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6020, 1 << 0),       /* UMA GFX */
  44         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x63fc, 1 << 0),       /* VTDTRK */
  45         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x6800, 1 << 31),
  46         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7000, 1 << 31),
  47         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x77fc, 1 << 0),
  48         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x50fc, 0x8f),
  49         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x7ffc, 1 << 0),
  50         REG_MMIO_OR32(MCH_BASE_ADDRESS + 0x5880, 1 << 5),
  51         REG_MMIO_WRITE8(MCH_BASE_ADDRESS + 0x50fc, 0x8f),       /* MC */
  52
  53         REG_SCRIPT_END
  54 };
  55
  56 const struct reg_script pch_finalize_script[] = {
  57 #if !CONFIG(SPI_CONSOLE)
  58         /* Lock SPIBAR */
  59         REG_MMIO_OR32(RCBA_BASE_ADDRESS + SPIBAR_OFFSET + SPIBAR_HSFS,
  60                       SPIBAR_HSFS_FLOCKDN),
  61 #endif
  62
  63         /* TC Lockdown */
  64         REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x0050, (1 << 31)),
  65
  66         /* BIOS Interface Lockdown */
  67         REG_MMIO_OR32(RCBA_BASE_ADDRESS + GCS, (1 << 0)),
  68
  69         /* Function Disable SUS Well Lockdown */
  70         REG_MMIO_OR8(RCBA_BASE_ADDRESS + FDSW, (1 << 7)),
  71
  72         /* Global SMI Lock */
  73         REG_PCI_OR16(GEN_PMCON_1, SMI_LOCK),
  74
  75         /* GEN_PMCON Lock */
  76         REG_PCI_OR8(GEN_PMCON_LOCK, SLP_STR_POL_LOCK | ACPI_BASE_LOCK),
  77
  78         /* PMSYNC */
  79         REG_MMIO_OR32(RCBA_BASE_ADDRESS + PMSYNC_CONFIG, (1 << 31)),
  80
  81
  82         REG_SCRIPT_END
  83 };
  84
  85 static void broadwell_finalize(void *unused)
  86 {
  87         struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
  88
  89         printk(BIOS_DEBUG, "Finalizing chipset.\n");
  90
  91         reg_script_run_on_dev(sa_dev, system_agent_finalize_script);
  92
  93         spi_finalize_ops();
  94         reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
  95
  96         /* Lock */
  97         RCBA32_OR(0x3a6c, 0x00000001);
  98
  99         /* Read+Write the following registers */
 100         MCHBAR32(0x6030) = MCHBAR32(0x6030);
 101         MCHBAR32(0x6034) = MCHBAR32(0x6034);
 102         MCHBAR32(0x6008) = MCHBAR32(0x6008);
 103         RCBA32(0x21a4) = RCBA32(0x21a4);
 104
 105         /* Indicate finalize step with post code */
 106         post_code(POST_OS_BOOT);
 107 }
 108
 109 BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, broadwell_finalize, NULL);
 110 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL);