| blob | 76c01276b4f9fc419c7dcd34475d3b60c3fa8ec7 |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto 0
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
69 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
70 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
71 in that slot. */
74 {
75 /* No relocation. */
104 /* 32 bit absolute */
119 /* standard 32bit pc-relative reloc */
134 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
149 /* 16 bit absolute */
164 /* 12 bit absolute */
193 /* 8 bit absolute */
292 /* BLX instruction for the ARM. */
307 /* BLX instruction for the Thumb. */
322 /* Dynamic TLS relocations. */
366 /* Relocs used in ARM Linux */
830 /* These are declared as 13-bit signed relocations because we can
831 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
832 versa. */
889 /* Group relocations. */
1269 /* End of group relocations. */
1483 /* GNU extension to record C++ vtable member usage */
1498 /* GNU extension to record C++ vtable hierarchy */
1541 /* TLS relocations */
1685 };
1687 /* 112-127 private relocations
1688 128 R_ARM_ME_TOO, obsolete
1689 129-255 unallocated in AAELF.
1691 249-255 extended, currently unused, relocations: */
1694 {
1750 };
1754 {
1763 }
1765 static void
1768 {
1773 }
1775 struct elf32_arm_reloc_map
1776 {
1777 bfd_reloc_code_real_type bfd_reloc_val;
1779 };
1781 /* All entries in this list must also be present in elf32_arm_howto_table. */
1783 {
1869 };
1873 bfd_reloc_code_real_type code)
1874 {
1882 }
1887 {
1901 }
1903 /* Support for core dump NOTE sections. */
1905 static bfd_boolean
1907 {
1912 {
1917 /* pr_cursig */
1920 /* pr_pid */
1923 /* pr_reg */
1928 }
1930 /* Make a ".reg/999" section. */
1933 }
1935 static bfd_boolean
1937 {
1939 {
1948 }
1950 /* Note that for some reason, a spurious space is tacked
1951 onto the end of the args in some (at least one anyway)
1952 implementations, so strip it off if it exists. */
1953 {
1959 }
1962 }
1964 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
1966 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
1969 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
1970 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
1975 /* In lieu of proper flags, assume all EABIv4 or later objects are
1976 interworkable. */
1977 #define INTERWORK_FLAG(abfd) \
1978 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
1979 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
1980 || ((abfd)->flags & BFD_LINKER_CREATED))
1982 /* The linker script knows the section names for placement.
1983 The entry_names are used to do simple name mangling on the stubs.
1984 Given a function name, and its type, the stub can be found. The
1985 name can be changed. The only requirement is the %s be present. */
2000 /* The name of the dynamic interpreter. This is put in the .interp
2001 section. */
2005 {
2009 };
2012 {
2020 + dl_tlsdesc_lazy_resolver(GOT) */
2022 };
2024 #ifdef FOUR_WORD_PLT
2026 /* The first entry in a procedure linkage table looks like
2027 this. It is set up so that any shared library function that is
2028 called before the relocation has been set up calls the dynamic
2029 linker first. */
2031 {
2036 };
2038 /* Subsequent entries in a procedure linkage table look like
2039 this. */
2041 {
2046 };
2048 #else
2050 /* The first entry in a procedure linkage table looks like
2051 this. It is set up so that any shared library function that is
2052 called before the relocation has been set up calls the dynamic
2053 linker first. */
2055 {
2061 };
2063 /* Subsequent entries in a procedure linkage table look like
2064 this. */
2066 {
2070 };
2072 #endif
2074 /* The format of the first entry in the procedure linkage table
2075 for a VxWorks executable. */
2077 {
2082 };
2084 /* The format of subsequent entries in a VxWorks executable. */
2086 {
2093 };
2095 /* The format of entries in a VxWorks shared library. */
2097 {
2104 };
2106 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2107 #define PLT_THUMB_STUB_SIZE 4
2109 {
2112 };
2114 /* The entries in a PLT when using a DLL-based target with multiple
2115 address spaces. */
2117 {
2120 };
2122 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2123 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2124 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2125 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2126 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2127 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2129 enum stub_insn_type
2130 {
2132 THUMB32_TYPE,
2133 ARM_TYPE,
2134 DATA_TYPE
2135 };
2137 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2138 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2139 is inserted in arm_build_one_stub(). */
2140 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2141 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2142 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2143 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2144 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2145 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2148 {
2149 bfd_vma data;
2155 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2156 to reach the stub if necessary. */
2158 {
2161 };
2163 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2164 available. */
2166 {
2170 };
2172 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2174 {
2182 };
2184 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2185 allowed. */
2187 {
2193 };
2195 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2196 available. */
2198 {
2203 };
2205 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2206 one, when the destination is close enough. */
2208 {
2212 };
2214 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2215 blx to reach the stub if necessary. */
2217 {
2221 };
2223 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2224 blx to reach the stub if necessary. We can not add into pc;
2225 it is not guaranteed to mode switch (different in ARMv6 and
2226 ARMv7). */
2228 {
2233 };
2235 /* V4T ARM -> ARM long branch stub, PIC. */
2237 {
2242 };
2244 /* V4T Thumb -> ARM long branch stub, PIC. */
2246 {
2252 };
2254 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2255 architectures. */
2257 {
2265 };
2267 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2268 allowed. */
2270 {
2277 };
2279 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2280 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2282 {
2286 };
2288 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2289 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2291 {
2297 };
2299 /* Cortex-A8 erratum-workaround stubs. */
2301 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2302 can't use a conditional branch to reach this stub). */
2305 {
2309 };
2311 /* Stub used for b.w and bl.w instructions. */
2314 {
2316 };
2319 {
2321 };
2323 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2324 instruction (which switches to ARM mode) to point to this stub. Jump to the
2325 real destination using an ARM-mode branch. */
2328 {
2330 };
2332 /* Section name for stubs is the associated section name plus this
2333 string. */
2336 /* One entry per long/short branch stub defined above. */
2337 #define DEF_STUBS \
2338 DEF_STUB(long_branch_any_any) \
2339 DEF_STUB(long_branch_v4t_arm_thumb) \
2340 DEF_STUB(long_branch_thumb_only) \
2341 DEF_STUB(long_branch_v4t_thumb_thumb) \
2342 DEF_STUB(long_branch_v4t_thumb_arm) \
2343 DEF_STUB(short_branch_v4t_thumb_arm) \
2344 DEF_STUB(long_branch_any_arm_pic) \
2345 DEF_STUB(long_branch_any_thumb_pic) \
2346 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2347 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2348 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2349 DEF_STUB(long_branch_thumb_only_pic) \
2350 DEF_STUB(long_branch_any_tls_pic) \
2351 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2352 DEF_STUB(a8_veneer_b_cond) \
2353 DEF_STUB(a8_veneer_b) \
2354 DEF_STUB(a8_veneer_bl) \
2355 DEF_STUB(a8_veneer_blx)
2357 #define DEF_STUB(x) arm_stub_##x,
2359 arm_stub_none,
2360 DEF_STUBS
2361 /* Note the first a8_veneer type */
2362 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2363 };
2364 #undef DEF_STUB
2367 {
2372 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2375 DEF_STUBS
2376 };
2378 struct elf32_arm_stub_hash_entry
2379 {
2380 /* Base hash table entry structure. */
2383 /* The stub section. */
2386 /* Offset within stub_sec of the beginning of this stub. */
2387 bfd_vma stub_offset;
2389 /* Given the symbol's value and its section we can determine its final
2390 value when building the stubs (so the stub knows where to jump). */
2391 bfd_vma target_value;
2394 /* Offset to apply to relocation referencing target_value. */
2395 bfd_vma target_addend;
2397 /* The instruction which caused this stub to be generated (only valid for
2398 Cortex-A8 erratum workaround stubs at present). */
2401 /* The stub type. */
2403 /* Its encoding size in bytes. */
2405 /* Its template. */
2407 /* The size of the template (number of entries). */
2410 /* The symbol table entry, if any, that this was derived from. */
2413 /* Destination symbol type (STT_ARM_TFUNC, ...) */
2416 /* Where this stub is being called from, or, in the case of combined
2417 stub sections, the first input section in the group. */
2420 /* The name for the local symbol at the start of this stub. The
2421 stub name in the hash table has to be unique; this does not, so
2422 it can be friendlier. */
2424 };
2426 /* Used to build a map of a section. This is required for mixed-endian
2427 code/data. */
2430 {
2431 bfd_vma vma;
2433 }
2434 elf32_arm_section_map;
2436 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2439 {
2440 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2441 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2442 VFP11_ERRATUM_ARM_VENEER,
2443 VFP11_ERRATUM_THUMB_VENEER
2444 }
2445 elf32_vfp11_erratum_type;
2448 {
2450 bfd_vma vma;
2451 union
2452 {
2453 struct
2454 {
2458 struct
2459 {
2464 elf32_vfp11_erratum_type type;
2465 }
2466 elf32_vfp11_erratum_list;
2469 {
2470 DELETE_EXIDX_ENTRY,
2471 INSERT_EXIDX_CANTUNWIND_AT_END
2472 }
2473 arm_unwind_edit_type;
2475 /* A (sorted) list of edits to apply to an unwind table. */
2477 {
2478 arm_unwind_edit_type type;
2479 /* Note: we sometimes want to insert an unwind entry corresponding to a
2480 section different from the one we're currently writing out, so record the
2481 (text) section this edit relates to here. */
2485 }
2486 arm_unwind_table_edit;
2489 {
2490 /* Information about mapping symbols. */
2495 /* Information about CPU errata. */
2498 /* Information about unwind tables. */
2499 union
2500 {
2501 /* Unwind info attached to a text section. */
2502 struct
2503 {
2507 /* Unwind info attached to an .ARM.exidx section. */
2508 struct
2509 {
2514 }
2515 _arm_elf_section_data;
2517 #define elf32_arm_section_data(sec) \
2518 ((_arm_elf_section_data *) elf_section_data (sec))
2520 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2521 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2522 so may be created multiple times: we use an array of these entries whilst
2523 relaxing which we can refresh easily, then create stubs for each potentially
2524 erratum-triggering instruction once we've settled on a solution. */
2529 bfd_vma offset;
2530 bfd_vma addend;
2535 };
2537 /* A table of relocs applied to branches which might trigger Cortex-A8
2538 erratum. */
2541 bfd_vma from;
2542 bfd_vma destination;
2547 bfd_boolean non_a8_stub;
2548 };
2550 /* The size of the thread control block. */
2551 #define TCB_SIZE 8
2553 struct elf_arm_obj_tdata
2554 {
2557 /* tls_type for each local got entry. */
2560 /* GOTPLT entries for TLS descriptors. */
2563 /* Zero to warn when linking objects with incompatible enum sizes. */
2566 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2568 };
2570 #define elf_arm_tdata(bfd) \
2571 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2573 #define elf32_arm_local_got_tls_type(bfd) \
2574 (elf_arm_tdata (bfd)->local_got_tls_type)
2576 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2577 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2579 #define is_arm_elf(bfd) \
2580 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2581 && elf_tdata (bfd) != NULL \
2582 && elf_object_id (bfd) == ARM_ELF_DATA)
2584 static bfd_boolean
2586 {
2588 ARM_ELF_DATA);
2589 }
2591 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2593 /* Arm ELF linker hash entry. */
2594 struct elf32_arm_link_hash_entry
2595 {
2598 /* Track dynamic relocs copied for this symbol. */
2601 /* We reference count Thumb references to a PLT entry separately,
2602 so that we can emit the Thumb trampoline only if needed. */
2603 bfd_signed_vma plt_thumb_refcount;
2605 /* Some references from Thumb code may be eliminated by BL->BLX
2606 conversion, so record them separately. */
2607 bfd_signed_vma plt_maybe_thumb_refcount;
2609 /* Since PLT entries have variable size if the Thumb prologue is
2610 used, we need to record the index into .got.plt instead of
2611 recomputing it from the PLT offset. */
2612 bfd_signed_vma plt_got_offset;
2614 #define GOT_UNKNOWN 0
2615 #define GOT_NORMAL 1
2616 #define GOT_TLS_GD 2
2617 #define GOT_TLS_IE 4
2618 #define GOT_TLS_GDESC 8
2619 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2622 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2623 starting at the end of the jump table. */
2624 bfd_vma tlsdesc_got;
2626 /* The symbol marking the real symbol location for exported thumb
2627 symbols with Arm stubs. */
2630 /* A pointer to the most recently used stub hash entry against this
2631 symbol. */
2633 };
2635 /* Traverse an arm ELF linker hash table. */
2636 #define elf32_arm_link_hash_traverse(table, func, info) \
2637 (elf_link_hash_traverse \
2638 (&(table)->root, \
2639 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2640 (info)))
2642 /* Get the ARM elf linker hash table from a link_info structure. */
2643 #define elf32_arm_hash_table(info) \
2644 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2645 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2647 #define arm_stub_hash_lookup(table, string, create, copy) \
2648 ((struct elf32_arm_stub_hash_entry *) \
2649 bfd_hash_lookup ((table), (string), (create), (copy)))
2651 /* Array to keep track of which stub sections have been created, and
2652 information on stub grouping. */
2653 struct map_stub
2654 {
2655 /* This is the section to which stubs in the group will be
2656 attached. */
2658 /* The stub section. */
2660 };
2662 #define elf32_arm_compute_jump_table_size(htab) \
2663 ((htab)->next_tls_desc_index * 4)
2665 /* ARM ELF linker hash table. */
2666 struct elf32_arm_link_hash_table
2667 {
2668 /* The main hash table. */
2671 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2672 bfd_size_type thumb_glue_size;
2674 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2675 bfd_size_type arm_glue_size;
2677 /* The size in bytes of section containing the ARMv4 BX veneers. */
2678 bfd_size_type bx_glue_size;
2680 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2681 veneer has been populated. */
2684 /* The size in bytes of the section containing glue for VFP11 erratum
2685 veneers. */
2686 bfd_size_type vfp11_erratum_glue_size;
2688 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2689 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2690 elf32_arm_write_section(). */
2694 /* An arbitrary input BFD chosen to hold the glue sections. */
2697 /* Nonzero to output a BE8 image. */
2700 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2701 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2704 /* The relocation to use for R_ARM_TARGET2 relocations. */
2707 /* 0 = Ignore R_ARM_V4BX.
2708 1 = Convert BX to MOV PC.
2709 2 = Generate v4 interworing stubs. */
2712 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2715 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2718 /* What sort of code sequences we should look for which may trigger the
2719 VFP11 denorm erratum. */
2720 bfd_arm_vfp11_fix vfp11_fix;
2722 /* Global counter for the number of fixes we have emitted. */
2725 /* Nonzero to force PIC branch veneers. */
2728 /* The number of bytes in the initial entry in the PLT. */
2729 bfd_size_type plt_header_size;
2731 /* The number of bytes in the subsequent PLT etries. */
2732 bfd_size_type plt_entry_size;
2734 /* True if the target system is VxWorks. */
2737 /* True if the target system is Symbian OS. */
2740 /* True if the target uses REL relocations. */
2743 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2744 bfd_vma next_tls_desc_index;
2746 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2747 bfd_vma num_tls_desc;
2749 /* Short-cuts to get to dynamic linker sections. */
2753 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2756 /* The offset into splt of the PLT entry for the TLS descriptor
2757 resolver. Special values are 0, if not necessary (or not found
2758 to be necessary yet), and -1 if needed but not determined
2759 yet. */
2760 bfd_vma dt_tlsdesc_plt;
2762 /* The offset into sgot of the GOT entry used by the PLT entry
2763 above. */
2764 bfd_vma dt_tlsdesc_got;
2766 /* Offset in .plt section of tls_arm_trampoline. */
2767 bfd_vma tls_trampoline;
2769 /* Data for R_ARM_TLS_LDM32 relocations. */
2770 union
2771 {
2772 bfd_signed_vma refcount;
2773 bfd_vma offset;
2776 /* Small local sym cache. */
2779 /* For convenience in allocate_dynrelocs. */
2782 /* The amount of space used by the reserved portion of the sgotplt
2783 section, plus whatever space is used by the jump slots. */
2784 bfd_vma sgotplt_jump_table_size;
2786 /* The stub hash table. */
2789 /* Linker stub bfd. */
2792 /* Linker call-backs. */
2796 /* Array to keep track of which stub sections have been created, and
2797 information on stub grouping. */
2800 /* Number of elements in stub_group. */
2803 /* Assorted information used by elf32_arm_size_stubs. */
2807 };
2809 /* Create an entry in an ARM ELF linker hash table. */
2815 {
2819 /* Allocate the structure if it has not already been allocated by a
2820 subclass. */
2827 /* Call the allocation method of the superclass. */
2832 {
2842 }
2845 }
2847 /* Initialize an entry in the stub hash table. */
2853 {
2854 /* Allocate the structure if it has not already been allocated by a
2855 subclass. */
2857 {
2862 }
2864 /* Call the allocation method of the superclass. */
2867 {
2870 /* Initialize the local fields. */
2885 }
2888 }
2890 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
2891 shortcuts to them in our hash table. */
2893 static bfd_boolean
2895 {
2902 /* BPABI objects never have a GOT, or associated sections. */
2910 }
2912 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
2913 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
2914 hash table. */
2916 static bfd_boolean
2918 {
2937 {
2942 {
2944 htab->plt_entry_size
2946 }
2947 else
2948 {
2949 htab->plt_header_size
2951 htab->plt_entry_size
2953 }
2954 }
2963 }
2965 /* Copy the extra info we tack onto an elf_link_hash_entry. */
2967 static void
2971 {
2978 {
2980 {
2984 /* Add reloc counts against the indirect sym to the direct sym
2985 list. Merge any entries against the same section. */
2987 {
2992 {
2997 }
3000 }
3002 }
3006 }
3009 {
3010 /* Copy over PLT info. */
3017 {
3020 }
3021 }
3024 }
3026 /* Create an ARM elf linker hash table. */
3030 {
3039 elf32_arm_link_hash_newfunc,
3041 ARM_ELF_DATA))
3042 {
3045 }
3067 #ifdef FOUR_WORD_PLT
3070 #else
3073 #endif
3093 {
3096 }
3099 }
3101 /* Free the derived linker hash table. */
3103 static void
3105 {
3111 }
3113 /* Determine if we're dealing with a Thumb only architecture. */
3115 static bfd_boolean
3117 {
3119 Tag_CPU_arch);
3129 Tag_CPU_arch_profile);
3132 }
3134 /* Determine if we're dealing with a Thumb-2 object. */
3136 static bfd_boolean
3138 {
3140 Tag_CPU_arch);
3142 }
3144 /* Determine what kind of NOPs are available. */
3146 static bfd_boolean
3148 {
3150 Tag_CPU_arch);
3155 }
3157 static bfd_boolean
3159 {
3161 Tag_CPU_arch);
3164 }
3166 static bfd_boolean
3168 {
3170 {
3183 }
3184 }
3186 /* Determine the type of stub needed, if any, for a call. */
3188 static enum elf32_arm_stub_type
3194 bfd_vma destination,
3198 {
3199 bfd_vma location;
3200 bfd_signed_vma branch_offset;
3209 /* We don't know the actual type of destination in case it is of
3210 type STT_SECTION: give up. */
3222 /* Determine where the call point is. */
3229 /* Keep a simpler condition, for the sake of clarity. */
3233 {
3236 /* Note when dealing with PLT entries: the main PLT stub is in
3237 ARM mode, so if the branch is in Thumb mode, another
3238 Thumb->ARM stub will be inserted later just before the ARM
3239 PLT stub. We don't take this extra distance into account
3240 here, because if a long branch stub is needed, we'll add a
3241 Thumb->Arm one and branch directly to the ARM PLT entry
3242 because it avoids spreading offset corrections in several
3243 places. */
3249 }
3255 {
3256 /* Handle cases where:
3257 - this call goes too far (different Thumb/Thumb2 max
3258 distance)
3259 - it's a Thumb->Arm call and blx is not available, or it's a
3260 Thumb->Arm branch (not bl). A stub is needed in this case,
3261 but only if this call is not through a PLT entry. Indeed,
3262 PLT stubs handle mode switching already.
3263 */
3267 || (thumb2
3275 {
3277 {
3278 /* Thumb to thumb. */
3280 {
3282 /* PIC stubs. */
3285 /* V5T and above. Stub starts with ARM code, so
3286 we must be able to switch mode before
3287 reaching it, which is only possible for 'bl'
3288 (ie R_ARM_THM_CALL relocation). */
3289 ? arm_stub_long_branch_any_thumb_pic
3290 /* On V4T, use Thumb code only. */
3293 /* non-PIC stubs. */
3296 /* V5T and above. */
3297 ? arm_stub_long_branch_any_any
3298 /* V4T. */
3300 }
3301 else
3302 {
3304 /* PIC stub. */
3305 ? arm_stub_long_branch_thumb_only_pic
3306 /* non-PIC stub. */
3308 }
3309 }
3310 else
3311 {
3312 /* Thumb to arm. */
3316 {
3321 }
3323 stub_type =
3325 /* PIC stubs. */
3327 /* TLS PIC stubs */
3331 /* V5T PIC and above. */
3332 ? arm_stub_long_branch_any_arm_pic
3333 /* V4T PIC stub. */
3336 /* non-PIC stubs. */
3338 /* V5T and above. */
3339 ? arm_stub_long_branch_any_any
3340 /* V4T. */
3343 /* Handle v4t short branches. */
3348 }
3349 }
3350 }
3355 {
3357 {
3358 /* Arm to thumb. */
3363 {
3368 }
3370 /* We have an extra 2-bytes reach because of
3371 the mode change (bit 24 (H) of BLX encoding). */
3377 {
3379 /* PIC stubs. */
3381 /* V5T and above. */
3382 ? arm_stub_long_branch_any_thumb_pic
3383 /* V4T stub. */
3386 /* non-PIC stubs. */
3388 /* V5T and above. */
3389 ? arm_stub_long_branch_any_any
3390 /* V4T. */
3392 }
3393 }
3394 else
3395 {
3396 /* Arm to arm. */
3399 {
3400 stub_type =
3402 /* PIC stubs. */
3404 /* TLS PIC Stub */
3405 ? arm_stub_long_branch_any_tls_pic
3407 /* non-PIC stubs. */
3409 }
3410 }
3411 }
3413 /* If a stub is needed, record the actual destination type. */
3418 }
3420 /* Build a name for an entry in the stub hash table. */
3428 {
3430 bfd_size_type len;
3433 {
3442 }
3443 else
3444 {
3456 }
3459 }
3461 /* Look up an entry in the stub hash. Stub entries are cached because
3462 creating the stub name takes a bit of time. */
3471 {
3479 /* If this input section is part of a group of sections sharing one
3480 stub section, then use the id of the first section in the group.
3481 Stub names need to include a section id, as there may well be
3482 more than one stub used to reach say, printf, and we need to
3483 distinguish between them. */
3490 {
3492 }
3493 else
3494 {
3507 }
3510 }
3512 /* Find or create a stub section. Returns a pointer to the stub section, and
3513 the section to which the stub section will be attached (in *LINK_SEC_P).
3514 LINK_SEC_P may be NULL. */
3519 {
3526 {
3529 {
3531 bfd_size_type len;
3546 }
3548 }
3554 }
3556 /* Add a new stub entry to the stub hash. Not all fields of the new
3557 stub entry are initialised. */
3563 {
3572 /* Enter this entry into the linker stub hash table. */
3576 {
3579 stub_name);
3581 }
3588 }
3590 /* Store an Arm insn into an output section not processed by
3591 elf32_arm_write_section. */
3593 static void
3596 {
3599 else
3601 }
3603 /* Store a 16-bit Thumb insn into an output section not processed by
3604 elf32_arm_write_section. */
3606 static void
3609 {
3612 else
3614 }
3616 /* If it's possible to change R_TYPE to a more efficient access
3617 model, return the new reloc type. */
3619 static unsigned
3622 {
3628 /* We do not support relaxations for Old TLS models. */
3630 {
3637 }
3640 }
3642 static bfd_reloc_status_type elf32_arm_final_link_relocate
3647 static unsigned int
3649 {
3651 {
3676 }
3677 }
3679 static bfd_boolean
3682 {
3683 #define MAXRELOCS 2
3690 bfd_vma sym_value;
3699 /* Massage our args to the form they really have. */
3711 /* We have to do less-strictly-aligned fixes last. */
3714 /* Make a note of the offset within the stubs for this entry. */
3720 /* This is the address of the stub destination. */
3730 {
3732 {
3734 {
3737 {
3738 /* We've borrowed the reloc_addend field to mean we should
3739 insert a condition code into this (Thumb-1 branch)
3740 instruction. See THUMB16_BCOND_INSN. */
3743 }
3746 }
3756 {
3759 }
3766 /* Handle cases where the target is encoded within the
3767 instruction. */
3769 {
3772 }
3786 }
3787 }
3791 /* Stub size has already been computed in arm_size_one_stub. Check
3792 consistency. */
3795 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
3799 /* Assume there is at least one and at most MAXRELOCS entries to relocate
3800 in each stub. */
3808 {
3809 Elf_Internal_Rela rel;
3810 bfd_boolean unresolved_reloc;
3812 int sym_flags
3823 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
3824 template should refer back to the instruction after the original
3825 branch. */
3828 /* There may be unintended consequences if this is not true. */
3831 /* Note: _bfd_final_link_relocate doesn't handle these relocations
3832 properly. We should probably use this function unconditionally,
3833 rather than only for certain relocations listed in the enclosing
3834 conditional, for the sake of consistency. */
3841 }
3842 else
3843 {
3844 Elf_Internal_Rela rel;
3845 bfd_boolean unresolved_reloc;
3861 }
3864 #undef MAXRELOCS
3865 }
3867 /* Calculate the template, template size and instruction size for a stub.
3868 Return value is the instruction size. */
3870 static unsigned int
3874 {
3889 {
3891 {
3905 }
3906 }
3909 }
3911 /* As above, but don't actually build the stub. Just bump offset so
3912 we know stub section sizes. */
3914 static bfd_boolean
3917 {
3922 /* Massage our args to the form they really have. */
3939 }
3941 /* External entry points for sizing and building linker stubs. */
3943 /* Set up various things so that we can make a list of input sections
3944 for each output section included in the link. Returns -1 on error,
3945 0 when no stubs will be needed, and 1 on success. */
3947 int
3950 {
3956 bfd_size_type amt;
3964 /* Count the number of input BFDs and find the top input section id. */
3968 {
3973 {
3976 }
3977 }
3986 /* We can't use output_bfd->section_count here to find the top output
3987 section index as some sections may have been removed, and
3988 _bfd_strip_section_from_output doesn't renumber the indices. */
3992 {
3995 }
4004 /* For sections we aren't interested in, mark their entries with a
4005 value we can check later. */
4007 do
4014 {
4017 }
4020 }
4022 /* The linker repeatedly calls this function for each input section,
4023 in the order that input sections are linked into output sections.
4024 Build lists of input sections to determine groupings between which
4025 we may insert linker stubs. */
4027 void
4030 {
4037 {
4041 {
4042 /* Steal the link_sec pointer for our list. */
4043 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4044 /* This happens to make the list in reverse order,
4045 which we reverse later. */
4048 }
4049 }
4050 }
4052 /* See whether we can group stub sections together. Grouping stub
4053 sections may result in fewer stubs. More importantly, we need to
4054 put all .init* and .fini* stubs at the end of the .init or
4055 .fini output sections respectively, because glibc splits the
4056 _init and _fini functions into multiple parts. Putting a stub in
4057 the middle of a function is not a good idea. */
4059 static void
4061 bfd_size_type stub_group_size,
4062 bfd_boolean stubs_always_after_branch)
4063 {
4066 do
4067 {
4074 /* Reverse the list: we must avoid placing stubs at the
4075 beginning of the section because the beginning of the text
4076 section may be required for an interrupt vector in bare metal
4077 code. */
4078 #define NEXT_SEC PREV_SEC
4081 {
4082 /* Pop from tail. */
4086 /* Push on head. */
4089 }
4092 {
4096 bfd_vma end_of_next;
4100 {
4104 /* End of NEXT is too far from start, so stop. */
4106 /* Add NEXT to the group. */
4108 }
4110 /* OK, the size from the start to the start of CURR is less
4111 than stub_group_size and thus can be handled by one stub
4112 section. (Or the head section is itself larger than
4113 stub_group_size, in which case we may be toast.)
4114 We should really be keeping track of the total size of
4115 stubs added here, as stubs contribute to the final output
4116 section size. */
4117 do
4118 {
4120 /* Set up this stub group. */
4122 }
4125 /* But wait, there's more! Input sections up to stub_group_size
4126 bytes after the stub section can be handled by it too. */
4128 {
4132 {
4135 /* End of NEXT is too far from stubs, so stop. */
4137 /* Add NEXT to the stub group. */
4141 }
4142 }
4144 }
4145 }
4149 #undef PREV_SEC
4150 #undef NEXT_SEC
4151 }
4153 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4154 erratum fix. */
4156 static int
4158 {
4166 else
4168 }
4173 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4174 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4175 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4176 otherwise. */
4178 static bfd_boolean
4188 {
4201 {
4205 bfd_vma base_vma;
4224 {
4235 /* Span is entirely within a single 4KB region: skip scanning. */
4240 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4242 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4243 * The branch target is in the same 4KB region as the
4244 first half of the branch.
4245 * The instruction before the branch is a 32-bit
4246 length non-branch instruction. */
4248 {
4257 {
4258 /* Load the rest of the insn (in manual-friendly order). */
4261 /* Encoding T4: B<c>.W. */
4263 /* Encoding T1: BL<c>.W. */
4265 /* Encoding T2: BLX<c>.W. */
4267 /* Encoding T3: B<c>.W (not permitted in IT block). */
4270 }
4275 && insn_32bit
4276 && is_32bit_branch
4277 && last_was_32bit
4279 {
4283 bfd_vma target;
4294 {
4299 /* We don't care about the error returned from this
4300 function, only if there is glue or not. */
4307 /* Keep a simpler condition, for the sake of clarity. */
4313 {
4316 else
4318 }
4319 }
4321 /* Check if we have an offending branch instruction. */
4324 /* We've already made a stub for this instruction, e.g.
4325 it's a long branch or a Thumb->ARM stub. Assume that
4326 stub will suffice to work around the A8 erratum (see
4327 setting of always_after_branch above). */
4328 ;
4330 {
4339 }
4341 {
4361 }
4364 {
4367 /* The original instruction is a BL, but the target is
4368 an ARM instruction. If we were not making a stub,
4369 the BL would have been converted to a BLX. Use the
4370 BLX stub instead in that case. */
4373 {
4377 }
4378 /* Conversely, if the original instruction was
4379 BLX but the target is Thumb mode, use the BL
4380 stub. */
4383 {
4387 }
4392 /* If we found a relocation, use the proper destination,
4393 not the offset in the (unrelocated) instruction.
4394 Note this is always done if we switched the stub type
4395 above. */
4397 offset =
4402 /* The BLX stub is ARM-mode code. Adjust the offset to
4403 take the different PC value (+8 instead of +4) into
4404 account. */
4409 {
4413 {
4419 }
4422 {
4423 /* If we're doing a subsequent scan,
4424 check if we've found the same fix as
4425 before, and try and reuse the stub
4426 name. */
4430 {
4434 }
4435 }
4438 {
4442 }
4454 num_a8_fixes++;
4455 }
4456 }
4457 }
4462 }
4463 }
4467 }
4474 }
4476 /* Determine and set the size of the stub section for a final link.
4478 The basic idea here is to examine all the relocations looking for
4479 PC-relative calls to a target that is unreachable with a "bl"
4480 instruction. */
4482 bfd_boolean
4486 bfd_signed_vma group_size,
4489 {
4490 bfd_size_type stub_group_size;
4491 bfd_boolean stubs_always_after_branch;
4502 {
4507 }
4509 /* Propagate mach to stub bfd, because it may not have been
4510 finalized when we created stub_bfd. */
4514 /* Stash our params away. */
4520 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4521 as the first half of a 32-bit branch straddling two 4K pages. This is a
4522 crude way of enforcing that. */
4528 else
4532 {
4533 /* Default values. */
4534 /* Thumb branch range is +-4MB has to be used as the default
4535 maximum size (a given section can contain both ARM and Thumb
4536 code, so the worst case has to be taken into account).
4538 This value is 24K less than that, which allows for 2025
4539 12-byte stubs. If we exceed that, then we will fail to link.
4540 The user will have to relink with an explicit group size
4541 option. */
4543 }
4547 /* If we're applying the cortex A8 fix, we need to determine the
4548 program header size now, because we cannot change it later --
4549 that could alter section placements. Notice the A8 erratum fix
4550 ends up requiring the section addresses to remain unchanged
4551 modulo the page size. That's something we cannot represent
4552 inside BFD, and we don't want to force the section alignment to
4553 be the page size. */
4558 {
4569 {
4576 /* We'll need the symbol table in a second. */
4581 /* Walk over each section attached to the input bfd. */
4585 {
4588 /* If there aren't any relocs, then there's nothing more
4589 to do. */
4595 /* If this section is a link-once section that will be
4596 discarded, then don't create any stubs. */
4601 /* Get the relocs. */
4602 internal_relocs
4608 /* Now examine each relocation. */
4612 {
4617 bfd_vma sym_value;
4618 bfd_vma destination;
4630 {
4632 error_ret_free_internal:
4636 }
4640 hash = elf32_arm_hash_entry
4644 /* Only look for stubs on branch instructions, or
4645 non-relaxed TLSCALL */
4658 : (elf32_arm_local_got_tls_type
4663 /* Now determine the call target, its name, value,
4664 section. */
4672 {
4673 /* A non-relaxed TLS call. The target is the
4674 plt-resident trampoline and nothing to do
4675 with the symbol. */
4681 }
4683 {
4684 /* It's a local symbol. */
4688 {
4689 local_syms
4692 local_syms
4698 }
4707 else
4708 sym_sec =
4712 /* This is an undefined symbol. It can never
4713 be resolved. */
4722 sym_name
4726 }
4727 else
4728 {
4729 /* It's an external symbol. */
4737 {
4744 /* For a destination in a shared library,
4745 use the PLT stub as target address to
4746 decide whether a branch stub is
4747 needed. */
4752 {
4756 destination = (sym_value
4759 }
4764 }
4767 {
4768 /* For a shared library, use the PLT stub as
4769 target address to decide whether a long
4770 branch stub is needed.
4771 For absolute code, they cannot be handled. */
4779 {
4783 destination = (sym_value
4786 }
4787 else
4789 }
4790 else
4791 {
4794 }
4797 }
4799 do
4800 {
4801 /* Determine what (if any) linker stub is needed. */
4809 /* Support for grouping stub sections. */
4812 /* Get the name of this stub. */
4818 /* We've either created a stub for this reloc already,
4819 or we are about to. */
4822 stub_entry = arm_stub_hash_lookup
4826 {
4827 /* The proper stub has already been created. */
4831 }
4834 htab);
4836 {
4839 }
4854 {
4857 }
4859 /* For historical reasons, use the existing names for
4860 ARM-to-Thumb and Thumb-to-ARM stubs. */
4871 else
4873 sym_name);
4876 }
4879 /* Look for relocations which might trigger Cortex-A8
4880 erratum. */
4886 {
4892 {
4893 /* Found a candidate. Note we haven't checked the
4894 destination is within 4K here: if we do so (and
4895 don't create an entry in a8_relocs) we can't tell
4896 that a branch should have been relocated when
4897 scanning later. */
4899 {
4905 }
4915 num_a8_relocs++;
4916 }
4917 }
4918 }
4920 /* We're done with the internal relocs, free them. */
4923 }
4926 {
4927 /* Sort relocs which might apply to Cortex-A8 erratum. */
4932 /* Scan for branches which might trigger Cortex-A8 erratum. */
4939 }
4940 }
4948 /* OK, we've added some stubs. Find out the new size of the
4949 stub sections. */
4953 {
4954 /* Ignore non-stub sections. */
4959 }
4963 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
4966 {
4973 stub_sec->size
4975 NULL);
4976 }
4979 /* Ask the linker to do its stuff. */
4981 }
4983 /* Add stubs for Cortex-A8 erratum fixes now. */
4985 {
4987 {
5000 {
5003 stub_name);
5005 }
5024 }
5026 /* Stash the Cortex-A8 erratum fix array for use later in
5027 elf32_arm_write_section(). */
5030 }
5031 else
5032 {
5035 }
5038 error_ret_free_local:
5040 }
5042 /* Build all the stubs associated with the current output file. The
5043 stubs are kept in a hash table attached to the main linker hash
5044 table. We also set up the .plt entries for statically linked PIC
5045 functions here. This function is called via arm_elf_finish in the
5046 linker. */
5048 bfd_boolean
5050 {
5062 {
5063 bfd_size_type size;
5065 /* Ignore non-stub sections. */
5069 /* Allocate memory to hold the linker stubs. */
5075 }
5077 /* Build the stubs as directed by the stub hash table. */
5081 {
5082 /* Place the cortex a8 stubs last. */
5085 }
5088 }
5090 /* Locate the Thumb encoded calling stub for NAME. */
5096 {
5101 /* We need a pointer to the armelf specific hash table. */
5113 hash = elf_link_hash_lookup
5124 }
5126 /* Locate the ARM encoded calling stub for NAME. */
5132 {
5137 /* We need a pointer to the elfarm specific hash table. */
5149 myh = elf_link_hash_lookup
5160 }
5162 /* ARM->Thumb glue (static images):
5164 .arm
5165 __func_from_arm:
5166 ldr r12, __func_addr
5167 bx r12
5168 __func_addr:
5169 .word func @ behave as if you saw a ARM_32 reloc.
5171 (v5t static images)
5172 .arm
5173 __func_from_arm:
5174 ldr pc, __func_addr
5175 __func_addr:
5176 .word func @ behave as if you saw a ARM_32 reloc.
5178 (relocatable images)
5179 .arm
5180 __func_from_arm:
5181 ldr r12, __func_offset
5182 add r12, r12, pc
5183 bx r12
5184 __func_offset:
5185 .word func - . */
5187 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5192 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5196 #define ARM2THUMB_PIC_GLUE_SIZE 16
5201 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5203 .thumb .thumb
5204 .align 2 .align 2
5205 __func_from_thumb: __func_from_thumb:
5206 bx pc push {r6, lr}
5207 nop ldr r6, __func_addr
5208 .arm mov lr, pc
5209 b func bx r6
5210 .arm
5211 ;; back_to_thumb
5212 ldmia r13! {r6, lr}
5213 bx lr
5214 __func_addr:
5215 .word func */
5217 #define THUMB2ARM_GLUE_SIZE 8
5222 #define VFP11_ERRATUM_VENEER_SIZE 8
5224 #define ARM_BX_VENEER_SIZE 12
5229 #ifndef ELFARM_NABI_C_INCLUDED
5230 static void
5232 {
5237 {
5238 /* Do not include empty glue sections in the output. */
5240 {
5244 }
5246 }
5257 }
5259 bfd_boolean
5261 {
5269 ARM2THUMB_GLUE_SECTION_NAME);
5273 THUMB2ARM_GLUE_SECTION_NAME);
5277 VFP11_ERRATUM_VENEER_SECTION_NAME);
5281 ARM_BX_GLUE_SECTION_NAME);
5284 }
5286 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5287 returns the symbol identifying the stub. */
5292 {
5299 bfd_vma val;
5300 bfd_size_type size;
5306 s = bfd_get_section_by_name
5318 myh = elf_link_hash_lookup
5322 {
5323 /* We've already seen this guy. */
5326 }
5328 /* The only trick here is using hash_table->arm_glue_size as the value.
5329 Even though the section isn't allocated yet, this is where we will be
5330 putting it. The +1 on the value marks that the stub has not been
5331 output yet - not that it is a Thumb function. */
5349 else
5356 }
5358 /* Allocate space for ARMv4 BX veneers. */
5360 static void
5362 {
5368 bfd_vma val;
5370 /* BX PC does not need a veneer. */
5378 /* Check if this veneer has already been allocated. */
5382 s = bfd_get_section_by_name
5387 /* Add symbol for veneer. */
5395 myh = elf_link_hash_lookup
5413 }
5416 /* Add an entry to the code/data map for section SEC. */
5418 static void
5420 {
5425 {
5430 }
5435 {
5440 }
5443 {
5446 }
5447 }
5450 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5451 veneers are handled for now. */
5453 static bfd_vma
5459 {
5465 bfd_vma val;
5473 s = bfd_get_section_by_name
5488 myh = elf_link_hash_lookup
5503 /* Link veneer back to calling location. */
5517 /* A symbol for the return from the veneer. */
5521 myh = elf_link_hash_lookup
5538 /* Generate a mapping symbol for the veneer section, and explicitly add an
5539 entry for that symbol to the code/data map for the section. */
5541 {
5543 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5544 ever requires this erratum fix. */
5554 /* The elf32_arm_init_maps function only cares about symbols from input
5555 BFDs. We must make a note of this generated mapping symbol
5556 ourselves so that code byteswapping works properly in
5557 elf32_arm_write_section. */
5559 }
5565 /* The offset of the veneer. */
5567 }
5569 #define ARM_GLUE_SECTION_FLAGS \
5570 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5571 | SEC_READONLY | SEC_LINKER_CREATED)
5573 /* Create a fake section for use by the ARM backend of the linker. */
5575 static bfd_boolean
5577 {
5582 /* Already made. */
5591 /* Set the gc mark to prevent the section from being removed by garbage
5592 collection, despite the fact that no relocs refer to this section. */
5596 }
5598 /* Add the glue sections to ABFD. This function is called from the
5599 linker scripts in ld/emultempl/{armelf}.em. */
5601 bfd_boolean
5604 {
5605 /* If we are only performing a partial
5606 link do not bother adding the glue. */
5614 }
5616 /* Select a BFD to be used to hold the sections used by the glue code.
5617 This function is called from the linker scripts in ld/emultempl/
5618 {armelf/pe}.em. */
5620 bfd_boolean
5622 {
5625 /* If we are only performing a partial link
5626 do not bother getting a bfd to hold the glue. */
5630 /* Make sure we don't attach the glue sections to a dynamic object. */
5639 /* Save the bfd for later use. */
5643 }
5645 static void
5647 {
5651 }
5653 bfd_boolean
5656 {
5665 /* If we are only performing a partial link do not bother
5666 to construct any glue. */
5670 /* Here we have a bfd that is to be included on the link. We have a
5671 hook to do reloc rummaging, before section sizes are nailed down. */
5678 {
5680 abfd);
5682 }
5684 /* PR 5398: If we have not decided to include any loadable sections in
5685 the output then we will not have a glue owner bfd. This is OK, it
5686 just means that there is nothing else for us to do here. */
5690 /* Rummage around all the relocs and map the glue vectors. */
5697 {
5706 /* Load the relocs. */
5707 internal_relocs
5715 {
5724 /* These are the only relocation types we care about. */
5729 /* Get the section contents if we haven't done so already. */
5731 {
5732 /* Get cached copy if it exists. */
5735 else
5736 {
5737 /* Go get them off disk. */
5740 }
5741 }
5744 {
5750 }
5752 /* If the relocation is not against a symbol it cannot concern us. */
5755 /* We don't care about local symbols. */
5759 /* This is an external symbol. */
5764 /* If the relocation is against a static symbol it must be within
5765 the current section and so cannot be a cross ARM/Thumb relocation. */
5769 /* If the call will go through a PLT entry then we do not need
5770 glue. */
5775 {
5777 /* This one is a call from arm code. We need to look up
5778 the target of the call. If it is a thumb target, we
5779 insert glue. */
5786 }
5787 }
5798 }
5802 error_return:
5811 }
5812 #endif
5815 /* Initialise maps of ARM/Thumb/data for input BFDs. */
5817 void
5819 {
5824 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
5834 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
5835 should contain the number of local symbols, which should come before any
5836 global symbols. Mapping symbols are always local. */
5838 NULL);
5840 /* No internal symbols read? Skip this BFD. */
5845 {
5852 {
5857 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
5859 }
5860 }
5861 }
5864 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
5865 say what they wanted. */
5867 void
5869 {
5877 {
5878 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
5883 else
5885 }
5886 }
5889 void
5891 {
5897 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
5899 {
5901 {
5908 /* Give a warning, but do as the user requests anyway. */
5911 }
5912 }
5914 /* For earlier architectures, we might need the workaround, but do not
5915 enable it by default. If users is running with broken hardware, they
5916 must enable the erratum fix explicitly. */
5918 }
5921 enum bfd_arm_vfp11_pipe
5922 {
5923 VFP11_FMAC,
5924 VFP11_LS,
5925 VFP11_DS,
5926 VFP11_BAD
5927 };
5929 /* Return a VFP register number. This is encoded as RX:X for single-precision
5930 registers, or X:RX for double-precision registers, where RX is the group of
5931 four bits in the instruction encoding and X is the single extension bit.
5932 RX and X fields are specified using their lowest (starting) bit. The return
5933 value is:
5935 0...31: single-precision registers s0...s31
5936 32...63: double-precision registers d0...d31.
5938 Although X should be zero for VFP11 (encoding d0...d15 only), we might
5939 encounter VFP3 instructions, so we allow the full range for DP registers. */
5941 static unsigned int
5944 {
5947 else
5949 }
5951 /* Set bits in *WMASK according to a register number REG as encoded by
5952 bfd_arm_vfp11_regno(). Ignore d16-d31. */
5954 static void
5956 {
5961 }
5963 /* Return TRUE if WMASK overwrites anything in REGS. */
5965 static bfd_boolean
5967 {
5971 {
5984 }
5987 }
5989 /* In this function, we're interested in two things: finding input registers
5990 for VFP data-processing instructions, and finding the set of registers which
5991 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
5992 hold the written set, so FLDM etc. are easy to deal with (we're only
5993 interested in 32 SP registers or 16 dp registers, due to the VFP version
5994 implemented by the chip in question). DP registers are marked by setting
5995 both SP registers in the write mask). */
5997 static enum bfd_arm_vfp11_pipe
6000 {
6005 {
6015 {
6037 vfp_binop:
6045 {
6050 {
6064 /* These instructions will not bounce due to underflow. */
6070 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6071 registers to cause the erratum in previous instructions. */
6077 {
6082 /* Only FCVTSD can underflow. */
6089 }
6094 }
6095 }
6100 }
6101 }
6102 /* Two-register transfer. */
6104 {
6108 {
6111 else
6112 {
6115 }
6116 }
6119 }
6121 {
6126 {
6133 {
6141 }
6151 }
6154 }
6155 /* Single-register transfer. Note L==0. */
6157 {
6162 {
6165 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6166 destination register. I don't know if this is exactly right,
6167 but it is the conservative choice. */
6173 }
6176 }
6179 }
6185 /* Look for potentially-troublesome code sequences which might trigger the
6186 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6187 (available from ARM) for details of the erratum. A short version is
6188 described in ld.texinfo. */
6190 bfd_boolean
6192 {
6203 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6204 The states transition as follows:
6206 0 -> 1 (vector) or 0 -> 2 (scalar)
6207 A VFP FMAC-pipeline instruction has been seen. Fill
6208 regs[0]..regs[numregs-1] with its input operands. Remember this
6209 instruction in 'first_fmac'.
6211 1 -> 2
6212 Any instruction, except for a VFP instruction which overwrites
6213 regs[*].
6215 1 -> 3 [ -> 0 ] or
6216 2 -> 3 [ -> 0 ]
6217 A VFP instruction has been seen which overwrites any of regs[*].
6218 We must make a veneer! Reset state to 0 before examining next
6219 instruction.
6221 2 -> 0
6222 If we fail to match anything in state 2, reset to state 0 and reset
6223 the instruction pointer to the instruction after 'first_fmac'.
6225 If the VFP11 vector mode is in use, there must be at least two unrelated
6226 instructions between anti-dependent VFP11 instructions to properly avoid
6227 triggering the erratum, hence the use of the extra state 1. */
6229 /* If we are only performing a partial link do not bother
6230 to construct any glue. */
6234 /* Skip if this bfd does not correspond to an ELF image. */
6238 /* We should have chosen a fix type by the time we get here. */
6244 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6249 {
6253 /* If we don't have executable progbits, we're not interested in this
6254 section. Also skip if section is to be excluded. */
6274 elf32_arm_compare_mapping);
6277 {
6283 /* FIXME: Only ARM mode is supported at present. We may need to
6284 support Thumb-2 mode also at some point. */
6289 {
6304 {
6308 /* I'm assuming the VFP11 erratum can trigger with denorm
6309 operands on either the FMAC or the DS pipeline. This might
6310 lead to slightly overenthusiastic veneer insertion. */
6312 {
6316 }
6320 {
6323 other_regs,
6327 numregs))
6329 else
6331 }
6335 {
6338 other_regs,
6342 numregs))
6344 else
6345 {
6348 }
6349 }
6354 }
6357 {
6366 {
6373 }
6376 first_fmac);
6384 }
6387 }
6388 }
6394 }
6398 error_return:
6404 }
6406 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6407 after sections have been laid out, using specially-named symbols. */
6409 void
6412 {
6420 /* Skip if this bfd does not correspond to an ELF image. */
6432 {
6437 {
6439 bfd_vma vma;
6442 {
6445 /* Find veneer symbol. */
6449 myh = elf_link_hash_lookup
6465 /* Find return location. */
6469 myh = elf_link_hash_lookup
6485 }
6486 }
6487 }
6490 }
6493 /* Set target relocation values needed during linking. */
6495 void
6502 bfd_arm_vfp11_fix vfp11_fix,
6505 {
6519 else
6520 {
6522 target2_type);
6523 }
6533 }
6535 /* Replace the target offset of a Thumb bl or b.w instruction. */
6537 static void
6539 {
6540 bfd_vma upper;
6541 bfd_vma lower;
6558 }
6560 /* Thumb code calling an ARM function. */
6562 static int
6570 bfd_vma offset,
6571 bfd_signed_vma addend,
6572 bfd_vma val,
6574 {
6576 bfd_vma my_offset;
6592 THUMB2ARM_GLUE_SECTION_NAME);
6599 {
6603 {
6610 }
6621 ret_offset =
6622 /* Address of destination of the stub. */
6625 /* Offset from the start of the current section
6626 to the start of the stubs. */
6628 /* Offset of the start of this stub from the start of the stubs. */
6629 + my_offset
6630 /* Address of the start of the current section. */
6632 /* The branch instruction is 4 bytes into the stub. */
6634 /* ARM branches work from the pc of the instruction + 8. */
6640 }
6644 /* Now go back and fix up the original BL insn to point to here. */
6645 ret_offset =
6646 /* Address of where the stub is located. */
6648 /* Address of where the BL is located. */
6651 /* Addend in the relocation. */
6652 - addend
6653 /* Biassing for PC-relative addressing. */
6659 }
6661 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
6669 bfd_vma val,
6672 {
6673 bfd_vma my_offset;
6689 {
6693 {
6698 }
6705 {
6706 /* For relocatable objects we can't use absolute addresses,
6707 so construct the address from a relative offset. */
6708 /* TODO: If the offset is small it's probably worth
6709 constructing the address with adds. */
6716 /* Adjust the offset by 4 for the position of the add,
6717 and 8 for the pipeline offset. */
6724 }
6726 {
6730 /* It's a thumb address. Add the low order bit. */
6733 }
6734 else
6735 {
6742 /* It's a thumb address. Add the low order bit. */
6747 }
6748 }
6753 }
6755 /* Arm code calling a Thumb function. */
6757 static int
6765 bfd_vma offset,
6766 bfd_signed_vma addend,
6767 bfd_vma val,
6769 {
6771 bfd_vma my_offset;
6782 ARM2THUMB_GLUE_SECTION_NAME);
6796 /* Somehow these are both 4 too far, so subtract 8. */
6798 + my_offset
6810 }
6812 /* Populate Arm stub for an exported Thumb function. */
6814 static bfd_boolean
6816 {
6823 bfd_vma val;
6827 /* Allocate stubs for exported Thumb functions on v4t. */
6836 ARM2THUMB_GLUE_SECTION_NAME);
6854 }
6856 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
6858 static bfd_vma
6860 {
6862 bfd_vma glue_addr;
6871 ARM_BX_GLUE_SECTION_NAME);
6881 {
6887 }
6890 }
6892 /* Generate Arm stubs for exported Thumb symbols. */
6893 static void
6896 {
6900 /* Ignore this if we are not called by the ELF backend linker. */
6907 /* If blx is available then exported Thumb symbols are OK and there is
6908 nothing to do. */
6913 link_info);
6914 }
6916 /* Reserve space for COUNT dynamic relocations in relocation selection
6917 SRELOC. */
6919 static void
6921 bfd_size_type count)
6922 {
6930 }
6932 /* Add relocation REL to the end of relocation section SRELOC. */
6934 static void
6937 {
6949 }
6951 /* Some relocations map to different relocations depending on the
6952 target. Return the real relocation. */
6954 static int
6957 {
6959 {
6963 else
6971 }
6972 }
6974 /* Return the base VMA address which should be subtracted from real addresses
6975 when resolving @dtpoff relocation.
6976 This is PT_TLS segment p_vaddr. */
6978 static bfd_vma
6980 {
6981 /* If tls_sec is NULL, we should have signalled an error already. */
6985 }
6987 /* Return the relocation value for @tpoff relocation
6988 if STT_TLS virtual address is ADDRESS. */
6990 static bfd_vma
6992 {
6994 bfd_vma base;
6996 /* If tls_sec is NULL, we should have signalled an error already. */
7001 }
7003 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7004 VALUE is the relocation value. */
7006 static bfd_reloc_status_type
7008 {
7015 }
7017 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7018 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7019 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7021 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7022 is to then call final_link_relocate. Return other values in the
7023 case of error.
7025 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7026 the pre-relaxed code. It would be nice if the relocs were updated
7027 to match the optimization. */
7029 static bfd_reloc_status_type
7033 {
7037 {
7044 else
7045 {
7049 else
7051 }
7056 /* Thumb insn. */
7059 {
7061 /* nop */
7063 }
7065 {
7067 /* nop */
7069 else
7070 /* ldr rx,[ry] */
7072 }
7074 {
7076 /* nop */
7078 else
7079 /* mov r0, rx */
7082 }
7083 else
7084 {
7086 /* It's a 32 bit instruction, fetch the rest of it for
7087 error generation. */
7094 }
7098 /* arm insn. */
7101 {
7103 /* mov rx, ry */
7106 }
7108 {
7110 /* nop */
7112 else
7113 /* ldr rx,[ry] */
7116 }
7118 {
7120 /* nop */
7122 else
7123 /* mov r0, rx */
7126 }
7127 else
7128 {
7133 }
7137 /* GD->IE relaxation, turn the instruction into 'nop' or
7138 'ldr r0, [pc,r0]' */
7144 /* GD->IE relaxation */
7146 /* add r0,pc; ldr r0, [r0] */
7149 /* nop.w */
7151 else
7152 /* nop; nop */
7158 }
7160 }
7162 /* For a given value of n, calculate the value of G_n as required to
7163 deal with group relocations. We return it in the form of an
7164 encoded constant-and-rotation, together with the final residual. If n is
7165 specified as less than zero, then final_residual is filled with the
7166 input value and no further action is performed. */
7168 static bfd_vma
7170 {
7172 bfd_vma g_n;
7177 {
7180 /* Calculate which part of the value to mask. */
7183 else
7184 {
7187 /* Determine the most significant bit in the residual and
7188 align the resulting value to a 2-bit boundary. */
7193 /* The desired shift is now (msb - 6), or zero, whichever
7194 is the greater. */
7198 }
7200 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7205 /* Calculate the residual for the next time around. */
7207 }
7212 }
7214 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7215 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7217 static int
7219 {
7229 }
7231 /* Perform a relocation as part of a final link. */
7233 static bfd_reloc_status_type
7240 bfd_vma value,
7248 {
7258 bfd_vma addend;
7259 bfd_signed_vma signed_addend;
7268 /* Some relocation types map to different relocations depending on the
7269 target. We pick the right one here. */
7272 /* It is possible to have linker relaxations on some TLS access
7273 models. Update our information here. */
7279 /* If the start address has been set, then set the EF_ARM_HASENTRY
7280 flag. Setting this more than once is redundant, but the cost is
7281 not too high, and it keeps the code simple.
7283 The test is done here, rather than somewhere else, because the
7284 start address is only set just before the final link commences.
7286 Note - if the user deliberately sets a start address of 0, the
7287 flag will not be set. */
7300 {
7304 {
7308 }
7309 else
7311 }
7312 else
7316 {
7318 /* We don't need to find a value for this symbol. It's just a
7319 marker. */
7337 /* Handle relocations which should use the PLT entry. ABS32/REL32
7338 will use the symbol's value, which may point to a PLT entry, but we
7339 don't need to handle that here. If we created a PLT entry, all
7340 branches in this object should go to it, except if the PLT is too
7341 far away, in which case a long branch stub should be inserted. */
7350 {
7351 /* If we've created a .plt section, and assigned a PLT entry to
7352 this function, it should not be known to bind locally. If
7353 it were, we would have cleared the PLT entry. */
7363 }
7365 /* When generating a shared object or relocatable executable, these
7366 relocations are copied into the output file to be resolved at
7367 run time. */
7384 {
7385 Elf_Internal_Rela outrel;
7391 {
7397 }
7421 else
7422 {
7425 /* This symbol is local, or marked to become local. */
7429 {
7432 /* On Symbian OS, the data segment and text segement
7433 can be relocated independently. Therefore, we
7434 must indicate the segment to which this
7435 relocation is relative. The BPABI allows us to
7436 use any symbol in the right segment; we just use
7437 the section symbol as it is convenient. (We
7438 cannot use the symbol given by "h" directly as it
7439 will not appear in the dynamic symbol table.)
7441 Note that the dynamic linker ignores the section
7442 symbol value, so we don't subtract osec->vma
7443 from the emitted reloc addend. */
7446 else
7450 {
7456 else
7459 }
7461 }
7462 else
7463 /* On SVR4-ish systems, the dynamic loader cannot
7464 relocate the text and data segments independently,
7465 so the symbol does not matter. */
7470 else
7472 }
7476 /* If this reloc is against an external symbol, we do not want to
7477 fiddle with the addend. Otherwise, we need to include the symbol
7478 value so that it becomes an addend for the dynamic reloc. */
7485 }
7487 {
7496 {
7500 {
7501 /* Check for Arm calling Arm function. */
7502 /* FIXME: Should we translate the instruction into a BL
7503 instruction instead ? */
7507 input_bfd,
7509 }
7511 {
7512 /* Check for Arm calling Thumb function. */
7514 {
7519 error_message))
7521 else
7523 }
7524 }
7526 /* Check if a stub has to be inserted because the
7527 destination is too far or we are changing mode. */
7531 {
7542 {
7543 /* The target is out of reach, so redirect the
7544 branch to the local stub for this function. */
7549 stub_type);
7554 }
7555 else
7556 {
7557 /* If the call goes through a PLT entry, make sure to
7558 check distance to the right destination address. */
7562 {
7567 /* The PLT entry is in ARM mode, regardless of the
7568 target function. */
7570 }
7571 }
7572 }
7574 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
7575 where:
7576 S is the address of the symbol in the relocation.
7577 P is address of the instruction being relocated.
7578 A is the addend (extracted from the instruction) in bytes.
7580 S is held in 'value'.
7581 P is the base address of the section containing the
7582 instruction plus the offset of the reloc into that
7583 section, ie:
7584 (input_section->output_section->vma +
7585 input_section->output_offset +
7586 rel->r_offset).
7587 A is the addend, converted into bytes, ie:
7588 (signed_addend * 4)
7590 Note: None of these operations have knowledge of the pipeline
7591 size of the processor, thus it is up to the assembler to
7592 encode this information into the addend. */
7598 else
7599 /* RELA addends do not have to be adjusted by howto->size. */
7605 /* A branch to an undefined weak symbol is turned into a jump to
7606 the next instruction unless a PLT entry will be created.
7607 Do the same for local undefined symbols (but not for STN_UNDEF).
7608 The jump to the next instruction is optimized as a NOP depending
7609 on the architecture. */
7613 {
7618 else
7620 }
7621 else
7622 {
7623 /* Perform a signed range check. */
7634 {
7635 /* Set the H bit in the BLX instruction. */
7637 {
7640 else
7642 }
7644 /* Select the correct instruction (BL or BLX). */
7645 /* Only if we are not handling a BL to a stub. In this
7646 case, mode switching is performed by the stub. */
7649 else
7650 {
7653 }
7654 }
7655 }
7656 }
7688 {
7689 /* Check for overflow. */
7692 }
7698 }
7706 /* There is no way to tell whether the user intended to use a signed or
7707 unsigned addend. When checking for overflow we accept either,
7708 as specified by the AAELF. */
7718 /* See comment for R_ARM_ABS8. */
7726 /* Support ldr and str instructions for the thumb. */
7728 {
7729 /* Need to refetch addend. */
7731 /* ??? Need to determine shift amount from operand size. */
7733 }
7736 /* ??? Isn't value unsigned? */
7740 /* ??? Value needs to be properly shifted into place first. */
7746 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
7747 {
7748 bfd_vma insn;
7749 bfd_signed_vma relocation;
7755 {
7760 }
7782 }
7785 /* PR 10073: This reloc is not generated by the GNU toolchain,
7786 but it is supported for compatibility with third party libraries
7787 generated by other compilers, specifically the ARM/IAR. */
7788 {
7789 bfd_vma insn;
7790 bfd_signed_vma relocation;
7804 /* We do not check for overflow of this reloc. Although strictly
7805 speaking this is incorrect, it appears to be necessary in order
7806 to work with IAR generated relocs. Since GCC and GAS do not
7807 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
7808 a problem for them. */
7816 }
7819 /* Corresponds to: ldr.w reg, [pc, #offset]. */
7820 {
7821 bfd_vma insn;
7822 bfd_signed_vma relocation;
7828 {
7832 }
7852 }
7857 /* Thumb BL (branch long instruction). */
7858 {
7859 bfd_vma relocation;
7860 bfd_vma reloc_sign;
7864 bfd_signed_vma reloc_signed_max;
7865 bfd_signed_vma reloc_signed_min;
7866 bfd_vma check;
7867 bfd_signed_vma signed_check;
7871 /* A branch to an undefined weak symbol is turned into a jump to
7872 the next instruction unless a PLT entry will be created.
7873 The jump to the next instruction is optimized as a NOP.W for
7874 Thumb-2 enabled architectures. */
7877 {
7879 {
7882 }
7883 else
7884 {
7887 }
7889 }
7891 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
7892 with Thumb-1) involving the J1 and J2 bits. */
7894 {
7904 /* Sign extend. */
7908 }
7911 {
7912 /* Check for Thumb to Thumb call. */
7913 /* FIXME: Should we translate the instruction into a BL
7914 instruction instead ? */
7918 input_bfd,
7920 }
7921 else
7922 {
7923 /* If it is not a call to Thumb, assume call to Arm.
7924 If it is a call relative to a section name, then it is not a
7925 function call at all, but rather a long jump. Calls through
7926 the PLT do not require stubs. */
7930 {
7932 {
7933 /* Convert BL to BLX. */
7935 }
7938 {
7942 error_message))
7944 else
7946 }
7947 }
7950 {
7951 /* Make sure this is a BL. */
7953 }
7954 }
7958 {
7959 /* Check if a stub has to be inserted because the destination
7960 is too far. */
7971 {
7972 /* The target is out of reach or we are changing modes, so
7973 redirect the branch to the local stub for this
7974 function. */
7978 stub_type);
7984 /* If this call becomes a call to Arm, force BLX. */
7986 {
7991 }
7992 }
7993 }
7995 /* Handle calls via the PLT. */
8000 {
8006 {
8007 /* If the Thumb BLX instruction is available, convert
8008 the BL to a BLX instruction to call the ARM-mode
8009 PLT entry. */
8012 }
8013 else
8014 {
8015 /* Target the Thumb stub before the ARM PLT entry. */
8018 }
8020 }
8030 /* If this is a signed value, the rightshift just dropped
8031 leading 1 bits (assuming twos complement). */
8034 else
8037 /* Calculate the permissable maximum and minimum values for
8038 this relocation according to whether we're relocating for
8039 Thumb-2 or not. */
8046 /* Assumes two's complement. */
8051 /* For a BLX instruction, make sure that the relocation is rounded up
8052 to a word boundary. This follows the semantics of the instruction
8053 which specifies that bit 1 of the target address will come from bit
8054 1 of the base address. */
8057 /* Put RELOCATION back into the insn. Assumes two's complement.
8058 We use the Thumb-2 encoding, which is safe even if dealing with
8059 a Thumb-1 instruction by virtue of our overflow check above. */
8069 /* Put the relocated value back in the object file: */
8074 }
8078 /* Thumb32 conditional branch instruction. */
8079 {
8080 bfd_vma relocation;
8086 bfd_signed_vma signed_check;
8088 /* Need to refetch the addend, reconstruct the top three bits,
8089 and squish the two 11 bit pieces together. */
8091 {
8105 }
8107 /* Handle calls via the PLT. */
8109 {
8113 /* Target the Thumb stub before the ARM PLT entry. */
8116 }
8118 /* ??? Should handle interworking? GCC might someday try to
8119 use this for tail calls. */
8130 /* Put RELOCATION back into the insn. */
8131 {
8140 }
8142 /* Put the relocated value back in the object file: */
8147 }
8152 /* Thumb B (branch) instruction). */
8153 {
8154 bfd_signed_vma relocation;
8157 bfd_signed_vma signed_check;
8159 /* CZB cannot jump backward. */
8164 {
8165 /* Need to refetch addend. */
8168 {
8172 }
8173 else
8175 /* The value in the insn has been right shifted. We need to
8176 undo this, so that we can perform the address calculation
8177 in terms of bytes. */
8179 }
8191 else
8197 /* Assumes two's complement. */
8202 }
8207 {
8208 bfd_vma insn;
8209 bfd_vma relocation;
8213 {
8214 /* Extract the addend. */
8217 }
8227 }
8235 /* Relocation is relative to the start of the
8236 global offset table. */
8242 /* If we are addressing a Thumb function, we need to adjust the
8243 address by one, so that attempts to call the function pointer will
8244 correctly interpret it as Thumb code. */
8248 /* Note that sgot->output_offset is not involved in this
8249 calculation. We always want the start of .got. If we
8250 define _GLOBAL_OFFSET_TABLE in a different way, as is
8251 permitted by the ABI, we might have to change this
8252 calculation. */
8259 /* Use global offset table as symbol value. */
8273 /* Relocation is to the entry for this symbol in the
8274 global offset table. */
8279 {
8280 bfd_vma off;
8285 {
8286 /* We have already processsed one GOT relocation against
8287 this symbol. */
8292 }
8293 else
8294 {
8295 Elf_Internal_Rela outrel;
8298 {
8299 /* If the symbol doesn't resolve locally in a static
8300 object, we have an undefined reference. If the
8301 symbol doesn't resolve locally in a dynamic object,
8302 it should be resolved by the dynamic linker. */
8304 {
8307 }
8308 else
8311 }
8312 else
8313 {
8316 else
8321 }
8323 /* The GOT entry is initialized to zero by default.
8324 See if we should install a different value. */
8327 {
8331 }
8334 {
8339 }
8341 }
8343 }
8344 else
8345 {
8346 bfd_vma off;
8353 /* The offset must always be a multiple of 4. We use the
8354 least significant bit to record whether we have already
8355 generated the necessary reloc. */
8358 else
8359 {
8360 /* If we are addressing a Thumb function, we need to
8361 adjust the address by one, so that attempts to
8362 call the function pointer will correctly
8363 interpret it as Thumb code. */
8371 {
8372 Elf_Internal_Rela outrel;
8382 }
8385 }
8388 }
8404 {
8405 bfd_vma off;
8414 else
8415 {
8416 /* If we don't know the module number, create a relocation
8417 for it. */
8419 {
8420 Elf_Internal_Rela outrel;
8435 }
8436 else
8440 }
8448 }
8457 {
8465 {
8466 bfd_boolean dyn;
8471 {
8474 }
8478 }
8479 else
8480 {
8485 }
8487 /* Linker relaxations happens from one of the
8488 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
8496 else
8497 {
8499 Elf_Internal_Rela outrel;
8502 /* The GOT entries have not been initialized yet. Do it
8503 now, and emit any relocations. If both an IE GOT and a
8504 GD GOT are necessary, we emit the GD first. */
8510 {
8513 }
8516 {
8519 /* We should have relaxed, unless this is an undefined
8520 weak symbol. */
8529 + offplt
8541 /* For globals, the first word in the relocation gets
8542 the relocation index and the top bit set, or zero,
8543 if we're binding now. For locals, it gets the
8544 symbol's offset in the tls section. */
8552 /* Second word in the relocation is always zero. */
8556 }
8558 {
8560 {
8576 else
8577 {
8580 R_ARM_TLS_DTPOFF32);
8589 }
8590 }
8591 else
8592 {
8593 /* If we are not emitting relocations for a
8594 general dynamic reference, then we must be in a
8595 static link or an executable link with the
8596 symbol binding locally. Mark it as belonging
8597 to module 1, the executable. */
8602 }
8605 }
8608 {
8610 {
8613 else
8625 }
8626 else
8630 }
8634 else
8636 }
8645 {
8646 bfd_signed_vma offset;
8647 enum elf32_arm_stub_type stub_type
8654 {
8656 = elf32_arm_get_stub_entry
8662 }
8663 else
8669 {
8678 }
8679 else
8680 {
8681 /* Thumb blx encodes the offset in a complicated
8682 fashion. */
8687 input_section->output_offset
8690 /* Round up the offset to a word boundary */
8703 }
8704 }
8705 /* These relocations needs special care, as besides the fact
8706 they point somewhere in .gotplt, the addend must be
8707 adjusted accordingly depending on the type of instruction
8708 we refer to */
8710 {
8719 {
8726 /* bl/blx */
8729 /* add */
8731 else
8732 {
8738 }
8739 }
8740 else
8741 {
8745 {
8761 }
8762 }
8770 }
8771 else
8780 }
8784 {
8790 }
8791 else
8800 {
8803 /* Ensure that we have a BX instruction. */
8807 {
8808 /* Branch to veneer. */
8809 bfd_vma glue_addr;
8816 }
8817 else
8818 {
8819 /* Preserve Rm (lowest four bits) and the condition code
8820 (highest four bits). Other bits encode MOV PC,Rm. */
8822 }
8825 }
8832 /* Until we properly support segment-base-relative addressing then
8833 we assume the segment base to be zero, as for the group relocations.
8834 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
8835 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
8839 {
8843 {
8846 }
8868 }
8875 /* Until we properly support segment-base-relative addressing then
8876 we assume the segment base to be zero, as for the above relocations.
8877 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
8878 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
8879 as R_ARM_THM_MOVT_ABS. */
8883 {
8884 bfd_vma insn;
8890 {
8896 }
8922 }
8935 {
8939 /* sb should be the origin of the *segment* containing the symbol.
8940 It is not clear how to obtain this OS-dependent value, so we
8941 make an arbitrary choice of zero. */
8943 bfd_vma residual;
8944 bfd_vma g_n;
8945 bfd_signed_vma signed_value;
8948 /* Determine which group of bits to select. */
8950 {
8972 }
8974 /* If REL, extract the addend from the insn. If RELA, it will
8975 have already been fetched for us. */
8977 {
8984 else
8985 {
8986 /* Compensate for the fact that in the instruction, the
8987 rotation is stored in multiples of 2 bits. */
8990 /* Rotate "constant" right by "rotation" bits. */
8993 }
8995 /* Determine if the instruction is an ADD or a SUB.
8996 (For REL, this determines the sign of the addend.) */
8999 {
9005 }
9008 }
9010 /* Compute the value (X) to go in the place. */
9016 /* PC relative. */
9018 else
9019 /* Section base relative. */
9022 /* If the target symbol is a Thumb function, then set the
9023 Thumb bit in the address. */
9027 /* Calculate the value of the relevant G_n, in encoded
9028 constant-with-rotation format. */
9032 /* Check for overflow if required. */
9039 {
9045 }
9047 /* Mask out the value and the ADD/SUB part of the opcode; take care
9048 not to destroy the S bit. */
9051 /* Set the opcode according to whether the value to go in the
9052 place is negative. */
9055 else
9058 /* Encode the offset. */
9062 }
9071 {
9076 bfd_vma residual;
9077 bfd_signed_vma signed_value;
9080 /* Determine which groups of bits to calculate. */
9082 {
9100 }
9102 /* If REL, extract the addend from the insn. If RELA, it will
9103 have already been fetched for us. */
9105 {
9108 }
9110 /* Compute the value (X) to go in the place. */
9114 /* PC relative. */
9116 else
9117 /* Section base relative. */
9120 /* Calculate the value of the relevant G_{n-1} to obtain
9121 the residual at that stage. */
9124 /* Check for overflow. */
9126 {
9132 }
9134 /* Mask out the value and U bit. */
9137 /* Set the U bit if the value to go in the place is non-negative. */
9141 /* Encode the offset. */
9145 }
9154 {
9159 bfd_vma residual;
9160 bfd_signed_vma signed_value;
9163 /* Determine which groups of bits to calculate. */
9165 {
9183 }
9185 /* If REL, extract the addend from the insn. If RELA, it will
9186 have already been fetched for us. */
9188 {
9191 }
9193 /* Compute the value (X) to go in the place. */
9197 /* PC relative. */
9199 else
9200 /* Section base relative. */
9203 /* Calculate the value of the relevant G_{n-1} to obtain
9204 the residual at that stage. */
9207 /* Check for overflow. */
9209 {
9215 }
9217 /* Mask out the value and U bit. */
9220 /* Set the U bit if the value to go in the place is non-negative. */
9224 /* Encode the offset. */
9228 }
9237 {
9242 bfd_vma residual;
9243 bfd_signed_vma signed_value;
9246 /* Determine which groups of bits to calculate. */
9248 {
9266 }
9268 /* If REL, extract the addend from the insn. If RELA, it will
9269 have already been fetched for us. */
9271 {
9274 }
9276 /* Compute the value (X) to go in the place. */
9280 /* PC relative. */
9282 else
9283 /* Section base relative. */
9286 /* Calculate the value of the relevant G_{n-1} to obtain
9287 the residual at that stage. */
9290 /* Check for overflow. (The absolute value to go in the place must be
9291 divisible by four and, after having been divided by four, must
9292 fit in eight bits.) */
9294 {
9300 }
9302 /* Mask out the value and U bit. */
9305 /* Set the U bit if the value to go in the place is non-negative. */
9309 /* Encode the offset. */
9313 }
9318 }
9319 }
9321 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
9322 static void
9326 bfd_signed_vma increment)
9327 {
9328 bfd_signed_vma addend;
9332 {
9350 }
9351 else
9352 {
9353 bfd_vma contents;
9357 /* Get the (signed) value from the instruction. */
9360 {
9361 bfd_signed_vma mask;
9366 }
9368 /* Add in the increment, (which is a byte value). */
9370 {
9382 /* Should we check for overflow here ? */
9384 /* Drop any undesired bits. */
9387 }
9392 }
9393 }
9395 #define IS_ARM_TLS_RELOC(R_TYPE) \
9396 ((R_TYPE) == R_ARM_TLS_GD32 \
9397 || (R_TYPE) == R_ARM_TLS_LDO32 \
9398 || (R_TYPE) == R_ARM_TLS_LDM32 \
9399 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
9400 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
9401 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
9402 || (R_TYPE) == R_ARM_TLS_LE32 \
9403 || (R_TYPE) == R_ARM_TLS_IE32 \
9404 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
9406 /* Specific set of relocations for the gnu tls dialect. */
9407 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
9408 ((R_TYPE) == R_ARM_TLS_GOTDESC \
9409 || (R_TYPE) == R_ARM_TLS_CALL \
9410 || (R_TYPE) == R_ARM_THM_TLS_CALL \
9411 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
9412 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
9414 /* Relocate an ARM ELF section. */
9416 static bfd_boolean
9425 {
9443 {
9450 bfd_vma relocation;
9451 bfd_reloc_status_type r;
9452 arelent bfd_reloc;
9473 {
9478 /* An object file might have a reference to a local
9479 undefined symbol. This is a daft object file, but we
9480 should at least do something about it. V4BX & NONE
9481 relocations do not use the symbol and are explicitly
9482 allowed to use the undefined symbol, so allow those.
9483 Likewise for relocations against STN_UNDEF. */
9489 {
9496 }
9499 {
9506 {
9511 {
9533 {
9539 }
9543 /* Get the (signed) value from the instruction. */
9546 {
9547 bfd_signed_vma mask;
9552 }
9554 }
9557 addend =
9562 /* Cases here must match those in the preceeding
9563 switch statement. */
9565 {
9588 }
9589 }
9590 }
9591 else
9593 }
9594 else
9595 {
9596 bfd_boolean warned;
9604 }
9611 {
9612 /* This is a relocatable link. We don't have to change
9613 anything, unless the reloc is against a section symbol,
9614 in which case we have to adjust according to where the
9615 section symbol winds up in the output section. */
9617 {
9621 else
9623 }
9625 }
9629 else
9630 {
9631 name = (bfd_elf_string_from_elf_section
9635 }
9643 {
9648 input_bfd,
9649 input_section,
9652 name);
9653 }
9655 /* We call elf32_arm_final_link_relocate unless we're completely
9656 done, i.e., the relaxation produced the final output we want,
9657 and we won't let anybody mess with it. Also, we have to do
9658 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
9659 both in relaxed and non-relaxed cases */
9665 {
9668 /* This may have been marked unresolved because it came from
9669 a shared library. But we've just dealt with that. */
9671 }
9672 else
9683 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
9684 because such sections are not SEC_ALLOC and thus ld.so will
9685 not process them. */
9689 {
9692 input_bfd,
9693 input_section,
9698 }
9701 {
9703 {
9705 /* If the overflowing reloc was to an undefined symbol,
9706 we have already printed one error message and there
9707 is no point complaining again. */
9733 /* error_message should already be set. */
9738 /* Fall through. */
9740 common_error:
9747 }
9748 }
9749 }
9752 }
9754 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
9755 adds the edit to the start of the list. (The list must be built in order of
9756 ascending TINDEX: the function's callers are primarily responsible for
9757 maintaining that condition). */
9759 static void
9762 arm_unwind_edit_type type,
9765 {
9774 {
9784 }
9785 else
9786 {
9793 }
9794 }
9798 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
9799 static void
9801 {
9809 /* Adjust size of output section. */
9811 }
9813 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
9814 static void
9816 {
9826 }
9828 /* Scan .ARM.exidx tables, and create a list describing edits which should be
9829 made to those tables, such that:
9831 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
9832 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
9833 codes which have been inlined into the index).
9835 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
9837 The edits are applied when the tables are written
9838 (in elf32_arm_write_section).
9839 */
9841 bfd_boolean
9845 bfd_boolean merge_exidx_entries)
9846 {
9853 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
9854 text sections. */
9856 {
9860 {
9868 {
9869 Elf_Internal_Shdr *linked_hdr
9877 /* Link this .ARM.exidx section back from the text section it
9878 describes. */
9880 }
9881 }
9882 }
9884 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
9885 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
9886 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
9889 {
9896 bfd_vma j;
9907 {
9908 /* Section has no unwind data. */
9912 /* Ignore zero sized sections. */
9919 }
9921 /* Skip /DISCARD/ sections. */
9938 /* An error? */
9942 {
9947 /* An EXIDX_CANTUNWIND entry. */
9949 {
9953 }
9954 /* Inlined unwinding data. Merge if equal to previous. */
9956 {
9962 }
9963 /* Normal table entry. In theory we could merge these too,
9964 but duplicate entries are likely to be much less common. */
9965 else
9969 {
9974 }
9977 }
9979 /* Free contents if we allocated it ourselves. */
9983 /* Record edits to be applied later (in elf32_arm_write_section). */
9992 }
9994 /* Add terminating CANTUNWIND entry. */
9999 }
10001 static bfd_boolean
10004 {
10020 }
10022 static bfd_boolean
10024 {
10031 /* Invoke the regular ELF backend linker to do all the work. */
10035 /* Process stub sections (eg BE8 encoding, ...). */
10039 {
10041 /* Only process it once, in its link_sec slot. */
10043 {
10049 }
10050 }
10052 /* Write out any glue sections now that we have created all the
10053 stubs. */
10055 {
10058 ARM2THUMB_GLUE_SECTION_NAME))
10063 THUMB2ARM_GLUE_SECTION_NAME))
10068 VFP11_ERRATUM_VENEER_SECTION_NAME))
10073 ARM_BX_GLUE_SECTION_NAME))
10075 }
10078 }
10080 /* Set the right machine number. */
10082 static bfd_boolean
10084 {
10095 else
10099 }
10101 /* Function to keep ARM specific flags in the ELF header. */
10103 static bfd_boolean
10105 {
10108 {
10110 {
10113 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
10114 abfd);
10115 else
10116 _bfd_error_handler
10118 abfd);
10119 }
10120 }
10121 else
10122 {
10125 }
10128 }
10130 /* Copy backend specific data from one object module to another. */
10132 static bfd_boolean
10134 {
10135 flagword in_flags;
10136 flagword out_flags;
10147 {
10148 /* Cannot mix APCS26 and APCS32 code. */
10152 /* Cannot mix float APCS and non-float APCS code. */
10156 /* If the src and dest have different interworking flags
10157 then turn off the interworking bit. */
10159 {
10161 _bfd_error_handler
10162 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
10166 }
10168 /* Likewise for PIC, though don't warn for this case. */
10171 }
10176 /* Also copy the EI_OSABI field. */
10180 /* Copy object attributes. */
10184 }
10186 /* Values for Tag_ABI_PCS_R9_use. */
10187 enum
10188 {
10189 AEABI_R9_V6,
10190 AEABI_R9_SB,
10191 AEABI_R9_TLS,
10192 AEABI_R9_unused
10193 };
10195 /* Values for Tag_ABI_PCS_RW_data. */
10196 enum
10197 {
10198 AEABI_PCS_RW_data_absolute,
10199 AEABI_PCS_RW_data_PCrel,
10200 AEABI_PCS_RW_data_SBrel,
10201 AEABI_PCS_RW_data_unused
10202 };
10204 /* Values for Tag_ABI_enum_size. */
10205 enum
10206 {
10207 AEABI_enum_unused,
10208 AEABI_enum_short,
10209 AEABI_enum_wide,
10210 AEABI_enum_forced_wide
10211 };
10213 /* Determine whether an object attribute tag takes an integer, a
10214 string or both. */
10216 static int
10218 {
10227 else
10229 }
10231 /* The ABI defines that Tag_conformance should be emitted first, and that
10232 Tag_nodefaults should be second (if either is defined). This sets those
10233 two positions, and bumps up the position of all the remaining tags to
10234 compensate. */
10235 static int
10237 {
10247 }
10249 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
10250 static bfd_boolean
10252 {
10254 {
10255 _bfd_error_handler
10260 }
10261 else
10262 {
10263 _bfd_error_handler
10267 }
10268 }
10270 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
10271 Returns -1 if no architecture could be read. */
10273 static int
10275 {
10279 /* Note: the tag and its argument below are uleb128 values, though
10280 currently-defined values fit in one byte for each. */
10287 /* This tag is "safely ignorable", so don't complain if it looks funny. */
10289 }
10291 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
10292 The tag is removed if ARCH is -1. */
10294 static void
10296 {
10301 {
10304 }
10306 /* Note: the tag and its argument below are uleb128 values, though
10307 currently-defined values fit in one byte for each. */
10313 }
10315 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
10316 into account. */
10318 static int
10321 {
10322 #define T(X) TAG_CPU_ARCH_##X
10325 {
10335 };
10337 {
10348 };
10350 {
10362 };
10364 {
10377 };
10379 {
10393 };
10395 {
10410 };
10412 {
10428 };
10430 {
10431 v6t2,
10432 v6k,
10433 v7,
10434 v6_m,
10435 v6s_m,
10436 v7e_m,
10437 /* Pseudo-architecture. */
10438 v4t_plus_v6_m
10439 };
10441 /* Check we've not got a higher architecture than we know about. */
10444 {
10447 }
10449 /* Override old tag if we have a Tag_also_compatible_with on the output. */
10455 /* And override the new tag if we have a Tag_also_compatible_with on the
10456 input. */
10465 /* Architectures before V6KZ add features monotonically. */
10471 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
10472 as the canonical version. */
10474 {
10477 }
10478 else
10482 {
10486 }
10489 #undef T
10490 }
10492 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
10493 are conflicting attributes. */
10495 static bfd_boolean
10497 {
10500 /* Some tags have 0 = don't care, 1 = strong requirement,
10501 2 = weak requirement. */
10506 /* Skip the linker stubs file. This preserves previous behavior
10507 of accepting unknown attributes in the first input file - but
10508 is that a bug? */
10513 {
10514 /* This is the first object. Copy the attributes. */
10519 /* Use the Tag_null value to indicate the attributes have been
10520 initialized. */
10523 /* We do not output objects with Tag_MPextension_use_legacy - we move
10524 the attribute's value to Tag_MPextension_use. */
10526 {
10530 {
10531 _bfd_error_handler
10535 }
10541 }
10544 }
10548 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
10550 {
10551 /* Ignore mismatches if the object doesn't use floating point. */
10555 {
10556 _bfd_error_handler
10561 }
10562 }
10565 {
10566 /* Merge this attribute with existing attributes. */
10568 {
10571 /* These are merged after Tag_CPU_arch. */
10576 /* Use the first value seen. */
10580 {
10584 /* These aren't real CPU names, but we can't guess
10585 that from the architecture version alone. */
10598 "ARM v6S-M"
10599 };
10601 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
10607 secondary_compat);
10610 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
10614 {
10615 /* The output architecture has been changed to match the
10616 input architecture. Use the input names. */
10623 }
10624 else
10625 {
10628 }
10630 /* If we still don't have a value for Tag_CPU_name,
10631 make one up now. Tag_CPU_raw_name remains blank. */
10636 }
10643 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
10652 /* Use the largest value specified. */
10659 /* Use the smallest value specified. */
10668 {
10669 /* This error message should be enabled once all non-conformant
10670 binaries in the toolchain have had the attributes set
10671 properly.
10672 _bfd_error_handler
10673 (_("error: %B: 8-byte data alignment conflicts with %B"),
10674 obfd, ibfd);
10675 result = FALSE; */
10676 }
10677 /* Fall through. */
10680 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
10681 value if greater than 2 (for future-proofing). */
10689 /* The virtualization tag effectively stores two bits of
10690 information: the intended use of TrustZone (in bit 0), and the
10691 intended use of Virtualization (in bit 1). */
10696 {
10699 else
10700 {
10701 _bfd_error_handler
10706 }
10707 }
10712 {
10713 /* 0 will merge with anything.
10714 'A' and 'S' merge to 'A'.
10715 'R' and 'S' merge to 'R'.
10716 'M' and 'A|R|S' is an error. */
10725 else
10726 {
10727 _bfd_error_handler
10729 ibfd,
10733 }
10734 }
10737 {
10738 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
10739 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
10740 when it's 0. It might mean absence of FP hardware if
10741 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
10743 static const struct
10744 {
10748 {
10756 };
10761 /* If the output has no requirement about FP hardware,
10762 follow the requirement of the input. */
10764 {
10770 }
10771 /* If the input has no requirement about FP hardware, do
10772 nothing. */
10774 {
10777 }
10779 /* Both the input and the output have nonzero Tag_FP_arch.
10780 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
10782 /* If both the input and the output have zero Tag_ABI_HardFP_use,
10783 do nothing. */
10786 ;
10787 /* If the input and the output have different Tag_ABI_HardFP_use,
10788 the combination of them is 3 (SP & DP). */
10793 /* Now we can handle Tag_FP_arch. */
10795 /* Values greater than 6 aren't defined, so just pick the
10796 biggest */
10798 {
10801 }
10802 /* The output uses the superset of input features
10803 (ISA version) and registers. */
10810 /* This assumes all possible supersets are also a valid
10811 options. */
10813 {
10817 }
10819 }
10825 {
10826 /* It's sometimes ok to mix different configs, so this is only
10827 a warning. */
10828 _bfd_error_handler
10830 }
10836 {
10837 _bfd_error_handler
10840 }
10848 {
10849 _bfd_error_handler
10851 ibfd);
10853 }
10854 /* Use the smallest value specified. */
10861 {
10862 _bfd_error_handler
10863 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
10865 }
10871 {
10874 {
10875 /* The existing object is compatible with anything.
10876 Use whatever requirements the new object has. */
10878 }
10882 {
10893 _bfd_error_handler
10894 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
10896 }
10897 }
10900 /* Aready done. */
10904 {
10905 _bfd_error_handler
10909 }
10912 /* Merged in target-independent code. */
10915 /* This is handled along with Tag_FP_arch. */
10919 {
10921 {
10922 _bfd_error_handler
10926 }
10927 }
10933 /* This tag is set to zero if we can use UDIV and SDIV in Thumb
10934 mode on a v7-M or v7-R CPU; to one if we can not use UDIV or
10935 SDIV at all; and to two if we can use UDIV or SDIV on a v7-A
10936 CPU. We will merge as follows: If the input attribute's value
10937 is one then the output attribute's value remains unchanged. If
10938 the input attribute's value is zero or two then if the output
10939 attribute's value is one the output value is set to the input
10940 value, otherwise the output value must be the same as the
10941 inputs. */
10943 {
10945 {
10946 _bfd_error_handler
10950 }
10951 }
10959 /* We don't output objects with Tag_MPextension_use_legacy - we
10960 move the value to Tag_MPextension_use. */
10962 {
10964 {
10965 _bfd_error_handler
10968 ibfd);
10970 }
10971 }
10979 /* This tag is set if it exists, but the value is unused (and is
10980 typically zero). We don't actually need to do anything here -
10981 the merge happens automatically when the type flags are merged
10982 below. */
10985 /* Already done in Tag_CPU_arch. */
10988 /* Keep the attribute if it matches. Throw it away otherwise.
10989 No attribute means no claim to conform. */
10996 result
10998 }
11000 /* If out_attr was copied from in_attr then it won't have a type yet. */
11003 }
11005 /* Merge Tag_compatibility attributes and any common GNU ones. */
11009 /* Check for any attributes not known on ARM. */
11013 }
11016 /* Return TRUE if the two EABI versions are incompatible. */
11018 static bfd_boolean
11020 {
11021 /* v4 and v5 are the same spec before and after it was released,
11022 so allow mixing them. */
11028 }
11030 /* Merge backend specific data from an object file to the output
11031 object file when linking. */
11033 static bfd_boolean
11036 /* Display the flags field. */
11038 static bfd_boolean
11040 {
11046 /* Print normal ELF private data. */
11050 /* Ignore init flag - it may not be set, despite the flags field
11051 containing valid data. */
11053 /* xgettext:c-format */
11057 {
11059 /* The following flag bits are GNU extensions and not part of the
11060 official ARM ELF extended ABI. Hence they are only decoded if
11061 the EABI version is not set. */
11067 else
11074 else
11103 else
11114 else
11137 eabi:
11150 }
11168 }
11170 static int
11172 {
11174 {
11179 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
11180 This allows us to distinguish between data used by Thumb instructions
11181 and non-data (which is probably code) inside Thumb regions of an
11182 executable. */
11189 }
11192 }
11200 {
11203 {
11207 }
11210 }
11212 /* Update the got entry reference counts for the section being removed. */
11214 static bfd_boolean
11219 {
11243 {
11248 bfd_boolean may_become_dynamic_p;
11249 bfd_boolean may_need_local_target_p;
11253 {
11258 }
11267 {
11273 {
11276 }
11278 {
11281 }
11301 {
11304 }
11305 /* Fall through. */
11318 /* Should the interworking branches be here also? */
11324 else
11330 }
11333 {
11343 }
11346 {
11352 {
11353 /* Everything must go for SEC. */
11356 }
11357 }
11358 }
11361 }
11363 /* Look through the relocs for a section during the first phase. */
11365 static bfd_boolean
11368 {
11376 bfd_boolean call_reloc_p;
11377 bfd_boolean may_become_dynamic_p;
11378 bfd_boolean may_need_local_target_p;
11392 /* Create dynamic sections for relocatable executables so that we can
11393 copy relocations. */
11396 {
11399 }
11408 {
11419 /* PR 9934: It is possible to have relocations that do not
11420 refer to symbols, thus it is also possible to have an
11421 object file containing relocations but no symbol table. */
11423 {
11425 r_symndx);
11427 }
11431 else
11432 {
11437 }
11445 /* Could be done earlier, if h were already available. */
11448 {
11458 /* This symbol requires a global offset table entry. */
11459 {
11463 {
11474 }
11477 {
11480 }
11481 else
11482 {
11485 /* This is a global offset table entry for a local symbol. */
11488 {
11489 bfd_size_type size;
11505 }
11508 }
11510 /* If a variable is accessed with both tls methods, two
11511 slots may be created. */
11516 /* We will already have issued an error message if there
11517 is a TLS/non-TLS mismatch, based on the symbol
11518 type. So just combine any TLS types needed. */
11523 /* If the symbol is accessed in both IE and GDESC
11524 method, we're able to relax. Turn off the GDESC flag,
11525 without messing up with any other kind of tls types
11526 that may be involved */
11531 {
11534 else
11536 }
11537 }
11538 /* Fall through. */
11543 /* Fall through. */
11548 {
11553 }
11569 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
11570 ldr __GOTT_INDEX__ offsets. */
11572 {
11575 }
11576 /* Fall through. */
11583 {
11585 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
11590 }
11592 /* Fall through. */
11602 /* Should the interworking branches be listed here? */
11603 /* If we are creating a shared library or relocatable
11604 executable, and this is a reloc against a global symbol,
11605 or a non-PC-relative reloc against a local symbol,
11606 then we may need to copy the reloc into the output. */
11612 else
11616 /* This relocation describes the C++ object vtable hierarchy.
11617 Reconstruct it for later use during GC. */
11623 /* This relocation describes which C++ vtable entries are actually
11624 used. Record for later use during GC. */
11631 }
11634 {
11636 /* We may need a .plt entry if the function this reloc
11637 refers to is in a different object, regardless of the
11638 symbol's type. We can't tell for sure yet, because
11639 something later might force the symbol local. */
11642 /* If this reloc is in a read-only section, we might
11643 need a copy reloc. We can't check reliably at this
11644 stage whether the section is read-only, as input
11645 sections have not yet been mapped to output sections.
11646 Tentatively set the flag for now, and correct in
11647 adjust_dynamic_symbol. */
11649 }
11652 {
11653 /* If the symbol is a function that doesn't bind locally,
11654 this relocation will need a PLT entry. */
11657 /* It's too early to use htab->use_blx here, so we have to
11658 record possible blx references separately from
11659 relocs that definitely need a thumb stub. */
11667 }
11670 {
11673 /* Create a reloc section in dynobj. */
11675 {
11676 sreloc = _bfd_elf_make_dynamic_reloc_section
11682 /* BPABI objects never have dynamic relocations mapped. */
11684 {
11685 flagword flags;
11690 }
11691 }
11693 /* If this is a global symbol, count the number of
11694 relocations we need for this symbol. */
11697 else
11698 {
11699 /* Track dynamic relocs needed for local syms too.
11700 We really need local syms available to do this
11701 easily. Oh well. */
11717 }
11721 {
11732 }
11737 }
11738 }
11741 }
11743 /* Unwinding tables are not referenced directly. This pass marks them as
11744 required if the corresponding code section is marked. */
11746 static bfd_boolean
11748 elf_gc_mark_hook_fn gc_mark_hook)
11749 {
11752 bfd_boolean again;
11754 /* Marking EH data may cause additional code sections to be marked,
11755 requiring multiple passes. */
11758 {
11761 {
11769 {
11778 {
11782 }
11783 }
11784 }
11785 }
11788 }
11790 /* Treat mapping symbols as special target symbols. */
11792 static bfd_boolean
11794 {
11796 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
11797 }
11799 /* This is a copy of elf_find_function() from elf.c except that
11800 ARM mapping symbols are ignored when looking for function names
11801 and STT_ARM_TFUNC is considered to a function type. */
11803 static bfd_boolean
11807 bfd_vma offset,
11810 {
11817 {
11823 {
11832 /* Skip mapping symbols. */
11835 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
11837 /* Fall through. */
11841 {
11844 }
11846 }
11847 }
11858 }
11861 /* Find the nearest line to a particular section and offset, for error
11862 reporting. This code is a duplicate of the code in elf.c, except
11863 that it uses arm_elf_find_function. */
11865 static bfd_boolean
11869 bfd_vma offset,
11873 {
11876 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
11882 {
11886 functionname_ptr);
11889 }
11909 }
11911 static bfd_boolean
11916 {
11917 bfd_boolean found;
11922 }
11924 /* Adjust a symbol defined by a dynamic object and referenced by a
11925 regular object. The current definition is in some section of the
11926 dynamic object, but we're not including those sections. We have to
11927 change the definition to something the rest of the link can
11928 understand. */
11930 static bfd_boolean
11933 {
11945 /* Make sure we know what is going on here. */
11955 /* If this is a function, put it in the procedure linkage table. We
11956 will fill in the contents of the procedure linkage table later,
11957 when we know the address of the .got section. */
11960 {
11965 {
11966 /* This case can occur if we saw a PLT32 reloc in an input
11967 file, but the symbol was never referred to by a dynamic
11968 object, or if all references were garbage collected. In
11969 such a case, we don't actually need to build a procedure
11970 linkage table, and we can just do a PC24 reloc instead. */
11975 }
11978 }
11979 else
11980 {
11981 /* It's possible that we incorrectly decided a .plt reloc was
11982 needed for an R_ARM_PC24 or similar reloc to a non-function sym
11983 in check_relocs. We can't decide accurately between function
11984 and non-function syms in check-relocs; Objects loaded later in
11985 the link may change h->type. So fix it now. */
11989 }
11991 /* If this is a weak symbol, and there is a real definition, the
11992 processor independent code will have arranged for us to see the
11993 real definition first, and we can just use the same value. */
11995 {
12001 }
12003 /* If there are no non-GOT references, we do not need a copy
12004 relocation. */
12008 /* This is a reference to a symbol defined by a dynamic object which
12009 is not a function. */
12011 /* If we are creating a shared library, we must presume that the
12012 only references to the symbol are via the global offset table.
12013 For such cases we need not do anything here; the relocations will
12014 be handled correctly by relocate_section. Relocatable executables
12015 can reference data in shared objects directly, so we don't need to
12016 do anything here. */
12021 {
12025 }
12027 /* We must allocate the symbol in our .dynbss section, which will
12028 become part of the .bss section of the executable. There will be
12029 an entry for this symbol in the .dynsym section. The dynamic
12030 object will contain position independent code, so all references
12031 from the dynamic object to this symbol will go through the global
12032 offset table. The dynamic linker will use the .dynsym entry to
12033 determine the address it must put in the global offset table, so
12034 both the dynamic object and the regular object will refer to the
12035 same memory location for the variable. */
12039 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
12040 copy the initial value out of the dynamic object and into the
12041 runtime process image. We need to remember the offset into the
12042 .rel(a).bss section we are going to use. */
12044 {
12050 }
12053 }
12055 /* Allocate space in .plt, .got and associated reloc sections for
12056 dynamic relocs. */
12058 static bfd_boolean
12060 {
12065 bfd_signed_vma thumb_refs;
12071 /* When warning symbols are created, they **replace** the "real"
12072 entry in the hash table, thus we never get to see the real
12073 symbol in a hash traversal. So look at it now. */
12085 {
12086 /* Make sure this symbol is output as a dynamic symbol.
12087 Undefined weak syms won't yet be marked as dynamic. */
12090 {
12093 }
12097 {
12100 /* If this is the first .plt entry, make room for the special
12101 first entry. */
12107 /* If we will insert a Thumb trampoline before this PLT, leave room
12108 for it. */
12114 {
12117 }
12119 /* If this symbol is not defined in a regular file, and we are
12120 not generating a shared library, then set the symbol to this
12121 location in the .plt. This is required to make function
12122 pointers compare as equal between the normal executable and
12123 the shared library. */
12126 {
12130 /* Make sure the function is not marked as Thumb, in case
12131 it is the target of an ABS32 relocation, which will
12132 point to the PLT entry. */
12135 }
12137 /* Make room for this entry. */
12141 {
12142 /* We also need to make an entry in the .got.plt section, which
12143 will be placed in the .got section by the linker script. */
12147 }
12149 /* We also need to make an entry in the .rel(a).plt section. */
12153 /* VxWorks executables have a second set of relocations for
12154 each PLT entry. They go in a separate relocation section,
12155 which is processed by the kernel loader. */
12157 {
12158 /* There is a relocation for the initial PLT entry:
12159 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
12163 /* There are two extra relocations for each subsequent
12164 PLT entry: an R_ARM_32 relocation for the GOT entry,
12165 and an R_ARM_32 relocation for the PLT entry. */
12167 }
12168 }
12169 else
12170 {
12173 }
12174 }
12175 else
12176 {
12179 }
12185 {
12187 bfd_boolean dyn;
12191 /* Make sure this symbol is output as a dynamic symbol.
12192 Undefined weak syms won't yet be marked as dynamic. */
12195 {
12198 }
12201 {
12209 /* Non-TLS symbols need one GOT slot. */
12211 else
12212 {
12214 {
12215 /* R_ARM_TLS_DESC needs 2 GOT slots. */
12216 eh->tlsdesc_got
12221 /* plt_got_offset needs to know there's a TLS_DESC
12222 reloc in the middle of .got.plt. */
12224 }
12227 {
12228 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
12229 the symbol is both GD and GDESC, got.offset may
12230 have been overwritten. */
12233 }
12236 /* R_ARM_TLS_IE32 needs one GOT slot. */
12238 }
12252 {
12260 {
12262 /* GDESC needs a trampoline to jump to. */
12264 }
12266 /* Only GD needs it. GDESC just emits one relocation per
12267 2 entries. */
12270 }
12272 {
12274 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
12276 }
12278 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
12280 }
12281 }
12282 else
12285 /* Allocate stubs for exported Thumb functions on v4t. */
12290 {
12297 /* Create a new symbol to regist the real location of the function. */
12310 /* Point the symbol at the stub. */
12314 }
12319 /* In the shared -Bsymbolic case, discard space allocated for
12320 dynamic pc-relative relocs against symbols which turn out to be
12321 defined in regular objects. For the normal shared case, discard
12322 space for pc-relative relocs that have become local due to symbol
12323 visibility changes. */
12326 {
12327 /* The only relocs that use pc_count are R_ARM_REL32 and
12328 R_ARM_REL32_NOI, which will appear on something like
12329 ".long foo - .". We want calls to protected symbols to resolve
12330 directly to the function rather than going via the plt. If people
12331 want function pointer comparisons to work as expected then they
12332 should avoid writing assembly like ".long foo - .". */
12334 {
12338 {
12343 else
12345 }
12346 }
12349 {
12353 {
12356 else
12358 }
12359 }
12361 /* Also discard relocs on undefined weak syms with non-default
12362 visibility. */
12365 {
12369 /* Make sure undefined weak symbols are output as a dynamic
12370 symbol in PIEs. */
12373 {
12376 }
12377 }
12381 {
12382 /* Output absolute symbols so that we can create relocations
12383 against them. For normal symbols we output a relocation
12384 against the section that contains them. */
12387 }
12389 }
12390 else
12391 {
12392 /* For the non-shared case, discard space for relocs against
12393 symbols which turn out to need copy relocs or are not
12394 dynamic. */
12402 {
12403 /* Make sure this symbol is output as a dynamic symbol.
12404 Undefined weak syms won't yet be marked as dynamic. */
12407 {
12410 }
12412 /* If that succeeded, we know we'll be keeping all the
12413 relocs. */
12416 }
12420 keep: ;
12421 }
12423 /* Finally, allocate space. */
12425 {
12428 }
12431 }
12433 /* Find any dynamic relocs that apply to read-only sections. */
12435 static bfd_boolean
12437 {
12446 {
12450 {
12455 /* Not an error, just cut short the traversal. */
12457 }
12458 }
12460 }
12462 void
12465 {
12473 }
12475 /* Set the sizes of the dynamic sections. */
12477 static bfd_boolean
12480 {
12483 bfd_boolean plt;
12484 bfd_boolean relocs;
12497 {
12498 /* Set the contents of the .interp section to the interpreter. */
12500 {
12505 }
12506 }
12508 /* Set up .got offsets for local syms, and space for local dynamic
12509 relocs. */
12511 {
12516 bfd_size_type locsymcount;
12525 {
12530 {
12533 {
12534 /* Input section has been discarded, either because
12535 it is a copy of a linkonce section or due to
12536 linker script /DISCARD/, so we'll be discarding
12537 the relocs too. */
12538 }
12542 {
12543 /* Relocations in vxworks .tls_vars sections are
12544 handled specially by the loader. */
12545 }
12547 {
12552 }
12553 }
12554 }
12569 {
12572 {
12575 /* TLS_GD relocs need an 8-byte structure in the GOT. */
12578 {
12583 /* plt_got_offset needs to know there's a TLS_DESC
12584 reloc in the middle of .got.plt. */
12586 }
12591 {
12592 /* If the symbol is both GD and GDESC, *local_got
12593 may have been overwritten. */
12596 }
12603 {
12606 }
12607 }
12608 else
12610 }
12611 }
12614 {
12615 /* Allocate two GOT entries and one dynamic relocation (if necessary)
12616 for R_ARM_TLS_LDM32 relocations. */
12621 }
12622 else
12625 /* Allocate global sym .plt and .got entries, and space for global
12626 sym dynamic relocs. */
12629 /* Here we rummage through the found bfds to collect glue information. */
12631 {
12635 /* Initialise mapping tables for code/data. */
12640 /* xgettext:c-format */
12643 }
12645 /* Allocate space for the glue sections now that we've sized them. */
12648 /* For every jump slot reserved in the sgotplt, reloc_count is
12649 incremented. However, when we reserve space for TLS descriptors,
12650 it's not incremented, so in order to compute the space reserved
12651 for them, it suffices to multiply the reloc count by the jump
12652 slot size. */
12657 {
12664 /* If we're not using lazy TLS relocations, don't generate the
12665 PLT and GOT entries they require. */
12667 {
12673 }
12674 }
12676 /* The check_relocs and adjust_dynamic_symbol entry points have
12677 determined the sizes of the various dynamic sections. Allocate
12678 memory for them. */
12682 {
12688 /* It's OK to base decisions on the section name, because none
12689 of the dynobj section names depend upon the input files. */
12693 {
12694 /* Remember whether there is a PLT. */
12696 }
12698 {
12700 {
12701 /* Remember whether there are any reloc sections other
12702 than .rel(a).plt and .rela.plt.unloaded. */
12706 /* We use the reloc_count field as a counter if we need
12707 to copy relocs into the output file. */
12709 }
12710 }
12713 {
12714 /* It's not one of our sections, so don't allocate space. */
12716 }
12719 {
12720 /* If we don't need this section, strip it from the
12721 output file. This is mostly to handle .rel(a).bss and
12722 .rel(a).plt. We must create both sections in
12723 create_dynamic_sections, because they must be created
12724 before the linker maps input sections to output
12725 sections. The linker does that before
12726 adjust_dynamic_symbol is called, and it is that
12727 function which decides whether anything needs to go
12728 into these sections. */
12731 }
12736 /* Allocate memory for the section contents. */
12740 }
12743 {
12744 /* Add some entries to the .dynamic section. We fill in the
12745 values later, in elf32_arm_finish_dynamic_sections, but we
12746 must add the entries now so that we get the correct size for
12747 the .dynamic section. The DT_DEBUG entry is filled in by the
12748 dynamic linker and used by the debugger. */
12749 #define add_dynamic_entry(TAG, VAL) \
12750 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
12753 {
12756 }
12759 {
12771 }
12774 {
12776 {
12781 }
12782 else
12783 {
12788 }
12789 }
12791 /* If any dynamic relocs apply to a read-only section,
12792 then we need a DT_TEXTREL entry. */
12795 info);
12798 {
12801 }
12805 }
12806 #undef add_dynamic_entry
12809 }
12811 /* Size sections even though they're not dynamic. We use it to setup
12812 _TLS_MODULE_BASE_, if needed. */
12814 static bfd_boolean
12817 {
12826 {
12829 tlsbase = elf_link_hash_lookup
12833 {
12849 }
12850 }
12852 }
12854 /* Finish up dynamic symbol handling. We set the contents of various
12855 dynamic sections here. */
12857 static bfd_boolean
12862 {
12873 {
12877 bfd_vma plt_index;
12878 Elf_Internal_Rela rel;
12880 /* This symbol has an entry in the procedure linkage table. Set
12881 it up. */
12889 /* Fill in the entry in the procedure linkage table. */
12891 {
12899 /* Fill in the entry in the .rel.plt section. */
12905 /* Get the index in the procedure linkage table which
12906 corresponds to this symbol. This is the index of this symbol
12907 in all the symbols for which we are making plt entries. The
12908 first entry in the procedure linkage table is reserved. */
12911 }
12912 else
12913 {
12915 bfd_vma got_displacement;
12922 /* Get the offset into the .got.plt table of the entry that
12923 corresponds to this function. */
12926 /* Get the index in the procedure linkage table which
12927 corresponds to this symbol. This is the index of this symbol
12928 in all the symbols for which we are making plt entries. The
12929 first three entries in .got.plt are reserved; after that
12930 symbols appear in the same order as in .plt. */
12933 /* Calculate the address of the GOT entry. */
12938 /* ...and the address of the PLT entry. */
12945 {
12947 bfd_vma val;
12950 {
12958 else
12960 }
12961 }
12963 {
12965 bfd_vma val;
12968 {
12978 else
12980 }
12985 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
12986 referencing the GOT for this PLT entry. */
12993 /* Create the R_ARM_ABS32 relocation referencing the
12994 beginning of the PLT for this GOT entry. */
12999 }
13000 else
13001 {
13002 bfd_signed_vma thumb_refs;
13003 /* Calculate the displacement between the PLT slot and the
13004 entry in the GOT. The eight-byte offset accounts for the
13005 value produced by adding to pc in the first instruction
13006 of the PLT stub. */
13016 {
13021 }
13035 #ifdef FOUR_WORD_PLT
13037 #endif
13038 }
13040 /* Fill in the entry in the global offset table. */
13046 /* Fill in the entry in the .rel(a).plt section. */
13050 }
13056 {
13057 /* Mark the symbol as undefined, rather than as defined in
13058 the .plt section. Leave the value alone. */
13060 /* If the symbol is weak, we do need to clear the value.
13061 Otherwise, the PLT entry would provide a definition for
13062 the symbol even if the symbol wasn't defined anywhere,
13063 and so the symbol would never be NULL. */
13066 }
13067 }
13070 {
13072 Elf_Internal_Rela rel;
13074 /* This symbol needs a copy reloc. Set it up. */
13088 }
13090 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13091 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13092 to the ".got" section. */
13098 }
13100 static void
13104 {
13108 {
13111 /* Emit mov pc,rx if bx is not permitted. */
13115 }
13116 }
13118 /* Finish up the dynamic sections. */
13120 static bfd_boolean
13122 {
13139 {
13150 {
13151 Elf_Internal_Dyn dyn;
13158 {
13191 get_vma:
13196 else
13197 /* In the BPABI, tags in the PT_DYNAMIC section point
13198 at the file offset, not the memory address, for the
13199 convenience of the post linker. */
13204 get_vma_if_bpabi:
13219 {
13220 /* My reading of the SVR4 ABI indicates that the
13221 procedure linkage table relocs (DT_JMPREL) should be
13222 included in the overall relocs (DT_REL). This is
13223 what Solaris does. However, UnixWare can not handle
13224 that case. Therefore, we override the DT_RELSZ entry
13225 here to make it not include the JMPREL relocs. Since
13226 the linker script arranges for .rel(a).plt to follow all
13227 other relocation sections, we don't have to worry
13228 about changing the DT_REL entry. */
13234 }
13235 /* Fall through. */
13239 /* In the BPABI, the DT_REL tag must point at the file
13240 offset, not the VMA, of the first relocation
13241 section. So, we use code similar to that in
13242 elflink.c, but do not check for SHF_ALLOC on the
13243 relcoation section, since relocations sections are
13244 never allocated under the BPABI. The comments above
13245 about Unixware notwithstanding, we include all of the
13246 relocations here. */
13248 {
13254 {
13255 Elf_Internal_Shdr *hdr
13258 {
13265 }
13266 }
13268 }
13285 /* Set the bottom bit of DT_INIT/FINI if the
13286 corresponding function is Thumb. */
13292 get_sym:
13293 /* If it wasn't set by elf_bfd_final_link
13294 then there is nothing to adjust. */
13296 {
13303 {
13306 }
13307 }
13309 }
13310 }
13312 /* Fill in the first entry in the procedure linkage table. */
13314 {
13318 /* Calculate the addresses of the GOT and PLT. */
13323 {
13324 /* The VxWorks GOT is relocated by the dynamic linker.
13325 Therefore, we must emit relocations rather than simply
13326 computing the values now. */
13327 Elf_Internal_Rela rel;
13338 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
13344 }
13345 else
13346 {
13359 #ifdef FOUR_WORD_PLT
13360 /* The displacement value goes in the otherwise-unused
13361 last word of the second entry. */
13363 #else
13365 #endif
13366 }
13367 }
13369 /* UnixWare sets the entsize of .plt to 4, although that doesn't
13370 really seem like the right value. */
13375 {
13376 bfd_vma got_address
13380 bfd_vma plt_address
13396 }
13399 {
13403 #ifdef FOUR_WORD_PLT
13406 #endif
13407 }
13410 {
13411 /* Correct the .rel(a).plt.unloaded relocations. They will have
13412 incorrect symbol indexes. */
13421 {
13422 Elf_Internal_Rela rel;
13433 }
13434 }
13435 }
13437 /* Fill in the first three entries in the global offset table. */
13439 {
13441 {
13444 else
13450 }
13453 }
13456 }
13458 static void
13459 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
13460 {
13468 else
13473 {
13477 }
13478 }
13480 static enum elf_reloc_type_class
13482 {
13484 {
13493 }
13494 }
13496 /* Set the right machine number for an Arm ELF file. */
13498 static bfd_boolean
13500 {
13505 }
13507 static void
13509 {
13511 }
13513 /* Return TRUE if this is an unwinding table entry. */
13515 static bfd_boolean
13517 {
13520 }
13523 /* Set the type and flags for an ARM section. We do this by
13524 the section name, which is a hack, but ought to work. */
13526 static bfd_boolean
13528 {
13534 {
13537 }
13539 }
13541 /* Handle an ARM specific section when reading an object file. This is
13542 called when bfd_section_from_shdr finds a section with an unknown
13543 type. */
13545 static bfd_boolean
13550 {
13551 /* There ought to be a place to keep ELF backend specific flags, but
13552 at the moment there isn't one. We just keep track of the
13553 sections by their name, instead. Fortunately, the ABI gives
13554 names for all the ARM specific sections, so we will probably get
13555 away with this. */
13557 {
13565 }
13571 }
13575 {
13578 else
13580 }
13583 {
13592 enum map_symbol_type
13593 {
13594 ARM_MAP_ARM,
13595 ARM_MAP_THUMB,
13596 ARM_MAP_DATA
13597 };
13600 /* Output a single mapping symbol. */
13602 static bfd_boolean
13605 bfd_vma offset)
13606 {
13608 Elf_Internal_Sym sym;
13619 }
13622 /* Output mapping symbols for PLT entries associated with H. */
13624 static bfd_boolean
13626 {
13630 bfd_vma addr;
13636 /* When warning symbols are created, they **replace** the "real"
13637 entry in the hash table, thus we never get to see the real
13638 symbol in a hash traversal. So look at it now. */
13651 {
13656 }
13658 {
13667 }
13668 else
13669 {
13670 bfd_signed_vma thumb_refs;
13677 {
13680 }
13681 #ifdef FOUR_WORD_PLT
13686 #else
13687 /* A three-word PLT with no Thumb thunk contains only Arm code,
13688 so only need to output a mapping symbol for the first PLT entry and
13689 entries with thumb thunks. */
13691 {
13694 }
13695 #endif
13696 }
13699 }
13701 /* Output a single local symbol for a generated stub. */
13703 static bfd_boolean
13706 {
13707 Elf_Internal_Sym sym;
13717 }
13719 static bfd_boolean
13722 {
13725 bfd_vma addr;
13734 /* Massage our args to the form they really have. */
13740 /* Ensure this stub is attached to the current section being
13741 processed. */
13750 {
13764 }
13769 {
13771 {
13788 }
13791 {
13795 }
13798 {
13815 }
13816 }
13819 }
13821 /* Output mapping symbols for linker generated sections,
13822 and for those data-only sections that do not have a
13823 $d. */
13825 static bfd_boolean
13830 Elf_Internal_Sym *,
13831 asection *,
13833 {
13834 output_arch_syminfo osi;
13836 bfd_vma offset;
13837 bfd_size_type size;
13850 /* Add a $d mapping symbol to data-only sections that
13851 don't have any mapping symbol. This may result in (harmless) redundant
13852 mapping symbols. */
13856 {
13861 {
13866 == SEC_HAS_CONTENTS
13870 {
13875 }
13876 }
13877 }
13879 /* ARM->Thumb glue. */
13881 {
13883 ARM2THUMB_GLUE_SECTION_NAME);
13892 else
13896 {
13899 }
13900 }
13902 /* Thumb->ARM glue. */
13904 {
13906 THUMB2ARM_GLUE_SECTION_NAME);
13913 {
13916 }
13917 }
13919 /* ARMv4 BX veneers. */
13921 {
13923 ARM_BX_GLUE_SECTION_NAME);
13929 }
13931 /* Long calls stubs. */
13933 {
13939 {
13940 /* Ignore non-stub sections. */
13950 }
13951 }
13953 /* Finally, output mapping symbols for the PLT. */
13960 /* Output mapping symbols for the plt header. SymbianOS does not have a
13961 plt header. */
13963 {
13964 /* VxWorks shared libraries have no PLT header. */
13966 {
13971 }
13972 }
13974 {
13977 #ifndef FOUR_WORD_PLT
13980 #endif
13981 }
13984 {
13985 /* Mapping symbols for the lazy tls trampoline. */
13992 }
13994 {
13995 /* Mapping symbols for the tls trampoline. */
13998 #ifdef FOUR_WORD_PLT
14002 #endif
14003 }
14007 }
14009 /* Allocate target specific section data. */
14011 static bfd_boolean
14013 {
14015 {
14023 }
14026 }
14029 /* Used to order a list of mapping symbols by address. */
14031 static int
14033 {
14042 /* Ensure results do not depend on the host qsort for objects with
14043 multiple mapping symbols at the same address by sorting on type
14044 after vma. */
14048 else
14050 }
14052 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
14054 static unsigned long
14056 {
14058 }
14060 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
14061 relocations. */
14063 static void
14065 {
14069 /* High bit of first word is supposed to be zero. */
14073 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
14074 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
14080 }
14082 /* Data for make_branch_to_a8_stub(). */
14087 };
14090 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
14091 places for a particular section. */
14093 static bfd_boolean
14096 {
14102 bfd_signed_vma branch_offset;
14131 /* We attempt to avoid this condition by setting stubs_always_after_branch
14132 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
14133 This check is just to be on the safe side... */
14135 {
14139 }
14142 {
14153 {
14158 jump24:
14160 {
14161 /* There's not much we can do apart from complain if this
14162 happens. */
14166 }
14168 /* i1 = not(j1 eor s), so:
14169 not i1 = j1 eor s
14170 j1 = (not i1) eor s. */
14182 }
14188 }
14194 }
14196 /* Do code byteswapping. Return FALSE afterwards so that the section is
14197 written out as normal. */
14199 static bfd_boolean
14204 {
14210 bfd_vma ptr;
14211 bfd_vma end;
14213 bfd_byte tmp;
14219 /* If this section has not been allocated an _arm_elf_section_data
14220 structure then we cannot record anything. */
14230 {
14235 {
14239 {
14241 {
14242 bfd_vma branch_to_veneer;
14243 /* Original condition code of instruction, plus bit mask for
14244 ARM B instruction. */
14248 /* The instruction is before the label. */
14251 /* Above offset included in -4 below. */
14265 }
14269 {
14270 bfd_vma branch_from_veneer;
14273 /* Take size of veneer into account. */
14282 /* Original instruction. */
14289 /* Branch back to insn after original insn. */
14295 }
14300 }
14301 }
14302 }
14305 {
14306 arm_unwind_table_edit *edit_node
14308 /* Now, sec->size is the size of the section we will write. The original
14309 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
14310 markers) was sec->rawsize. (This isn't the case if we perform no
14311 edits, then rawsize will be zero and we should use size). */
14318 {
14320 {
14324 {
14327 out_index++;
14328 in_index++;
14329 }
14333 {
14335 {
14337 in_index++;
14342 {
14350 /* Note: this is meant to be equivalent to an
14351 R_ARM_PREL31 relocation. These synthetic
14352 EXIDX_CANTUNWIND markers are not relocated by the
14353 usual BFD method. */
14357 /* First address we can't unwind. */
14361 /* Code for EXIDX_CANTUNWIND. */
14365 out_index++;
14367 }
14369 }
14372 }
14373 }
14374 else
14375 {
14376 /* No more edits, copy remaining entries verbatim. */
14379 out_index++;
14380 in_index++;
14381 }
14382 }
14386 edited_contents,
14390 }
14392 /* Fix code to point to Cortex-A8 erratum stubs. */
14394 {
14402 }
14408 {
14413 {
14416 else
14420 {
14422 /* Byte swap code words. */
14424 {
14432 }
14436 /* Byte swap code halfwords. */
14438 {
14443 }
14447 /* Leave data alone. */
14449 }
14451 }
14452 }
14460 }
14462 /* Display STT_ARM_TFUNC symbols as functions. */
14464 static void
14467 {
14472 }
14475 /* Mangle thumb function symbols as we read them in. */
14477 static bfd_boolean
14482 {
14486 /* New EABI objects mark thumb function symbols by setting the low bit of
14487 the address. Turn these into STT_ARM_TFUNC. */
14490 {
14493 }
14495 }
14498 /* Mangle thumb function symbols as we write them out. */
14500 static void
14505 {
14506 Elf_Internal_Sym newsym;
14508 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
14509 of the address set, as per the new EABI. We do this unconditionally
14510 because objcopy does not set the elf header flags until after
14511 it writes out the symbol table. */
14513 {
14517 {
14518 /* Do this only for defined symbols. At link type, the static
14519 linker will simulate the work of dynamic linker of resolving
14520 symbols and will carry over the thumbness of found symbols to
14521 the output symbol table. It's not clear how it happens, but
14522 the thumbness of undefined symbols can well be different at
14523 runtime, and writing '1' for them will be confusing for users
14524 and possibly for dynamic linker itself.
14525 */
14527 }
14530 }
14532 }
14534 /* Add the PT_ARM_EXIDX program header. */
14536 static bfd_boolean
14539 {
14545 {
14546 /* If there is already a PT_ARM_EXIDX header, then we do not
14547 want to add another one. This situation arises when running
14548 "strip"; the input binary already has the header. */
14553 {
14564 }
14565 }
14568 }
14570 /* We may add a PT_ARM_EXIDX program header. */
14572 static int
14575 {
14581 else
14583 }
14585 /* We have two function types: STT_FUNC and STT_ARM_TFUNC. */
14587 static bfd_boolean
14589 {
14591 }
14593 /* We use this to override swap_symbol_in and swap_symbol_out. */
14595 {
14608 bfd_elf32_write_out_phdrs,
14609 bfd_elf32_write_shdrs_and_ehdr,
14610 bfd_elf32_checksum_contents,
14611 bfd_elf32_write_relocs,
14612 elf32_arm_swap_symbol_in,
14613 elf32_arm_swap_symbol_out,
14614 bfd_elf32_slurp_reloc_table,
14615 bfd_elf32_slurp_symbol_table,
14616 bfd_elf32_swap_dyn_in,
14617 bfd_elf32_swap_dyn_out,
14618 bfd_elf32_swap_reloc_in,
14619 bfd_elf32_swap_reloc_out,
14620 bfd_elf32_swap_reloca_in,
14621 bfd_elf32_swap_reloca_out
14622 };
14624 #define ELF_ARCH bfd_arch_arm
14625 #define ELF_TARGET_ID ARM_ELF_DATA
14626 #define ELF_MACHINE_CODE EM_ARM
14627 #ifdef __QNXTARGET__
14628 #define ELF_MAXPAGESIZE 0x1000
14629 #else
14630 #define ELF_MAXPAGESIZE 0x8000
14631 #endif
14632 #define ELF_MINPAGESIZE 0x1000
14633 #define ELF_COMMONPAGESIZE 0x1000
14635 #define bfd_elf32_mkobject elf32_arm_mkobject
14637 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
14638 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
14639 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
14640 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
14641 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
14642 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
14643 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
14644 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
14645 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
14646 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
14647 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
14648 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
14649 #define bfd_elf32_bfd_final_link elf32_arm_final_link
14651 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
14652 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
14653 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
14654 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
14655 #define elf_backend_check_relocs elf32_arm_check_relocs
14656 #define elf_backend_relocate_section elf32_arm_relocate_section
14657 #define elf_backend_write_section elf32_arm_write_section
14658 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
14659 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
14660 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
14661 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
14662 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
14663 #define elf_backend_always_size_sections elf32_arm_always_size_sections
14664 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
14665 #define elf_backend_post_process_headers elf32_arm_post_process_headers
14666 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
14667 #define elf_backend_object_p elf32_arm_object_p
14668 #define elf_backend_section_flags elf32_arm_section_flags
14669 #define elf_backend_fake_sections elf32_arm_fake_sections
14670 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
14671 #define elf_backend_final_write_processing elf32_arm_final_write_processing
14672 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
14673 #define elf_backend_symbol_processing elf32_arm_symbol_processing
14674 #define elf_backend_size_info elf32_arm_size_info
14675 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
14676 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
14677 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
14678 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
14679 #define elf_backend_is_function_type elf32_arm_is_function_type
14681 #define elf_backend_can_refcount 1
14682 #define elf_backend_can_gc_sections 1
14683 #define elf_backend_plt_readonly 1
14684 #define elf_backend_want_got_plt 1
14685 #define elf_backend_want_plt_sym 0
14686 #define elf_backend_may_use_rel_p 1
14687 #define elf_backend_may_use_rela_p 0
14688 #define elf_backend_default_use_rela_p 0
14690 #define elf_backend_got_header_size 12
14692 #undef elf_backend_obj_attrs_vendor
14694 #undef elf_backend_obj_attrs_section
14696 #undef elf_backend_obj_attrs_arg_type
14697 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
14698 #undef elf_backend_obj_attrs_section_type
14699 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
14700 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
14701 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
14705 /* VxWorks Targets. */
14707 #undef TARGET_LITTLE_SYM
14708 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
14709 #undef TARGET_LITTLE_NAME
14711 #undef TARGET_BIG_SYM
14712 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
14713 #undef TARGET_BIG_NAME
14716 /* Like elf32_arm_link_hash_table_create -- but overrides
14717 appropriately for VxWorks. */
14721 {
14726 {
14731 }
14733 }
14735 static void
14737 {
14740 }
14742 #undef elf32_bed
14743 #define elf32_bed elf32_arm_vxworks_bed
14745 #undef bfd_elf32_bfd_link_hash_table_create
14746 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
14747 #undef elf_backend_add_symbol_hook
14748 #define elf_backend_add_symbol_hook elf_vxworks_add_symbol_hook
14749 #undef elf_backend_final_write_processing
14750 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
14751 #undef elf_backend_emit_relocs
14752 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
14754 #undef elf_backend_may_use_rel_p
14755 #define elf_backend_may_use_rel_p 0
14756 #undef elf_backend_may_use_rela_p
14757 #define elf_backend_may_use_rela_p 1
14758 #undef elf_backend_default_use_rela_p
14759 #define elf_backend_default_use_rela_p 1
14760 #undef elf_backend_want_plt_sym
14761 #define elf_backend_want_plt_sym 1
14762 #undef ELF_MAXPAGESIZE
14763 #define ELF_MAXPAGESIZE 0x1000
14768 /* Merge backend specific data from an object file to the output
14769 object file when linking. */
14771 static bfd_boolean
14773 {
14774 flagword out_flags;
14775 flagword in_flags;
14779 /* Check if we have the same endianess. */
14789 /* The input BFD must have had its flags initialised. */
14790 /* The following seems bogus to me -- The flags are initialized in
14791 the assembler but I don't think an elf_flags_init field is
14792 written into the object. */
14793 /* BFD_ASSERT (elf_flags_init (ibfd)); */
14798 /* In theory there is no reason why we couldn't handle this. However
14799 in practice it isn't even close to working and there is no real
14800 reason to want it. */
14804 {
14806 ibfd);
14808 }
14811 {
14812 /* If the input is the default architecture and had the default
14813 flags then do not bother setting the flags for the output
14814 architecture, instead allow future merges to do this. If no
14815 future merges ever set these flags then they will retain their
14816 uninitialised values, which surprise surprise, correspond
14817 to the default values. */
14830 }
14832 /* Determine what should happen if the input ARM architecture
14833 does not match the output ARM architecture. */
14837 /* Identical flags must be compatible. */
14841 /* Check to see if the input BFD actually contains any sections. If
14842 not, its flags may not have been initialised either, but it
14843 cannot actually cause any incompatiblity. Do not short-circuit
14844 dynamic objects; their section list may be emptied by
14845 elf_link_add_object_symbols.
14847 Also check to see if there are no code sections in the input.
14848 In this case there is no need to check for code specific flags.
14849 XXX - do we need to worry about floating-point format compatability
14850 in data sections ? */
14852 {
14857 {
14858 /* Ignore synthetic glue sections. */
14861 {
14869 }
14870 }
14874 }
14876 /* Complain about various flag mismatches. */
14879 {
14880 _bfd_error_handler
14886 }
14888 /* Not sure what needs to be checked for EABI versions >= 1. */
14889 /* VxWorks libraries do not use these flags. */
14893 {
14895 {
14896 _bfd_error_handler
14902 }
14905 {
14907 _bfd_error_handler
14908 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
14910 else
14911 _bfd_error_handler
14912 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
14916 }
14919 {
14921 _bfd_error_handler
14924 else
14925 _bfd_error_handler
14930 }
14933 {
14935 _bfd_error_handler
14938 else
14939 _bfd_error_handler
14944 }
14946 #ifdef EF_ARM_SOFT_FLOAT
14948 {
14949 /* We can allow interworking between code that is VFP format
14950 layout, and uses either soft float or integer regs for
14951 passing floating point arguments and results. We already
14952 know that the APCS_FLOAT flags match; similarly for VFP
14953 flags. */
14956 {
14958 _bfd_error_handler
14961 else
14962 _bfd_error_handler
14967 }
14968 }
14969 #endif
14971 /* Interworking mismatch is only a warning. */
14973 {
14975 {
14976 _bfd_error_handler
14979 }
14980 else
14981 {
14982 _bfd_error_handler
14985 }
14986 }
14987 }
14990 }
14993 /* Symbian OS Targets. */
14995 #undef TARGET_LITTLE_SYM
14996 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
14997 #undef TARGET_LITTLE_NAME
14999 #undef TARGET_BIG_SYM
15000 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
15001 #undef TARGET_BIG_NAME
15004 /* Like elf32_arm_link_hash_table_create -- but overrides
15005 appropriately for Symbian OS. */
15009 {
15014 {
15017 /* There is no PLT header for Symbian OS. */
15019 /* The PLT entries are each one instruction and one word. */
15022 /* Symbian uses armv5t or above, so use_blx is always true. */
15025 }
15027 }
15029 static const struct bfd_elf_special_section
15030 elf32_arm_symbian_special_sections[] =
15031 {
15032 /* In a BPABI executable, the dynamic linking sections do not go in
15033 the loadable read-only segment. The post-linker may wish to
15034 refer to these sections, but they are not part of the final
15035 program image. */
15041 /* These sections do not need to be writable as the SymbianOS
15042 postlinker will arrange things so that no dynamic relocation is
15043 required. */
15048 };
15050 static void
15053 {
15054 /* BPABI objects are never loaded directly by an OS kernel; they are
15055 processed by a postlinker first, into an OS-specific format. If
15056 the D_PAGED bit is set on the file, BFD will align segments on
15057 page boundaries, so that an OS can directly map the file. With
15058 BPABI objects, that just results in wasted space. In addition,
15059 because we clear the D_PAGED bit, map_sections_to_segments will
15060 recognize that the program headers should not be mapped into any
15061 loadable segment. */
15064 }
15066 static bfd_boolean
15069 {
15073 /* BPABI shared libraries and executables should have a PT_DYNAMIC
15074 segment. However, because the .dynamic section is not marked
15075 with SEC_LOAD, the generic ELF code will not create such a
15076 segment. */
15079 {
15085 {
15089 }
15090 }
15092 /* Also call the generic arm routine. */
15094 }
15096 /* Return address for Ith PLT stub in section PLT, for relocation REL
15097 or (bfd_vma) -1 if it should not be included. */
15099 static bfd_vma
15102 {
15104 }
15107 #undef elf32_bed
15108 #define elf32_bed elf32_arm_symbian_bed
15110 /* The dynamic sections are not allocated on SymbianOS; the postlinker
15111 will process them and then discard them. */
15112 #undef ELF_DYNAMIC_SEC_FLAGS
15113 #define ELF_DYNAMIC_SEC_FLAGS \
15114 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
15116 #undef elf_backend_add_symbol_hook
15117 #undef elf_backend_emit_relocs
15119 #undef bfd_elf32_bfd_link_hash_table_create
15120 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
15121 #undef elf_backend_special_sections
15122 #define elf_backend_special_sections elf32_arm_symbian_special_sections
15123 #undef elf_backend_begin_write_processing
15124 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
15125 #undef elf_backend_final_write_processing
15126 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15128 #undef elf_backend_modify_segment_map
15129 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
15131 /* There is no .got section for BPABI objects, and hence no header. */
15132 #undef elf_backend_got_header_size
15133 #define elf_backend_got_header_size 0
15135 /* Similarly, there is no .got.plt section. */
15136 #undef elf_backend_want_got_plt
15137 #define elf_backend_want_got_plt 0
15139 #undef elf_backend_plt_sym_val
15140 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
15142 #undef elf_backend_may_use_rel_p
15143 #define elf_backend_may_use_rel_p 1
15144 #undef elf_backend_may_use_rela_p
15145 #define elf_backend_may_use_rela_p 0
15146 #undef elf_backend_default_use_rela_p
15147 #define elf_backend_default_use_rela_p 0
15148 #undef elf_backend_want_plt_sym
15149 #define elf_backend_want_plt_sym 0
15150 #undef ELF_MAXPAGESIZE
15151 #define ELF_MAXPAGESIZE 0x8000