| blob | f42b2bf8138c9b8d73abbfc04a1b8b6c5d8c2950 |
1 /* 32-bit ELF support for ARM
2 Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007,
3 2008, 2009, 2010, 2011 Free Software Foundation, Inc.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
23 #include <limits.h>
32 /* Return the relocation section associated with NAME. HTAB is the
33 bfd's elf32_arm_link_hash_entry. */
34 #define RELOC_SECTION(HTAB, NAME) \
37 /* Return size of a relocation entry. HTAB is the bfd's
38 elf32_arm_link_hash_entry. */
39 #define RELOC_SIZE(HTAB) \
40 ((HTAB)->use_rel \
41 ? sizeof (Elf32_External_Rel) \
42 : sizeof (Elf32_External_Rela))
44 /* Return function to swap relocations in. HTAB is the bfd's
45 elf32_arm_link_hash_entry. */
46 #define SWAP_RELOC_IN(HTAB) \
47 ((HTAB)->use_rel \
48 ? bfd_elf32_swap_reloc_in \
49 : bfd_elf32_swap_reloca_in)
51 /* Return function to swap relocations out. HTAB is the bfd's
52 elf32_arm_link_hash_entry. */
53 #define SWAP_RELOC_OUT(HTAB) \
54 ((HTAB)->use_rel \
55 ? bfd_elf32_swap_reloc_out \
56 : bfd_elf32_swap_reloca_out)
58 #define elf_info_to_howto 0
59 #define elf_info_to_howto_rel elf32_arm_info_to_howto
61 #define ARM_ELF_ABI_VERSION 0
62 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
69 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
70 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
71 in that slot. */
74 {
75 /* No relocation. */
104 /* 32 bit absolute */
119 /* standard 32bit pc-relative reloc */
134 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
149 /* 16 bit absolute */
164 /* 12 bit absolute */
193 /* 8 bit absolute */
292 /* BLX instruction for the ARM. */
307 /* BLX instruction for the Thumb. */
322 /* Dynamic TLS relocations. */
366 /* Relocs used in ARM Linux */
830 /* These are declared as 13-bit signed relocations because we can
831 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
832 versa. */
889 /* Group relocations. */
1269 /* End of group relocations. */
1483 /* GNU extension to record C++ vtable member usage */
1498 /* GNU extension to record C++ vtable hierarchy */
1541 /* TLS relocations */
1654 /* 112-127 private relocations. */
1672 /* R_ARM_ME_TOO, obsolete. */
1688 };
1690 /* 160 onwards: */
1692 {
1706 };
1708 /* 249-255 extended, currently unused, relocations: */
1710 {
1766 };
1770 {
1782 }
1784 static void
1787 {
1792 }
1794 struct elf32_arm_reloc_map
1795 {
1796 bfd_reloc_code_real_type bfd_reloc_val;
1798 };
1800 /* All entries in this list must also be present in elf32_arm_howto_table. */
1802 {
1889 };
1893 bfd_reloc_code_real_type code)
1894 {
1902 }
1907 {
1926 }
1928 /* Support for core dump NOTE sections. */
1930 static bfd_boolean
1932 {
1937 {
1942 /* pr_cursig */
1945 /* pr_pid */
1948 /* pr_reg */
1953 }
1955 /* Make a ".reg/999" section. */
1958 }
1960 static bfd_boolean
1962 {
1964 {
1973 }
1975 /* Note that for some reason, a spurious space is tacked
1976 onto the end of the args in some (at least one anyway)
1977 implementations, so strip it off if it exists. */
1978 {
1984 }
1987 }
1989 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vec
1991 #define TARGET_BIG_SYM bfd_elf32_bigarm_vec
1994 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
1995 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2000 /* In lieu of proper flags, assume all EABIv4 or later objects are
2001 interworkable. */
2002 #define INTERWORK_FLAG(abfd) \
2003 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2004 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2005 || ((abfd)->flags & BFD_LINKER_CREATED))
2007 /* The linker script knows the section names for placement.
2008 The entry_names are used to do simple name mangling on the stubs.
2009 Given a function name, and its type, the stub can be found. The
2010 name can be changed. The only requirement is the %s be present. */
2025 /* The name of the dynamic interpreter. This is put in the .interp
2026 section. */
2030 {
2034 };
2037 {
2045 + dl_tlsdesc_lazy_resolver(GOT) */
2047 };
2049 #ifdef FOUR_WORD_PLT
2051 /* The first entry in a procedure linkage table looks like
2052 this. It is set up so that any shared library function that is
2053 called before the relocation has been set up calls the dynamic
2054 linker first. */
2056 {
2061 };
2063 /* Subsequent entries in a procedure linkage table look like
2064 this. */
2066 {
2071 };
2073 #else
2075 /* The first entry in a procedure linkage table looks like
2076 this. It is set up so that any shared library function that is
2077 called before the relocation has been set up calls the dynamic
2078 linker first. */
2080 {
2086 };
2088 /* Subsequent entries in a procedure linkage table look like
2089 this. */
2091 {
2095 };
2097 #endif
2099 /* The format of the first entry in the procedure linkage table
2100 for a VxWorks executable. */
2102 {
2107 };
2109 /* The format of subsequent entries in a VxWorks executable. */
2111 {
2118 };
2120 /* The format of entries in a VxWorks shared library. */
2122 {
2129 };
2131 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2132 #define PLT_THUMB_STUB_SIZE 4
2134 {
2137 };
2139 /* The entries in a PLT when using a DLL-based target with multiple
2140 address spaces. */
2142 {
2145 };
2147 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2148 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2149 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2150 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2151 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2152 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2154 enum stub_insn_type
2155 {
2157 THUMB32_TYPE,
2158 ARM_TYPE,
2159 DATA_TYPE
2160 };
2162 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2163 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2164 is inserted in arm_build_one_stub(). */
2165 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2166 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2167 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2168 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2169 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2170 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2173 {
2174 bfd_vma data;
2180 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2181 to reach the stub if necessary. */
2183 {
2186 };
2188 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2189 available. */
2191 {
2195 };
2197 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2199 {
2207 };
2209 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2210 allowed. */
2212 {
2218 };
2220 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2221 available. */
2223 {
2228 };
2230 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2231 one, when the destination is close enough. */
2233 {
2237 };
2239 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2240 blx to reach the stub if necessary. */
2242 {
2246 };
2248 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2249 blx to reach the stub if necessary. We can not add into pc;
2250 it is not guaranteed to mode switch (different in ARMv6 and
2251 ARMv7). */
2253 {
2258 };
2260 /* V4T ARM -> ARM long branch stub, PIC. */
2262 {
2267 };
2269 /* V4T Thumb -> ARM long branch stub, PIC. */
2271 {
2277 };
2279 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2280 architectures. */
2282 {
2290 };
2292 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2293 allowed. */
2295 {
2302 };
2304 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2305 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2307 {
2311 };
2313 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2314 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2316 {
2322 };
2324 /* Cortex-A8 erratum-workaround stubs. */
2326 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2327 can't use a conditional branch to reach this stub). */
2330 {
2334 };
2336 /* Stub used for b.w and bl.w instructions. */
2339 {
2341 };
2344 {
2346 };
2348 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2349 instruction (which switches to ARM mode) to point to this stub. Jump to the
2350 real destination using an ARM-mode branch. */
2353 {
2355 };
2357 /* For each section group there can be a specially created linker section
2358 to hold the stubs for that group. The name of the stub section is based
2359 upon the name of another section within that group with the suffix below
2360 applied.
2362 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2363 create what appeared to be a linker stub section when it actually
2364 contained user code/data. For example, consider this fragment:
2366 const char * stubborn_problems[] = { "np" };
2368 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2369 section called:
2371 .data.rel.local.stubborn_problems
2373 This then causes problems in arm32_arm_build_stubs() as it triggers:
2375 // Ignore non-stub sections.
2376 if (!strstr (stub_sec->name, STUB_SUFFIX))
2377 continue;
2379 And so the section would be ignored instead of being processed. Hence
2380 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2381 C identifier. */
2384 /* One entry per long/short branch stub defined above. */
2385 #define DEF_STUBS \
2386 DEF_STUB(long_branch_any_any) \
2387 DEF_STUB(long_branch_v4t_arm_thumb) \
2388 DEF_STUB(long_branch_thumb_only) \
2389 DEF_STUB(long_branch_v4t_thumb_thumb) \
2390 DEF_STUB(long_branch_v4t_thumb_arm) \
2391 DEF_STUB(short_branch_v4t_thumb_arm) \
2392 DEF_STUB(long_branch_any_arm_pic) \
2393 DEF_STUB(long_branch_any_thumb_pic) \
2394 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2395 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2396 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2397 DEF_STUB(long_branch_thumb_only_pic) \
2398 DEF_STUB(long_branch_any_tls_pic) \
2399 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2400 DEF_STUB(a8_veneer_b_cond) \
2401 DEF_STUB(a8_veneer_b) \
2402 DEF_STUB(a8_veneer_bl) \
2403 DEF_STUB(a8_veneer_blx)
2405 #define DEF_STUB(x) arm_stub_##x,
2407 arm_stub_none,
2408 DEF_STUBS
2409 /* Note the first a8_veneer type */
2410 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2411 };
2412 #undef DEF_STUB
2415 {
2420 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2423 DEF_STUBS
2424 };
2426 struct elf32_arm_stub_hash_entry
2427 {
2428 /* Base hash table entry structure. */
2431 /* The stub section. */
2434 /* Offset within stub_sec of the beginning of this stub. */
2435 bfd_vma stub_offset;
2437 /* Given the symbol's value and its section we can determine its final
2438 value when building the stubs (so the stub knows where to jump). */
2439 bfd_vma target_value;
2442 /* Offset to apply to relocation referencing target_value. */
2443 bfd_vma target_addend;
2445 /* The instruction which caused this stub to be generated (only valid for
2446 Cortex-A8 erratum workaround stubs at present). */
2449 /* The stub type. */
2451 /* Its encoding size in bytes. */
2453 /* Its template. */
2455 /* The size of the template (number of entries). */
2458 /* The symbol table entry, if any, that this was derived from. */
2461 /* Type of branch. */
2464 /* Where this stub is being called from, or, in the case of combined
2465 stub sections, the first input section in the group. */
2468 /* The name for the local symbol at the start of this stub. The
2469 stub name in the hash table has to be unique; this does not, so
2470 it can be friendlier. */
2472 };
2474 /* Used to build a map of a section. This is required for mixed-endian
2475 code/data. */
2478 {
2479 bfd_vma vma;
2481 }
2482 elf32_arm_section_map;
2484 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2487 {
2488 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2489 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2490 VFP11_ERRATUM_ARM_VENEER,
2491 VFP11_ERRATUM_THUMB_VENEER
2492 }
2493 elf32_vfp11_erratum_type;
2496 {
2498 bfd_vma vma;
2499 union
2500 {
2501 struct
2502 {
2506 struct
2507 {
2512 elf32_vfp11_erratum_type type;
2513 }
2514 elf32_vfp11_erratum_list;
2517 {
2518 DELETE_EXIDX_ENTRY,
2519 INSERT_EXIDX_CANTUNWIND_AT_END
2520 }
2521 arm_unwind_edit_type;
2523 /* A (sorted) list of edits to apply to an unwind table. */
2525 {
2526 arm_unwind_edit_type type;
2527 /* Note: we sometimes want to insert an unwind entry corresponding to a
2528 section different from the one we're currently writing out, so record the
2529 (text) section this edit relates to here. */
2533 }
2534 arm_unwind_table_edit;
2537 {
2538 /* Information about mapping symbols. */
2543 /* Information about CPU errata. */
2546 /* Information about unwind tables. */
2547 union
2548 {
2549 /* Unwind info attached to a text section. */
2550 struct
2551 {
2555 /* Unwind info attached to an .ARM.exidx section. */
2556 struct
2557 {
2562 }
2563 _arm_elf_section_data;
2565 #define elf32_arm_section_data(sec) \
2566 ((_arm_elf_section_data *) elf_section_data (sec))
2568 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2569 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2570 so may be created multiple times: we use an array of these entries whilst
2571 relaxing which we can refresh easily, then create stubs for each potentially
2572 erratum-triggering instruction once we've settled on a solution. */
2577 bfd_vma offset;
2578 bfd_vma addend;
2583 };
2585 /* A table of relocs applied to branches which might trigger Cortex-A8
2586 erratum. */
2589 bfd_vma from;
2590 bfd_vma destination;
2595 bfd_boolean non_a8_stub;
2596 };
2598 /* The size of the thread control block. */
2599 #define TCB_SIZE 8
2601 /* ARM-specific information about a PLT entry, over and above the usual
2602 gotplt_union. */
2604 /* We reference count Thumb references to a PLT entry separately,
2605 so that we can emit the Thumb trampoline only if needed. */
2606 bfd_signed_vma thumb_refcount;
2608 /* Some references from Thumb code may be eliminated by BL->BLX
2609 conversion, so record them separately. */
2610 bfd_signed_vma maybe_thumb_refcount;
2612 /* How many of the recorded PLT accesses were from non-call relocations.
2613 This information is useful when deciding whether anything takes the
2614 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2615 non-call references to the function should resolve directly to the
2616 real runtime target. */
2619 /* Since PLT entries have variable size if the Thumb prologue is
2620 used, we need to record the index into .got.plt instead of
2621 recomputing it from the PLT offset. */
2622 bfd_signed_vma got_offset;
2623 };
2625 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2627 /* The information that is usually found in the generic ELF part of
2628 the hash table entry. */
2631 /* The information that is usually found in the ARM-specific part of
2632 the hash table entry. */
2635 /* A list of all potential dynamic relocations against this symbol. */
2637 };
2639 struct elf_arm_obj_tdata
2640 {
2643 /* tls_type for each local got entry. */
2646 /* GOTPLT entries for TLS descriptors. */
2649 /* Information for local symbols that need entries in .iplt. */
2652 /* Zero to warn when linking objects with incompatible enum sizes. */
2655 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2657 };
2659 #define elf_arm_tdata(bfd) \
2660 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2662 #define elf32_arm_local_got_tls_type(bfd) \
2663 (elf_arm_tdata (bfd)->local_got_tls_type)
2665 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2666 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2668 #define elf32_arm_local_iplt(bfd) \
2669 (elf_arm_tdata (bfd)->local_iplt)
2671 #define is_arm_elf(bfd) \
2672 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2673 && elf_tdata (bfd) != NULL \
2674 && elf_object_id (bfd) == ARM_ELF_DATA)
2676 static bfd_boolean
2678 {
2680 ARM_ELF_DATA);
2681 }
2683 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2685 /* Arm ELF linker hash entry. */
2686 struct elf32_arm_link_hash_entry
2687 {
2690 /* Track dynamic relocs copied for this symbol. */
2693 /* ARM-specific PLT information. */
2696 #define GOT_UNKNOWN 0
2697 #define GOT_NORMAL 1
2698 #define GOT_TLS_GD 2
2699 #define GOT_TLS_IE 4
2700 #define GOT_TLS_GDESC 8
2701 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2704 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2709 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2710 starting at the end of the jump table. */
2711 bfd_vma tlsdesc_got;
2713 /* The symbol marking the real symbol location for exported thumb
2714 symbols with Arm stubs. */
2717 /* A pointer to the most recently used stub hash entry against this
2718 symbol. */
2720 };
2722 /* Traverse an arm ELF linker hash table. */
2723 #define elf32_arm_link_hash_traverse(table, func, info) \
2724 (elf_link_hash_traverse \
2725 (&(table)->root, \
2726 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2727 (info)))
2729 /* Get the ARM elf linker hash table from a link_info structure. */
2730 #define elf32_arm_hash_table(info) \
2731 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2732 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2734 #define arm_stub_hash_lookup(table, string, create, copy) \
2735 ((struct elf32_arm_stub_hash_entry *) \
2736 bfd_hash_lookup ((table), (string), (create), (copy)))
2738 /* Array to keep track of which stub sections have been created, and
2739 information on stub grouping. */
2740 struct map_stub
2741 {
2742 /* This is the section to which stubs in the group will be
2743 attached. */
2745 /* The stub section. */
2747 };
2749 #define elf32_arm_compute_jump_table_size(htab) \
2750 ((htab)->next_tls_desc_index * 4)
2752 /* ARM ELF linker hash table. */
2753 struct elf32_arm_link_hash_table
2754 {
2755 /* The main hash table. */
2758 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2759 bfd_size_type thumb_glue_size;
2761 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2762 bfd_size_type arm_glue_size;
2764 /* The size in bytes of section containing the ARMv4 BX veneers. */
2765 bfd_size_type bx_glue_size;
2767 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2768 veneer has been populated. */
2771 /* The size in bytes of the section containing glue for VFP11 erratum
2772 veneers. */
2773 bfd_size_type vfp11_erratum_glue_size;
2775 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2776 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2777 elf32_arm_write_section(). */
2781 /* An arbitrary input BFD chosen to hold the glue sections. */
2784 /* Nonzero to output a BE8 image. */
2787 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2788 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2791 /* The relocation to use for R_ARM_TARGET2 relocations. */
2794 /* 0 = Ignore R_ARM_V4BX.
2795 1 = Convert BX to MOV PC.
2796 2 = Generate v4 interworing stubs. */
2799 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2802 /* Whether we should fix the ARM1176 BLX immediate issue. */
2805 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2808 /* What sort of code sequences we should look for which may trigger the
2809 VFP11 denorm erratum. */
2810 bfd_arm_vfp11_fix vfp11_fix;
2812 /* Global counter for the number of fixes we have emitted. */
2815 /* Nonzero to force PIC branch veneers. */
2818 /* The number of bytes in the initial entry in the PLT. */
2819 bfd_size_type plt_header_size;
2821 /* The number of bytes in the subsequent PLT etries. */
2822 bfd_size_type plt_entry_size;
2824 /* True if the target system is VxWorks. */
2827 /* True if the target system is Symbian OS. */
2830 /* True if the target uses REL relocations. */
2833 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
2834 bfd_vma next_tls_desc_index;
2836 /* How many R_ARM_TLS_DESC relocations were generated so far. */
2837 bfd_vma num_tls_desc;
2839 /* Short-cuts to get to dynamic linker sections. */
2843 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
2846 /* The offset into splt of the PLT entry for the TLS descriptor
2847 resolver. Special values are 0, if not necessary (or not found
2848 to be necessary yet), and -1 if needed but not determined
2849 yet. */
2850 bfd_vma dt_tlsdesc_plt;
2852 /* The offset into sgot of the GOT entry used by the PLT entry
2853 above. */
2854 bfd_vma dt_tlsdesc_got;
2856 /* Offset in .plt section of tls_arm_trampoline. */
2857 bfd_vma tls_trampoline;
2859 /* Data for R_ARM_TLS_LDM32 relocations. */
2860 union
2861 {
2862 bfd_signed_vma refcount;
2863 bfd_vma offset;
2866 /* Small local sym cache. */
2869 /* For convenience in allocate_dynrelocs. */
2872 /* The amount of space used by the reserved portion of the sgotplt
2873 section, plus whatever space is used by the jump slots. */
2874 bfd_vma sgotplt_jump_table_size;
2876 /* The stub hash table. */
2879 /* Linker stub bfd. */
2882 /* Linker call-backs. */
2886 /* Array to keep track of which stub sections have been created, and
2887 information on stub grouping. */
2890 /* Number of elements in stub_group. */
2893 /* Assorted information used by elf32_arm_size_stubs. */
2897 };
2899 /* Create an entry in an ARM ELF linker hash table. */
2905 {
2909 /* Allocate the structure if it has not already been allocated by a
2910 subclass. */
2917 /* Call the allocation method of the superclass. */
2922 {
2934 }
2937 }
2939 /* Ensure that we have allocated bookkeeping structures for ABFD's local
2940 symbols. */
2942 static bfd_boolean
2944 {
2946 {
2947 bfd_size_type num_syms;
2948 bfd_size_type size;
2970 }
2972 }
2974 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
2975 to input bfd ABFD. Create the information if it doesn't already exist.
2976 Return null if an allocation fails. */
2980 {
2991 }
2993 /* Try to obtain PLT information for the symbol with index R_SYMNDX
2994 in ABFD's symbol table. If the symbol is global, H points to its
2995 hash table entry, otherwise H is null.
2997 Return true if the symbol does have PLT information. When returning
2998 true, point *ROOT_PLT at the target-independent reference count/offset
2999 union and *ARM_PLT at the ARM-specific information. */
3001 static bfd_boolean
3005 {
3009 {
3013 }
3025 }
3027 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3028 before it. */
3030 static bfd_boolean
3033 {
3039 }
3041 /* Return a pointer to the head of the dynamic reloc list that should
3042 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3043 ABFD's symbol table. Return null if an error occurs. */
3048 {
3050 {
3057 }
3058 else
3059 {
3060 /* Track dynamic relocs needed for local syms too.
3061 We really need local syms available to do this
3062 easily. Oh well. */
3072 }
3073 }
3075 /* Initialize an entry in the stub hash table. */
3081 {
3082 /* Allocate the structure if it has not already been allocated by a
3083 subclass. */
3085 {
3090 }
3092 /* Call the allocation method of the superclass. */
3095 {
3098 /* Initialize the local fields. */
3113 }
3116 }
3118 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3119 shortcuts to them in our hash table. */
3121 static bfd_boolean
3123 {
3130 /* BPABI objects never have a GOT, or associated sections. */
3138 }
3140 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3142 static bfd_boolean
3144 {
3149 flagword flags;
3157 {
3164 }
3167 {
3174 }
3177 {
3183 }
3185 }
3187 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3188 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3189 hash table. */
3191 static bfd_boolean
3193 {
3212 {
3217 {
3219 htab->plt_entry_size
3221 }
3222 else
3223 {
3224 htab->plt_header_size
3226 htab->plt_entry_size
3228 }
3229 }
3238 }
3240 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3242 static void
3246 {
3253 {
3255 {
3259 /* Add reloc counts against the indirect sym to the direct sym
3260 list. Merge any entries against the same section. */
3262 {
3267 {
3272 }
3275 }
3277 }
3281 }
3284 {
3285 /* Copy over PLT info. */
3293 /* We should only allocate a function to .iplt once the final
3294 symbol information is known. */
3298 {
3301 }
3302 }
3305 }
3307 /* Create an ARM elf linker hash table. */
3311 {
3320 elf32_arm_link_hash_newfunc,
3322 ARM_ELF_DATA))
3323 {
3326 }
3349 #ifdef FOUR_WORD_PLT
3352 #else
3355 #endif
3375 {
3378 }
3381 }
3383 /* Free the derived linker hash table. */
3385 static void
3387 {
3393 }
3395 /* Determine if we're dealing with a Thumb only architecture. */
3397 static bfd_boolean
3399 {
3401 Tag_CPU_arch);
3411 Tag_CPU_arch_profile);
3414 }
3416 /* Determine if we're dealing with a Thumb-2 object. */
3418 static bfd_boolean
3420 {
3422 Tag_CPU_arch);
3424 }
3426 /* Determine what kind of NOPs are available. */
3428 static bfd_boolean
3430 {
3432 Tag_CPU_arch);
3437 }
3439 static bfd_boolean
3441 {
3443 Tag_CPU_arch);
3446 }
3448 static bfd_boolean
3450 {
3452 {
3466 }
3467 }
3469 /* Determine the type of stub needed, if any, for a call. */
3471 static enum elf32_arm_stub_type
3478 bfd_vma destination,
3482 {
3483 bfd_vma location;
3484 bfd_signed_vma branch_offset;
3506 /* Determine where the call point is. */
3513 /* For TLS call relocs, it is the caller's responsibility to provide
3514 the address of the appropriate trampoline. */
3520 {
3525 else
3528 {
3531 /* Note when dealing with PLT entries: the main PLT stub is in
3532 ARM mode, so if the branch is in Thumb mode, another
3533 Thumb->ARM stub will be inserted later just before the ARM
3534 PLT stub. We don't take this extra distance into account
3535 here, because if a long branch stub is needed, we'll add a
3536 Thumb->Arm one and branch directly to the ARM PLT entry
3537 because it avoids spreading offset corrections in several
3538 places. */
3545 }
3546 }
3547 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3554 {
3555 /* Handle cases where:
3556 - this call goes too far (different Thumb/Thumb2 max
3557 distance)
3558 - it's a Thumb->Arm call and blx is not available, or it's a
3559 Thumb->Arm branch (not bl). A stub is needed in this case,
3560 but only if this call is not through a PLT entry. Indeed,
3561 PLT stubs handle mode switching already.
3562 */
3566 || (thumb2
3574 {
3576 {
3577 /* Thumb to thumb. */
3579 {
3581 /* PIC stubs. */
3584 /* V5T and above. Stub starts with ARM code, so
3585 we must be able to switch mode before
3586 reaching it, which is only possible for 'bl'
3587 (ie R_ARM_THM_CALL relocation). */
3588 ? arm_stub_long_branch_any_thumb_pic
3589 /* On V4T, use Thumb code only. */
3592 /* non-PIC stubs. */
3595 /* V5T and above. */
3596 ? arm_stub_long_branch_any_any
3597 /* V4T. */
3599 }
3600 else
3601 {
3603 /* PIC stub. */
3604 ? arm_stub_long_branch_thumb_only_pic
3605 /* non-PIC stub. */
3607 }
3608 }
3609 else
3610 {
3611 /* Thumb to arm. */
3615 {
3620 }
3622 stub_type =
3624 /* PIC stubs. */
3626 /* TLS PIC stubs */
3630 /* V5T PIC and above. */
3631 ? arm_stub_long_branch_any_arm_pic
3632 /* V4T PIC stub. */
3635 /* non-PIC stubs. */
3637 /* V5T and above. */
3638 ? arm_stub_long_branch_any_any
3639 /* V4T. */
3642 /* Handle v4t short branches. */
3647 }
3648 }
3649 }
3654 {
3656 {
3657 /* Arm to thumb. */
3662 {
3667 }
3669 /* We have an extra 2-bytes reach because of
3670 the mode change (bit 24 (H) of BLX encoding). */
3676 {
3678 /* PIC stubs. */
3680 /* V5T and above. */
3681 ? arm_stub_long_branch_any_thumb_pic
3682 /* V4T stub. */
3685 /* non-PIC stubs. */
3687 /* V5T and above. */
3688 ? arm_stub_long_branch_any_any
3689 /* V4T. */
3691 }
3692 }
3693 else
3694 {
3695 /* Arm to arm. */
3698 {
3699 stub_type =
3701 /* PIC stubs. */
3703 /* TLS PIC Stub */
3704 ? arm_stub_long_branch_any_tls_pic
3706 /* non-PIC stubs. */
3708 }
3709 }
3710 }
3712 /* If a stub is needed, record the actual destination type. */
3717 }
3719 /* Build a name for an entry in the stub hash table. */
3727 {
3729 bfd_size_type len;
3732 {
3741 }
3742 else
3743 {
3755 }
3758 }
3760 /* Look up an entry in the stub hash. Stub entries are cached because
3761 creating the stub name takes a bit of time. */
3770 {
3778 /* If this input section is part of a group of sections sharing one
3779 stub section, then use the id of the first section in the group.
3780 Stub names need to include a section id, as there may well be
3781 more than one stub used to reach say, printf, and we need to
3782 distinguish between them. */
3789 {
3791 }
3792 else
3793 {
3806 }
3809 }
3811 /* Find or create a stub section. Returns a pointer to the stub section, and
3812 the section to which the stub section will be attached (in *LINK_SEC_P).
3813 LINK_SEC_P may be NULL. */
3818 {
3827 {
3830 {
3832 bfd_size_type len;
3847 }
3849 }
3855 }
3857 /* Add a new stub entry to the stub hash. Not all fields of the new
3858 stub entry are initialised. */
3864 {
3873 /* Enter this entry into the linker stub hash table. */
3877 {
3880 stub_name);
3882 }
3889 }
3891 /* Store an Arm insn into an output section not processed by
3892 elf32_arm_write_section. */
3894 static void
3897 {
3900 else
3902 }
3904 /* Store a 16-bit Thumb insn into an output section not processed by
3905 elf32_arm_write_section. */
3907 static void
3910 {
3913 else
3915 }
3917 /* If it's possible to change R_TYPE to a more efficient access
3918 model, return the new reloc type. */
3920 static unsigned
3923 {
3929 /* We do not support relaxations for Old TLS models. */
3931 {
3938 }
3941 }
3943 static bfd_reloc_status_type elf32_arm_final_link_relocate
3949 static unsigned int
3951 {
3953 {
3978 }
3979 }
3981 static bfd_boolean
3984 {
3985 #define MAXRELOCS 2
3992 bfd_vma sym_value;
4001 /* Massage our args to the form they really have. */
4013 /* We have to do less-strictly-aligned fixes last. */
4016 /* Make a note of the offset within the stubs for this entry. */
4022 /* This is the address of the stub destination. */
4032 {
4034 {
4036 {
4039 {
4040 /* We've borrowed the reloc_addend field to mean we should
4041 insert a condition code into this (Thumb-1 branch)
4042 instruction. See THUMB16_BCOND_INSN. */
4045 }
4048 }
4058 {
4061 }
4068 /* Handle cases where the target is encoded within the
4069 instruction. */
4071 {
4074 }
4088 }
4089 }
4093 /* Stub size has already been computed in arm_size_one_stub. Check
4094 consistency. */
4097 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4101 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4102 in each stub. */
4110 {
4111 Elf_Internal_Rela rel;
4112 bfd_boolean unresolved_reloc;
4114 enum arm_st_branch_type branch_type
4125 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4126 template should refer back to the instruction after the original
4127 branch. */
4130 /* There may be unintended consequences if this is not true. */
4133 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4134 properly. We should probably use this function unconditionally,
4135 rather than only for certain relocations listed in the enclosing
4136 conditional, for the sake of consistency. */
4143 }
4144 else
4145 {
4146 Elf_Internal_Rela rel;
4147 bfd_boolean unresolved_reloc;
4164 }
4167 #undef MAXRELOCS
4168 }
4170 /* Calculate the template, template size and instruction size for a stub.
4171 Return value is the instruction size. */
4173 static unsigned int
4177 {
4192 {
4194 {
4208 }
4209 }
4212 }
4214 /* As above, but don't actually build the stub. Just bump offset so
4215 we know stub section sizes. */
4217 static bfd_boolean
4220 {
4225 /* Massage our args to the form they really have. */
4242 }
4244 /* External entry points for sizing and building linker stubs. */
4246 /* Set up various things so that we can make a list of input sections
4247 for each output section included in the link. Returns -1 on error,
4248 0 when no stubs will be needed, and 1 on success. */
4250 int
4253 {
4259 bfd_size_type amt;
4267 /* Count the number of input BFDs and find the top input section id. */
4271 {
4276 {
4279 }
4280 }
4289 /* We can't use output_bfd->section_count here to find the top output
4290 section index as some sections may have been removed, and
4291 _bfd_strip_section_from_output doesn't renumber the indices. */
4295 {
4298 }
4307 /* For sections we aren't interested in, mark their entries with a
4308 value we can check later. */
4310 do
4317 {
4320 }
4323 }
4325 /* The linker repeatedly calls this function for each input section,
4326 in the order that input sections are linked into output sections.
4327 Build lists of input sections to determine groupings between which
4328 we may insert linker stubs. */
4330 void
4333 {
4340 {
4344 {
4345 /* Steal the link_sec pointer for our list. */
4346 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4347 /* This happens to make the list in reverse order,
4348 which we reverse later. */
4351 }
4352 }
4353 }
4355 /* See whether we can group stub sections together. Grouping stub
4356 sections may result in fewer stubs. More importantly, we need to
4357 put all .init* and .fini* stubs at the end of the .init or
4358 .fini output sections respectively, because glibc splits the
4359 _init and _fini functions into multiple parts. Putting a stub in
4360 the middle of a function is not a good idea. */
4362 static void
4364 bfd_size_type stub_group_size,
4365 bfd_boolean stubs_always_after_branch)
4366 {
4369 do
4370 {
4377 /* Reverse the list: we must avoid placing stubs at the
4378 beginning of the section because the beginning of the text
4379 section may be required for an interrupt vector in bare metal
4380 code. */
4381 #define NEXT_SEC PREV_SEC
4384 {
4385 /* Pop from tail. */
4389 /* Push on head. */
4392 }
4395 {
4399 bfd_vma end_of_next;
4403 {
4407 /* End of NEXT is too far from start, so stop. */
4409 /* Add NEXT to the group. */
4411 }
4413 /* OK, the size from the start to the start of CURR is less
4414 than stub_group_size and thus can be handled by one stub
4415 section. (Or the head section is itself larger than
4416 stub_group_size, in which case we may be toast.)
4417 We should really be keeping track of the total size of
4418 stubs added here, as stubs contribute to the final output
4419 section size. */
4420 do
4421 {
4423 /* Set up this stub group. */
4425 }
4428 /* But wait, there's more! Input sections up to stub_group_size
4429 bytes after the stub section can be handled by it too. */
4431 {
4435 {
4438 /* End of NEXT is too far from stubs, so stop. */
4440 /* Add NEXT to the stub group. */
4444 }
4445 }
4447 }
4448 }
4452 #undef PREV_SEC
4453 #undef NEXT_SEC
4454 }
4456 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4457 erratum fix. */
4459 static int
4461 {
4469 else
4471 }
4476 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4477 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4478 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4479 otherwise. */
4481 static bfd_boolean
4491 {
4504 {
4508 bfd_vma base_vma;
4527 {
4538 /* Span is entirely within a single 4KB region: skip scanning. */
4543 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4545 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4546 * The branch target is in the same 4KB region as the
4547 first half of the branch.
4548 * The instruction before the branch is a 32-bit
4549 length non-branch instruction. */
4551 {
4560 {
4561 /* Load the rest of the insn (in manual-friendly order). */
4564 /* Encoding T4: B<c>.W. */
4566 /* Encoding T1: BL<c>.W. */
4568 /* Encoding T2: BLX<c>.W. */
4570 /* Encoding T3: B<c>.W (not permitted in IT block). */
4573 }
4578 && insn_32bit
4579 && is_32bit_branch
4580 && last_was_32bit
4582 {
4586 bfd_vma target;
4598 {
4602 /* We don't care about the error returned from this
4603 function, only if there is glue or not. */
4610 /* Keep a simpler condition, for the sake of clarity. */
4616 {
4620 else
4622 }
4623 }
4625 /* Check if we have an offending branch instruction. */
4628 /* We've already made a stub for this instruction, e.g.
4629 it's a long branch or a Thumb->ARM stub. Assume that
4630 stub will suffice to work around the A8 erratum (see
4631 setting of always_after_branch above). */
4632 ;
4634 {
4643 }
4645 {
4665 }
4668 {
4671 /* The original instruction is a BL, but the target is
4672 an ARM instruction. If we were not making a stub,
4673 the BL would have been converted to a BLX. Use the
4674 BLX stub instead in that case. */
4677 {
4681 }
4682 /* Conversely, if the original instruction was
4683 BLX but the target is Thumb mode, use the BL
4684 stub. */
4687 {
4691 }
4696 /* If we found a relocation, use the proper destination,
4697 not the offset in the (unrelocated) instruction.
4698 Note this is always done if we switched the stub type
4699 above. */
4701 offset =
4704 /* If the stub will use a Thumb-mode branch to a
4705 PLT target, redirect it to the preceding Thumb
4706 entry point. */
4712 /* The BLX stub is ARM-mode code. Adjust the offset to
4713 take the different PC value (+8 instead of +4) into
4714 account. */
4719 {
4723 {
4729 }
4732 {
4733 /* If we're doing a subsequent scan,
4734 check if we've found the same fix as
4735 before, and try and reuse the stub
4736 name. */
4740 {
4744 }
4745 }
4748 {
4752 }
4764 num_a8_fixes++;
4765 }
4766 }
4767 }
4772 }
4773 }
4777 }
4784 }
4786 /* Determine and set the size of the stub section for a final link.
4788 The basic idea here is to examine all the relocations looking for
4789 PC-relative calls to a target that is unreachable with a "bl"
4790 instruction. */
4792 bfd_boolean
4796 bfd_signed_vma group_size,
4799 {
4800 bfd_size_type stub_group_size;
4801 bfd_boolean stubs_always_after_branch;
4812 {
4817 }
4819 /* Propagate mach to stub bfd, because it may not have been
4820 finalized when we created stub_bfd. */
4824 /* Stash our params away. */
4830 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
4831 as the first half of a 32-bit branch straddling two 4K pages. This is a
4832 crude way of enforcing that. */
4838 else
4842 {
4843 /* Default values. */
4844 /* Thumb branch range is +-4MB has to be used as the default
4845 maximum size (a given section can contain both ARM and Thumb
4846 code, so the worst case has to be taken into account).
4848 This value is 24K less than that, which allows for 2025
4849 12-byte stubs. If we exceed that, then we will fail to link.
4850 The user will have to relink with an explicit group size
4851 option. */
4853 }
4857 /* If we're applying the cortex A8 fix, we need to determine the
4858 program header size now, because we cannot change it later --
4859 that could alter section placements. Notice the A8 erratum fix
4860 ends up requiring the section addresses to remain unchanged
4861 modulo the page size. That's something we cannot represent
4862 inside BFD, and we don't want to force the section alignment to
4863 be the page size. */
4868 {
4879 {
4886 /* We'll need the symbol table in a second. */
4891 /* Walk over each section attached to the input bfd. */
4895 {
4898 /* If there aren't any relocs, then there's nothing more
4899 to do. */
4905 /* If this section is a link-once section that will be
4906 discarded, then don't create any stubs. */
4911 /* Get the relocs. */
4912 internal_relocs
4918 /* Now examine each relocation. */
4922 {
4927 bfd_vma sym_value;
4928 bfd_vma destination;
4941 {
4943 error_ret_free_internal:
4947 }
4951 hash = elf32_arm_hash_entry
4955 /* Only look for stubs on branch instructions, or
4956 non-relaxed TLSCALL */
4969 : (elf32_arm_local_got_tls_type
4974 /* Now determine the call target, its name, value,
4975 section. */
4983 {
4984 /* A non-relaxed TLS call. The target is the
4985 plt-resident trampoline and nothing to do
4986 with the symbol. */
4993 }
4995 {
4996 /* It's a local symbol. */
5000 {
5001 local_syms
5004 local_syms
5010 }
5019 else
5020 sym_sec =
5024 /* This is an undefined symbol. It can never
5025 be resolved. */
5035 sym_name
5039 }
5040 else
5041 {
5042 /* It's an external symbol. */
5050 {
5057 /* For a destination in a shared library,
5058 use the PLT stub as target address to
5059 decide whether a branch stub is
5060 needed. */
5065 {
5069 destination = (sym_value
5072 }
5077 }
5080 {
5081 /* For a shared library, use the PLT stub as
5082 target address to decide whether a long
5083 branch stub is needed.
5084 For absolute code, they cannot be handled. */
5092 {
5096 destination = (sym_value
5099 }
5100 else
5102 }
5103 else
5104 {
5107 }
5111 }
5113 do
5114 {
5115 /* Determine what (if any) linker stub is needed. */
5123 /* Support for grouping stub sections. */
5126 /* Get the name of this stub. */
5132 /* We've either created a stub for this reloc already,
5133 or we are about to. */
5136 stub_entry = arm_stub_hash_lookup
5140 {
5141 /* The proper stub has already been created. */
5145 }
5148 htab);
5150 {
5153 }
5168 {
5171 }
5173 /* For historical reasons, use the existing names for
5174 ARM-to-Thumb and Thumb-to-ARM stubs. */
5185 else
5187 sym_name);
5190 }
5193 /* Look for relocations which might trigger Cortex-A8
5194 erratum. */
5200 {
5206 {
5207 /* Found a candidate. Note we haven't checked the
5208 destination is within 4K here: if we do so (and
5209 don't create an entry in a8_relocs) we can't tell
5210 that a branch should have been relocated when
5211 scanning later. */
5213 {
5219 }
5229 num_a8_relocs++;
5230 }
5231 }
5232 }
5234 /* We're done with the internal relocs, free them. */
5237 }
5240 {
5241 /* Sort relocs which might apply to Cortex-A8 erratum. */
5246 /* Scan for branches which might trigger Cortex-A8 erratum. */
5253 }
5254 }
5262 /* OK, we've added some stubs. Find out the new size of the
5263 stub sections. */
5267 {
5268 /* Ignore non-stub sections. */
5273 }
5277 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5280 {
5287 stub_sec->size
5289 NULL);
5290 }
5293 /* Ask the linker to do its stuff. */
5295 }
5297 /* Add stubs for Cortex-A8 erratum fixes now. */
5299 {
5301 {
5314 {
5317 stub_name);
5319 }
5338 }
5340 /* Stash the Cortex-A8 erratum fix array for use later in
5341 elf32_arm_write_section(). */
5344 }
5345 else
5346 {
5349 }
5352 error_ret_free_local:
5354 }
5356 /* Build all the stubs associated with the current output file. The
5357 stubs are kept in a hash table attached to the main linker hash
5358 table. We also set up the .plt entries for statically linked PIC
5359 functions here. This function is called via arm_elf_finish in the
5360 linker. */
5362 bfd_boolean
5364 {
5376 {
5377 bfd_size_type size;
5379 /* Ignore non-stub sections. */
5383 /* Allocate memory to hold the linker stubs. */
5389 }
5391 /* Build the stubs as directed by the stub hash table. */
5395 {
5396 /* Place the cortex a8 stubs last. */
5399 }
5402 }
5404 /* Locate the Thumb encoded calling stub for NAME. */
5410 {
5415 /* We need a pointer to the armelf specific hash table. */
5427 hash = elf_link_hash_lookup
5438 }
5440 /* Locate the ARM encoded calling stub for NAME. */
5446 {
5451 /* We need a pointer to the elfarm specific hash table. */
5463 myh = elf_link_hash_lookup
5474 }
5476 /* ARM->Thumb glue (static images):
5478 .arm
5479 __func_from_arm:
5480 ldr r12, __func_addr
5481 bx r12
5482 __func_addr:
5483 .word func @ behave as if you saw a ARM_32 reloc.
5485 (v5t static images)
5486 .arm
5487 __func_from_arm:
5488 ldr pc, __func_addr
5489 __func_addr:
5490 .word func @ behave as if you saw a ARM_32 reloc.
5492 (relocatable images)
5493 .arm
5494 __func_from_arm:
5495 ldr r12, __func_offset
5496 add r12, r12, pc
5497 bx r12
5498 __func_offset:
5499 .word func - . */
5501 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5506 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5510 #define ARM2THUMB_PIC_GLUE_SIZE 16
5515 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5517 .thumb .thumb
5518 .align 2 .align 2
5519 __func_from_thumb: __func_from_thumb:
5520 bx pc push {r6, lr}
5521 nop ldr r6, __func_addr
5522 .arm mov lr, pc
5523 b func bx r6
5524 .arm
5525 ;; back_to_thumb
5526 ldmia r13! {r6, lr}
5527 bx lr
5528 __func_addr:
5529 .word func */
5531 #define THUMB2ARM_GLUE_SIZE 8
5536 #define VFP11_ERRATUM_VENEER_SIZE 8
5538 #define ARM_BX_VENEER_SIZE 12
5543 #ifndef ELFARM_NABI_C_INCLUDED
5544 static void
5546 {
5551 {
5552 /* Do not include empty glue sections in the output. */
5554 {
5558 }
5560 }
5571 }
5573 bfd_boolean
5575 {
5583 ARM2THUMB_GLUE_SECTION_NAME);
5587 THUMB2ARM_GLUE_SECTION_NAME);
5591 VFP11_ERRATUM_VENEER_SECTION_NAME);
5595 ARM_BX_GLUE_SECTION_NAME);
5598 }
5600 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5601 returns the symbol identifying the stub. */
5606 {
5613 bfd_vma val;
5614 bfd_size_type size;
5620 s = bfd_get_section_by_name
5632 myh = elf_link_hash_lookup
5636 {
5637 /* We've already seen this guy. */
5640 }
5642 /* The only trick here is using hash_table->arm_glue_size as the value.
5643 Even though the section isn't allocated yet, this is where we will be
5644 putting it. The +1 on the value marks that the stub has not been
5645 output yet - not that it is a Thumb function. */
5663 else
5670 }
5672 /* Allocate space for ARMv4 BX veneers. */
5674 static void
5676 {
5682 bfd_vma val;
5684 /* BX PC does not need a veneer. */
5692 /* Check if this veneer has already been allocated. */
5696 s = bfd_get_section_by_name
5701 /* Add symbol for veneer. */
5709 myh = elf_link_hash_lookup
5727 }
5730 /* Add an entry to the code/data map for section SEC. */
5732 static void
5734 {
5739 {
5744 }
5749 {
5754 }
5757 {
5760 }
5761 }
5764 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5765 veneers are handled for now. */
5767 static bfd_vma
5773 {
5779 bfd_vma val;
5787 s = bfd_get_section_by_name
5802 myh = elf_link_hash_lookup
5817 /* Link veneer back to calling location. */
5831 /* A symbol for the return from the veneer. */
5835 myh = elf_link_hash_lookup
5852 /* Generate a mapping symbol for the veneer section, and explicitly add an
5853 entry for that symbol to the code/data map for the section. */
5855 {
5857 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
5858 ever requires this erratum fix. */
5868 /* The elf32_arm_init_maps function only cares about symbols from input
5869 BFDs. We must make a note of this generated mapping symbol
5870 ourselves so that code byteswapping works properly in
5871 elf32_arm_write_section. */
5873 }
5879 /* The offset of the veneer. */
5881 }
5883 #define ARM_GLUE_SECTION_FLAGS \
5884 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
5885 | SEC_READONLY | SEC_LINKER_CREATED)
5887 /* Create a fake section for use by the ARM backend of the linker. */
5889 static bfd_boolean
5891 {
5896 /* Already made. */
5905 /* Set the gc mark to prevent the section from being removed by garbage
5906 collection, despite the fact that no relocs refer to this section. */
5910 }
5912 /* Add the glue sections to ABFD. This function is called from the
5913 linker scripts in ld/emultempl/{armelf}.em. */
5915 bfd_boolean
5918 {
5919 /* If we are only performing a partial
5920 link do not bother adding the glue. */
5928 }
5930 /* Select a BFD to be used to hold the sections used by the glue code.
5931 This function is called from the linker scripts in ld/emultempl/
5932 {armelf/pe}.em. */
5934 bfd_boolean
5936 {
5939 /* If we are only performing a partial link
5940 do not bother getting a bfd to hold the glue. */
5944 /* Make sure we don't attach the glue sections to a dynamic object. */
5953 /* Save the bfd for later use. */
5957 }
5959 static void
5961 {
5965 Tag_CPU_arch);
5968 {
5971 }
5972 else
5973 {
5976 }
5977 }
5979 bfd_boolean
5982 {
5991 /* If we are only performing a partial link do not bother
5992 to construct any glue. */
5996 /* Here we have a bfd that is to be included on the link. We have a
5997 hook to do reloc rummaging, before section sizes are nailed down. */
6004 {
6006 abfd);
6008 }
6010 /* PR 5398: If we have not decided to include any loadable sections in
6011 the output then we will not have a glue owner bfd. This is OK, it
6012 just means that there is nothing else for us to do here. */
6016 /* Rummage around all the relocs and map the glue vectors. */
6023 {
6032 /* Load the relocs. */
6033 internal_relocs
6041 {
6050 /* These are the only relocation types we care about. */
6055 /* Get the section contents if we haven't done so already. */
6057 {
6058 /* Get cached copy if it exists. */
6061 else
6062 {
6063 /* Go get them off disk. */
6066 }
6067 }
6070 {
6076 }
6078 /* If the relocation is not against a symbol it cannot concern us. */
6081 /* We don't care about local symbols. */
6085 /* This is an external symbol. */
6090 /* If the relocation is against a static symbol it must be within
6091 the current section and so cannot be a cross ARM/Thumb relocation. */
6095 /* If the call will go through a PLT entry then we do not need
6096 glue. */
6101 {
6103 /* This one is a call from arm code. We need to look up
6104 the target of the call. If it is a thumb target, we
6105 insert glue. */
6112 }
6113 }
6124 }
6128 error_return:
6137 }
6138 #endif
6141 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6143 void
6145 {
6150 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6160 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6161 should contain the number of local symbols, which should come before any
6162 global symbols. Mapping symbols are always local. */
6164 NULL);
6166 /* No internal symbols read? Skip this BFD. */
6171 {
6178 {
6183 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6185 }
6186 }
6187 }
6190 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6191 say what they wanted. */
6193 void
6195 {
6203 {
6204 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6209 else
6211 }
6212 }
6215 void
6217 {
6223 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6225 {
6227 {
6234 /* Give a warning, but do as the user requests anyway. */
6237 }
6238 }
6240 /* For earlier architectures, we might need the workaround, but do not
6241 enable it by default. If users is running with broken hardware, they
6242 must enable the erratum fix explicitly. */
6244 }
6247 enum bfd_arm_vfp11_pipe
6248 {
6249 VFP11_FMAC,
6250 VFP11_LS,
6251 VFP11_DS,
6252 VFP11_BAD
6253 };
6255 /* Return a VFP register number. This is encoded as RX:X for single-precision
6256 registers, or X:RX for double-precision registers, where RX is the group of
6257 four bits in the instruction encoding and X is the single extension bit.
6258 RX and X fields are specified using their lowest (starting) bit. The return
6259 value is:
6261 0...31: single-precision registers s0...s31
6262 32...63: double-precision registers d0...d31.
6264 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6265 encounter VFP3 instructions, so we allow the full range for DP registers. */
6267 static unsigned int
6270 {
6273 else
6275 }
6277 /* Set bits in *WMASK according to a register number REG as encoded by
6278 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6280 static void
6282 {
6287 }
6289 /* Return TRUE if WMASK overwrites anything in REGS. */
6291 static bfd_boolean
6293 {
6297 {
6310 }
6313 }
6315 /* In this function, we're interested in two things: finding input registers
6316 for VFP data-processing instructions, and finding the set of registers which
6317 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6318 hold the written set, so FLDM etc. are easy to deal with (we're only
6319 interested in 32 SP registers or 16 dp registers, due to the VFP version
6320 implemented by the chip in question). DP registers are marked by setting
6321 both SP registers in the write mask). */
6323 static enum bfd_arm_vfp11_pipe
6326 {
6331 {
6341 {
6363 vfp_binop:
6371 {
6376 {
6390 /* These instructions will not bounce due to underflow. */
6396 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6397 registers to cause the erratum in previous instructions. */
6403 {
6408 /* Only FCVTSD can underflow. */
6415 }
6420 }
6421 }
6426 }
6427 }
6428 /* Two-register transfer. */
6430 {
6434 {
6437 else
6438 {
6441 }
6442 }
6445 }
6447 {
6452 {
6459 {
6467 }
6477 }
6480 }
6481 /* Single-register transfer. Note L==0. */
6483 {
6488 {
6491 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6492 destination register. I don't know if this is exactly right,
6493 but it is the conservative choice. */
6499 }
6502 }
6505 }
6511 /* Look for potentially-troublesome code sequences which might trigger the
6512 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6513 (available from ARM) for details of the erratum. A short version is
6514 described in ld.texinfo. */
6516 bfd_boolean
6518 {
6529 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6530 The states transition as follows:
6532 0 -> 1 (vector) or 0 -> 2 (scalar)
6533 A VFP FMAC-pipeline instruction has been seen. Fill
6534 regs[0]..regs[numregs-1] with its input operands. Remember this
6535 instruction in 'first_fmac'.
6537 1 -> 2
6538 Any instruction, except for a VFP instruction which overwrites
6539 regs[*].
6541 1 -> 3 [ -> 0 ] or
6542 2 -> 3 [ -> 0 ]
6543 A VFP instruction has been seen which overwrites any of regs[*].
6544 We must make a veneer! Reset state to 0 before examining next
6545 instruction.
6547 2 -> 0
6548 If we fail to match anything in state 2, reset to state 0 and reset
6549 the instruction pointer to the instruction after 'first_fmac'.
6551 If the VFP11 vector mode is in use, there must be at least two unrelated
6552 instructions between anti-dependent VFP11 instructions to properly avoid
6553 triggering the erratum, hence the use of the extra state 1. */
6555 /* If we are only performing a partial link do not bother
6556 to construct any glue. */
6560 /* Skip if this bfd does not correspond to an ELF image. */
6564 /* We should have chosen a fix type by the time we get here. */
6570 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6575 {
6579 /* If we don't have executable progbits, we're not interested in this
6580 section. Also skip if section is to be excluded. */
6600 elf32_arm_compare_mapping);
6603 {
6609 /* FIXME: Only ARM mode is supported at present. We may need to
6610 support Thumb-2 mode also at some point. */
6615 {
6630 {
6634 /* I'm assuming the VFP11 erratum can trigger with denorm
6635 operands on either the FMAC or the DS pipeline. This might
6636 lead to slightly overenthusiastic veneer insertion. */
6638 {
6642 }
6646 {
6649 other_regs,
6653 numregs))
6655 else
6657 }
6661 {
6664 other_regs,
6668 numregs))
6670 else
6671 {
6674 }
6675 }
6680 }
6683 {
6692 {
6699 }
6702 first_fmac);
6710 }
6713 }
6714 }
6720 }
6724 error_return:
6730 }
6732 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6733 after sections have been laid out, using specially-named symbols. */
6735 void
6738 {
6746 /* Skip if this bfd does not correspond to an ELF image. */
6758 {
6763 {
6765 bfd_vma vma;
6768 {
6771 /* Find veneer symbol. */
6775 myh = elf_link_hash_lookup
6791 /* Find return location. */
6795 myh = elf_link_hash_lookup
6811 }
6812 }
6813 }
6816 }
6819 /* Set target relocation values needed during linking. */
6821 void
6828 bfd_arm_vfp11_fix vfp11_fix,
6832 {
6846 else
6847 {
6849 target2_type);
6850 }
6861 }
6863 /* Replace the target offset of a Thumb bl or b.w instruction. */
6865 static void
6867 {
6868 bfd_vma upper;
6869 bfd_vma lower;
6886 }
6888 /* Thumb code calling an ARM function. */
6890 static int
6898 bfd_vma offset,
6899 bfd_signed_vma addend,
6900 bfd_vma val,
6902 {
6904 bfd_vma my_offset;
6920 THUMB2ARM_GLUE_SECTION_NAME);
6927 {
6931 {
6938 }
6949 ret_offset =
6950 /* Address of destination of the stub. */
6953 /* Offset from the start of the current section
6954 to the start of the stubs. */
6956 /* Offset of the start of this stub from the start of the stubs. */
6957 + my_offset
6958 /* Address of the start of the current section. */
6960 /* The branch instruction is 4 bytes into the stub. */
6962 /* ARM branches work from the pc of the instruction + 8. */
6968 }
6972 /* Now go back and fix up the original BL insn to point to here. */
6973 ret_offset =
6974 /* Address of where the stub is located. */
6976 /* Address of where the BL is located. */
6979 /* Addend in the relocation. */
6980 - addend
6981 /* Biassing for PC-relative addressing. */
6987 }
6989 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
6997 bfd_vma val,
7000 {
7001 bfd_vma my_offset;
7017 {
7021 {
7026 }
7033 {
7034 /* For relocatable objects we can't use absolute addresses,
7035 so construct the address from a relative offset. */
7036 /* TODO: If the offset is small it's probably worth
7037 constructing the address with adds. */
7044 /* Adjust the offset by 4 for the position of the add,
7045 and 8 for the pipeline offset. */
7052 }
7054 {
7058 /* It's a thumb address. Add the low order bit. */
7061 }
7062 else
7063 {
7070 /* It's a thumb address. Add the low order bit. */
7075 }
7076 }
7081 }
7083 /* Arm code calling a Thumb function. */
7085 static int
7093 bfd_vma offset,
7094 bfd_signed_vma addend,
7095 bfd_vma val,
7097 {
7099 bfd_vma my_offset;
7110 ARM2THUMB_GLUE_SECTION_NAME);
7124 /* Somehow these are both 4 too far, so subtract 8. */
7126 + my_offset
7138 }
7140 /* Populate Arm stub for an exported Thumb function. */
7142 static bfd_boolean
7144 {
7151 bfd_vma val;
7155 /* Allocate stubs for exported Thumb functions on v4t. */
7164 ARM2THUMB_GLUE_SECTION_NAME);
7182 }
7184 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7186 static bfd_vma
7188 {
7190 bfd_vma glue_addr;
7199 ARM_BX_GLUE_SECTION_NAME);
7209 {
7215 }
7218 }
7220 /* Generate Arm stubs for exported Thumb symbols. */
7221 static void
7224 {
7228 /* Ignore this if we are not called by the ELF backend linker. */
7235 /* If blx is available then exported Thumb symbols are OK and there is
7236 nothing to do. */
7241 link_info);
7242 }
7244 /* Reserve space for COUNT dynamic relocations in relocation selection
7245 SRELOC. */
7247 static void
7249 bfd_size_type count)
7250 {
7258 }
7260 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7261 dynamic, the relocations should go in SRELOC, otherwise they should
7262 go in the special .rel.iplt section. */
7264 static void
7266 bfd_size_type count)
7267 {
7273 else
7274 {
7277 }
7278 }
7280 /* Add relocation REL to the end of relocation section SRELOC. */
7282 static void
7285 {
7300 }
7302 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7303 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7304 to .plt. */
7306 static void
7308 bfd_boolean is_iplt_entry,
7311 {
7319 {
7323 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7325 }
7326 else
7327 {
7331 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7334 /* If this is the first .plt entry, make room for the special
7335 first entry. */
7338 }
7340 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7347 {
7348 /* We also need to make an entry in the .got.plt section, which
7349 will be placed in the .got section by the linker script. */
7352 }
7353 }
7355 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7356 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7357 Otherwise, DYNINDX is the index of the symbol in the dynamic
7358 symbol table and SYM_VALUE is undefined.
7360 ROOT_PLT points to the offset of the PLT entry from the start of its
7361 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7362 bookkeeping information. */
7364 static void
7369 {
7375 bfd_vma plt_index;
7376 Elf_Internal_Rela rel;
7377 bfd_vma plt_header_size;
7378 bfd_vma got_header_size;
7382 /* Pick the appropriate sections and sizes. */
7384 {
7389 /* There are no reserved entries in .igot.plt, and no special
7390 first entry in .iplt. */
7393 }
7394 else
7395 {
7402 }
7405 /* Fill in the entry in the procedure linkage table. */
7407 {
7416 /* Fill in the entry in the .rel.plt section. */
7422 /* Get the index in the procedure linkage table which
7423 corresponds to this symbol. This is the index of this symbol
7424 in all the symbols for which we are making plt entries. The
7425 first entry in the procedure linkage table is reserved. */
7428 }
7429 else
7430 {
7437 /* Get the offset into the .(i)got.plt table of the entry that
7438 corresponds to this function. */
7441 /* Get the index in the procedure linkage table which
7442 corresponds to this symbol. This is the index of this symbol
7443 in all the symbols for which we are making plt entries.
7444 After the reserved .got.plt entries, all symbols appear in
7445 the same order as in .plt. */
7448 /* Calculate the address of the GOT entry. */
7453 /* ...and the address of the PLT entry. */
7460 {
7462 bfd_vma val;
7465 {
7473 else
7475 }
7476 }
7478 {
7480 bfd_vma val;
7483 {
7493 else
7495 }
7500 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7501 referencing the GOT for this PLT entry. */
7508 /* Create the R_ARM_ABS32 relocation referencing the
7509 beginning of the PLT for this GOT entry. */
7514 }
7515 else
7516 {
7517 /* Calculate the displacement between the PLT slot and the
7518 entry in the GOT. The eight-byte offset accounts for the
7519 value produced by adding to pc in the first instruction
7520 of the PLT stub. */
7526 {
7531 }
7545 #ifdef FOUR_WORD_PLT
7547 #endif
7548 }
7550 /* Fill in the entry in the .rel(a).(i)plt section. */
7554 {
7555 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7556 The dynamic linker or static executable then calls SYM_VALUE
7557 to determine the correct run-time value of the .igot.plt entry. */
7560 }
7561 else
7562 {
7566 }
7568 /* Fill in the entry in the global offset table. */
7571 }
7575 }
7577 /* Some relocations map to different relocations depending on the
7578 target. Return the real relocation. */
7580 static int
7583 {
7585 {
7589 else
7597 }
7598 }
7600 /* Return the base VMA address which should be subtracted from real addresses
7601 when resolving @dtpoff relocation.
7602 This is PT_TLS segment p_vaddr. */
7604 static bfd_vma
7606 {
7607 /* If tls_sec is NULL, we should have signalled an error already. */
7611 }
7613 /* Return the relocation value for @tpoff relocation
7614 if STT_TLS virtual address is ADDRESS. */
7616 static bfd_vma
7618 {
7620 bfd_vma base;
7622 /* If tls_sec is NULL, we should have signalled an error already. */
7627 }
7629 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7630 VALUE is the relocation value. */
7632 static bfd_reloc_status_type
7634 {
7641 }
7643 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7644 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7645 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7647 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7648 is to then call final_link_relocate. Return other values in the
7649 case of error.
7651 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7652 the pre-relaxed code. It would be nice if the relocs were updated
7653 to match the optimization. */
7655 static bfd_reloc_status_type
7659 {
7663 {
7670 else
7671 {
7675 else
7677 }
7682 /* Thumb insn. */
7685 {
7687 /* nop */
7689 }
7691 {
7693 /* nop */
7695 else
7696 /* ldr rx,[ry] */
7698 }
7700 {
7702 /* nop */
7704 else
7705 /* mov r0, rx */
7708 }
7709 else
7710 {
7712 /* It's a 32 bit instruction, fetch the rest of it for
7713 error generation. */
7720 }
7724 /* arm insn. */
7727 {
7729 /* mov rx, ry */
7732 }
7734 {
7736 /* nop */
7738 else
7739 /* ldr rx,[ry] */
7742 }
7744 {
7746 /* nop */
7748 else
7749 /* mov r0, rx */
7752 }
7753 else
7754 {
7759 }
7763 /* GD->IE relaxation, turn the instruction into 'nop' or
7764 'ldr r0, [pc,r0]' */
7770 /* GD->IE relaxation */
7772 /* add r0,pc; ldr r0, [r0] */
7775 /* nop.w */
7777 else
7778 /* nop; nop */
7784 }
7786 }
7788 /* For a given value of n, calculate the value of G_n as required to
7789 deal with group relocations. We return it in the form of an
7790 encoded constant-and-rotation, together with the final residual. If n is
7791 specified as less than zero, then final_residual is filled with the
7792 input value and no further action is performed. */
7794 static bfd_vma
7796 {
7798 bfd_vma g_n;
7803 {
7806 /* Calculate which part of the value to mask. */
7809 else
7810 {
7813 /* Determine the most significant bit in the residual and
7814 align the resulting value to a 2-bit boundary. */
7819 /* The desired shift is now (msb - 6), or zero, whichever
7820 is the greater. */
7824 }
7826 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
7831 /* Calculate the residual for the next time around. */
7833 }
7838 }
7840 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
7841 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
7843 static int
7845 {
7855 }
7857 /* Perform a relocation as part of a final link. */
7859 static bfd_reloc_status_type
7866 bfd_vma value,
7875 {
7885 bfd_vma addend;
7886 bfd_signed_vma signed_addend;
7888 bfd_vma dynreloc_value;
7893 bfd_vma plt_offset;
7894 bfd_vma gotplt_offset;
7895 bfd_boolean has_iplt_entry;
7903 /* Some relocation types map to different relocations depending on the
7904 target. We pick the right one here. */
7907 /* It is possible to have linker relaxations on some TLS access
7908 models. Update our information here. */
7914 /* If the start address has been set, then set the EF_ARM_HASENTRY
7915 flag. Setting this more than once is redundant, but the cost is
7916 not too high, and it keeps the code simple.
7918 The test is done here, rather than somewhere else, because the
7919 start address is only set just before the final link commences.
7921 Note - if the user deliberately sets a start address of 0, the
7922 flag will not be set. */
7933 else
7939 {
7943 {
7947 }
7948 else
7950 }
7951 else
7954 /* Record the symbol information that should be used in dynamic
7955 relocations. */
7961 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
7962 VALUE appropriately for relocations that we resolve at link time. */
7966 {
7971 {
7975 /* Populate .iplt entries here, because not all of them will
7976 be seen by finish_dynamic_symbol. The lower bit is set if
7977 we have already populated the entry. */
7979 plt_offset--;
7980 else
7981 {
7985 }
7987 /* Static relocations always resolve to the .iplt entry. */
7994 /* If there are non-call relocations that resolve to the .iplt
7995 entry, then all dynamic ones must too. */
7997 {
8000 }
8001 }
8002 else
8003 /* We populate the .plt entry in finish_dynamic_symbol. */
8005 }
8006 else
8007 {
8011 }
8014 {
8016 /* We don't need to find a value for this symbol. It's just a
8017 marker. */
8035 /* Handle relocations which should use the PLT entry. ABS32/REL32
8036 will use the symbol's value, which may point to a PLT entry, but we
8037 don't need to handle that here. If we created a PLT entry, all
8038 branches in this object should go to it, except if the PLT is too
8039 far away, in which case a long branch stub should be inserted. */
8046 {
8047 /* If we've created a .plt section, and assigned a PLT entry
8048 to this function, it must either be a STT_GNU_IFUNC reference
8049 or not be known to bind locally. In other cases, we should
8050 have cleared the PLT entry by now. */
8060 }
8062 /* When generating a shared object or relocatable executable, these
8063 relocations are copied into the output file to be resolved at
8064 run time. */
8081 {
8082 Elf_Internal_Rela outrel;
8088 {
8094 }
8118 else
8119 {
8122 /* This symbol is local, or marked to become local. */
8125 {
8128 /* On Symbian OS, the data segment and text segement
8129 can be relocated independently. Therefore, we
8130 must indicate the segment to which this
8131 relocation is relative. The BPABI allows us to
8132 use any symbol in the right segment; we just use
8133 the section symbol as it is convenient. (We
8134 cannot use the symbol given by "h" directly as it
8135 will not appear in the dynamic symbol table.)
8137 Note that the dynamic linker ignores the section
8138 symbol value, so we don't subtract osec->vma
8139 from the emitted reloc addend. */
8142 else
8146 {
8152 else
8155 }
8157 }
8158 else
8159 /* On SVR4-ish systems, the dynamic loader cannot
8160 relocate the text and data segments independently,
8161 so the symbol does not matter. */
8164 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8165 to the .iplt entry. Instead, every non-call reference
8166 must use an R_ARM_IRELATIVE relocation to obtain the
8167 correct run-time address. */
8169 else
8173 else
8175 }
8179 /* If this reloc is against an external symbol, we do not want to
8180 fiddle with the addend. Otherwise, we need to include the symbol
8181 value so that it becomes an addend for the dynamic reloc. */
8188 }
8190 {
8199 {
8203 {
8204 /* Check for Arm calling Arm function. */
8205 /* FIXME: Should we translate the instruction into a BL
8206 instruction instead ? */
8210 input_bfd,
8212 }
8214 {
8215 /* Check for Arm calling Thumb function. */
8217 {
8222 error_message))
8224 else
8226 }
8227 }
8229 /* Check if a stub has to be inserted because the
8230 destination is too far or we are changing mode. */
8234 {
8245 {
8246 /* The target is out of reach, so redirect the
8247 branch to the local stub for this function. */
8251 stub_type);
8252 {
8260 }
8261 }
8262 else
8263 {
8264 /* If the call goes through a PLT entry, make sure to
8265 check distance to the right destination address. */
8267 {
8272 /* The PLT entry is in ARM mode, regardless of the
8273 target function. */
8275 }
8276 }
8277 }
8279 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8280 where:
8281 S is the address of the symbol in the relocation.
8282 P is address of the instruction being relocated.
8283 A is the addend (extracted from the instruction) in bytes.
8285 S is held in 'value'.
8286 P is the base address of the section containing the
8287 instruction plus the offset of the reloc into that
8288 section, ie:
8289 (input_section->output_section->vma +
8290 input_section->output_offset +
8291 rel->r_offset).
8292 A is the addend, converted into bytes, ie:
8293 (signed_addend * 4)
8295 Note: None of these operations have knowledge of the pipeline
8296 size of the processor, thus it is up to the assembler to
8297 encode this information into the addend. */
8303 else
8304 /* RELA addends do not have to be adjusted by howto->size. */
8310 /* A branch to an undefined weak symbol is turned into a jump to
8311 the next instruction unless a PLT entry will be created.
8312 Do the same for local undefined symbols (but not for STN_UNDEF).
8313 The jump to the next instruction is optimized as a NOP depending
8314 on the architecture. */
8318 {
8323 else
8325 }
8326 else
8327 {
8328 /* Perform a signed range check. */
8339 {
8340 /* Set the H bit in the BLX instruction. */
8342 {
8345 else
8347 }
8349 /* Select the correct instruction (BL or BLX). */
8350 /* Only if we are not handling a BL to a stub. In this
8351 case, mode switching is performed by the stub. */
8355 {
8358 }
8359 }
8360 }
8361 }
8393 {
8394 /* Check for overflow. */
8397 }
8403 }
8411 /* There is no way to tell whether the user intended to use a signed or
8412 unsigned addend. When checking for overflow we accept either,
8413 as specified by the AAELF. */
8423 /* See comment for R_ARM_ABS8. */
8431 /* Support ldr and str instructions for the thumb. */
8433 {
8434 /* Need to refetch addend. */
8436 /* ??? Need to determine shift amount from operand size. */
8438 }
8441 /* ??? Isn't value unsigned? */
8445 /* ??? Value needs to be properly shifted into place first. */
8451 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8452 {
8453 bfd_vma insn;
8454 bfd_signed_vma relocation;
8460 {
8465 }
8487 }
8490 /* PR 10073: This reloc is not generated by the GNU toolchain,
8491 but it is supported for compatibility with third party libraries
8492 generated by other compilers, specifically the ARM/IAR. */
8493 {
8494 bfd_vma insn;
8495 bfd_signed_vma relocation;
8509 /* We do not check for overflow of this reloc. Although strictly
8510 speaking this is incorrect, it appears to be necessary in order
8511 to work with IAR generated relocs. Since GCC and GAS do not
8512 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8513 a problem for them. */
8521 }
8524 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8525 {
8526 bfd_vma insn;
8527 bfd_signed_vma relocation;
8533 {
8537 }
8557 }
8562 /* Thumb BL (branch long instruction). */
8563 {
8564 bfd_vma relocation;
8565 bfd_vma reloc_sign;
8569 bfd_signed_vma reloc_signed_max;
8570 bfd_signed_vma reloc_signed_min;
8571 bfd_vma check;
8572 bfd_signed_vma signed_check;
8576 /* A branch to an undefined weak symbol is turned into a jump to
8577 the next instruction unless a PLT entry will be created.
8578 The jump to the next instruction is optimized as a NOP.W for
8579 Thumb-2 enabled architectures. */
8582 {
8584 {
8587 }
8588 else
8589 {
8592 }
8594 }
8596 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8597 with Thumb-1) involving the J1 and J2 bits. */
8599 {
8609 /* Sign extend. */
8613 }
8616 {
8617 /* Check for Thumb to Thumb call. */
8618 /* FIXME: Should we translate the instruction into a BL
8619 instruction instead ? */
8623 input_bfd,
8625 }
8626 else
8627 {
8628 /* If it is not a call to Thumb, assume call to Arm.
8629 If it is a call relative to a section name, then it is not a
8630 function call at all, but rather a long jump. Calls through
8631 the PLT do not require stubs. */
8633 {
8635 {
8636 /* Convert BL to BLX. */
8638 }
8641 {
8645 error_message))
8647 else
8649 }
8650 }
8654 {
8655 /* Make sure this is a BL. */
8657 }
8658 }
8662 {
8663 /* Check if a stub has to be inserted because the destination
8664 is too far. */
8676 {
8677 /* The target is out of reach or we are changing modes, so
8678 redirect the branch to the local stub for this
8679 function. */
8683 stub_type);
8685 {
8692 }
8694 /* If this call becomes a call to Arm, force BLX. */
8696 {
8701 }
8702 }
8703 }
8705 /* Handle calls via the PLT. */
8707 {
8713 {
8714 /* If the Thumb BLX instruction is available, convert
8715 the BL to a BLX instruction to call the ARM-mode
8716 PLT entry. */
8719 }
8720 else
8721 {
8722 /* Target the Thumb stub before the ARM PLT entry. */
8725 }
8727 }
8737 /* If this is a signed value, the rightshift just dropped
8738 leading 1 bits (assuming twos complement). */
8741 else
8744 /* Calculate the permissable maximum and minimum values for
8745 this relocation according to whether we're relocating for
8746 Thumb-2 or not. */
8753 /* Assumes two's complement. */
8758 /* For a BLX instruction, make sure that the relocation is rounded up
8759 to a word boundary. This follows the semantics of the instruction
8760 which specifies that bit 1 of the target address will come from bit
8761 1 of the base address. */
8764 /* Put RELOCATION back into the insn. Assumes two's complement.
8765 We use the Thumb-2 encoding, which is safe even if dealing with
8766 a Thumb-1 instruction by virtue of our overflow check above. */
8776 /* Put the relocated value back in the object file: */
8781 }
8785 /* Thumb32 conditional branch instruction. */
8786 {
8787 bfd_vma relocation;
8793 bfd_signed_vma signed_check;
8795 /* Need to refetch the addend, reconstruct the top three bits,
8796 and squish the two 11 bit pieces together. */
8798 {
8812 }
8814 /* Handle calls via the PLT. */
8816 {
8820 /* Target the Thumb stub before the ARM PLT entry. */
8823 }
8825 /* ??? Should handle interworking? GCC might someday try to
8826 use this for tail calls. */
8837 /* Put RELOCATION back into the insn. */
8838 {
8847 }
8849 /* Put the relocated value back in the object file: */
8854 }
8859 /* Thumb B (branch) instruction). */
8860 {
8861 bfd_signed_vma relocation;
8864 bfd_signed_vma signed_check;
8866 /* CZB cannot jump backward. */
8871 {
8872 /* Need to refetch addend. */
8875 {
8879 }
8880 else
8882 /* The value in the insn has been right shifted. We need to
8883 undo this, so that we can perform the address calculation
8884 in terms of bytes. */
8886 }
8898 else
8904 /* Assumes two's complement. */
8909 }
8914 {
8915 bfd_vma insn;
8916 bfd_vma relocation;
8920 {
8921 /* Extract the addend. */
8924 }
8934 }
8942 /* Relocation is relative to the start of the
8943 global offset table. */
8949 /* If we are addressing a Thumb function, we need to adjust the
8950 address by one, so that attempts to call the function pointer will
8951 correctly interpret it as Thumb code. */
8955 /* Note that sgot->output_offset is not involved in this
8956 calculation. We always want the start of .got. If we
8957 define _GLOBAL_OFFSET_TABLE in a different way, as is
8958 permitted by the ABI, we might have to change this
8959 calculation. */
8966 /* Use global offset table as symbol value. */
8980 /* Relocation is to the entry for this symbol in the
8981 global offset table. */
8988 {
8989 /* We have a relocation against a locally-binding STT_GNU_IFUNC
8990 symbol, and the relocation resolves directly to the runtime
8991 target rather than to the .iplt entry. This means that any
8992 .got entry would be the same value as the .igot.plt entry,
8993 so there's no point creating both. */
8996 }
8998 {
8999 bfd_vma off;
9004 {
9005 /* We have already processsed one GOT relocation against
9006 this symbol. */
9011 }
9012 else
9013 {
9014 Elf_Internal_Rela outrel;
9017 {
9018 /* If the symbol doesn't resolve locally in a static
9019 object, we have an undefined reference. If the
9020 symbol doesn't resolve locally in a dynamic object,
9021 it should be resolved by the dynamic linker. */
9023 {
9026 }
9027 else
9030 }
9031 else
9032 {
9037 else
9040 }
9042 /* The GOT entry is initialized to zero by default.
9043 See if we should install a different value. */
9046 {
9050 }
9053 {
9058 }
9060 }
9062 }
9063 else
9064 {
9065 bfd_vma off;
9072 /* The offset must always be a multiple of 4. We use the
9073 least significant bit to record whether we have already
9074 generated the necessary reloc. */
9077 else
9078 {
9083 {
9084 Elf_Internal_Rela outrel;
9092 else
9095 }
9098 }
9101 }
9117 {
9118 bfd_vma off;
9127 else
9128 {
9129 /* If we don't know the module number, create a relocation
9130 for it. */
9132 {
9133 Elf_Internal_Rela outrel;
9148 }
9149 else
9153 }
9161 }
9170 {
9178 {
9179 bfd_boolean dyn;
9184 {
9187 }
9191 }
9192 else
9193 {
9198 }
9200 /* Linker relaxations happens from one of the
9201 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9209 else
9210 {
9212 Elf_Internal_Rela outrel;
9215 /* The GOT entries have not been initialized yet. Do it
9216 now, and emit any relocations. If both an IE GOT and a
9217 GD GOT are necessary, we emit the GD first. */
9223 {
9226 }
9229 {
9232 /* We should have relaxed, unless this is an undefined
9233 weak symbol. */
9242 + offplt
9254 /* For globals, the first word in the relocation gets
9255 the relocation index and the top bit set, or zero,
9256 if we're binding now. For locals, it gets the
9257 symbol's offset in the tls section. */
9265 /* Second word in the relocation is always zero. */
9269 }
9271 {
9273 {
9289 else
9290 {
9293 R_ARM_TLS_DTPOFF32);
9302 }
9303 }
9304 else
9305 {
9306 /* If we are not emitting relocations for a
9307 general dynamic reference, then we must be in a
9308 static link or an executable link with the
9309 symbol binding locally. Mark it as belonging
9310 to module 1, the executable. */
9315 }
9318 }
9321 {
9323 {
9326 else
9338 }
9339 else
9343 }
9347 else
9349 }
9358 {
9359 bfd_signed_vma offset;
9360 /* TLS stubs are arm mode. The original symbol is a
9361 data object, so branch_type is bogus. */
9363 enum elf32_arm_stub_type stub_type
9371 {
9373 = elf32_arm_get_stub_entry
9379 }
9380 else
9386 {
9395 }
9396 else
9397 {
9398 /* Thumb blx encodes the offset in a complicated
9399 fashion. */
9404 input_section->output_offset
9409 {
9411 }
9412 else
9413 {
9415 /* Round up the offset to a word boundary */
9417 }
9429 }
9430 }
9431 /* These relocations needs special care, as besides the fact
9432 they point somewhere in .gotplt, the addend must be
9433 adjusted accordingly depending on the type of instruction
9434 we refer to */
9436 {
9445 {
9452 /* bl/blx */
9455 /* add */
9457 else
9458 {
9464 }
9465 }
9466 else
9467 {
9471 {
9487 }
9488 }
9496 }
9497 else
9506 }
9510 {
9516 }
9517 else
9526 {
9529 /* Ensure that we have a BX instruction. */
9533 {
9534 /* Branch to veneer. */
9535 bfd_vma glue_addr;
9542 }
9543 else
9544 {
9545 /* Preserve Rm (lowest four bits) and the condition code
9546 (highest four bits). Other bits encode MOV PC,Rm. */
9548 }
9551 }
9558 /* Until we properly support segment-base-relative addressing then
9559 we assume the segment base to be zero, as for the group relocations.
9560 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9561 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9565 {
9569 {
9572 }
9594 }
9601 /* Until we properly support segment-base-relative addressing then
9602 we assume the segment base to be zero, as for the above relocations.
9603 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9604 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9605 as R_ARM_THM_MOVT_ABS. */
9609 {
9610 bfd_vma insn;
9616 {
9622 }
9648 }
9661 {
9665 /* sb should be the origin of the *segment* containing the symbol.
9666 It is not clear how to obtain this OS-dependent value, so we
9667 make an arbitrary choice of zero. */
9669 bfd_vma residual;
9670 bfd_vma g_n;
9671 bfd_signed_vma signed_value;
9674 /* Determine which group of bits to select. */
9676 {
9698 }
9700 /* If REL, extract the addend from the insn. If RELA, it will
9701 have already been fetched for us. */
9703 {
9710 else
9711 {
9712 /* Compensate for the fact that in the instruction, the
9713 rotation is stored in multiples of 2 bits. */
9716 /* Rotate "constant" right by "rotation" bits. */
9719 }
9721 /* Determine if the instruction is an ADD or a SUB.
9722 (For REL, this determines the sign of the addend.) */
9725 {
9731 }
9734 }
9736 /* Compute the value (X) to go in the place. */
9742 /* PC relative. */
9744 else
9745 /* Section base relative. */
9748 /* If the target symbol is a Thumb function, then set the
9749 Thumb bit in the address. */
9753 /* Calculate the value of the relevant G_n, in encoded
9754 constant-with-rotation format. */
9758 /* Check for overflow if required. */
9765 {
9771 }
9773 /* Mask out the value and the ADD/SUB part of the opcode; take care
9774 not to destroy the S bit. */
9777 /* Set the opcode according to whether the value to go in the
9778 place is negative. */
9781 else
9784 /* Encode the offset. */
9788 }
9797 {
9802 bfd_vma residual;
9803 bfd_signed_vma signed_value;
9806 /* Determine which groups of bits to calculate. */
9808 {
9826 }
9828 /* If REL, extract the addend from the insn. If RELA, it will
9829 have already been fetched for us. */
9831 {
9834 }
9836 /* Compute the value (X) to go in the place. */
9840 /* PC relative. */
9842 else
9843 /* Section base relative. */
9846 /* Calculate the value of the relevant G_{n-1} to obtain
9847 the residual at that stage. */
9850 /* Check for overflow. */
9852 {
9858 }
9860 /* Mask out the value and U bit. */
9863 /* Set the U bit if the value to go in the place is non-negative. */
9867 /* Encode the offset. */
9871 }
9880 {
9885 bfd_vma residual;
9886 bfd_signed_vma signed_value;
9889 /* Determine which groups of bits to calculate. */
9891 {
9909 }
9911 /* If REL, extract the addend from the insn. If RELA, it will
9912 have already been fetched for us. */
9914 {
9917 }
9919 /* Compute the value (X) to go in the place. */
9923 /* PC relative. */
9925 else
9926 /* Section base relative. */
9929 /* Calculate the value of the relevant G_{n-1} to obtain
9930 the residual at that stage. */
9933 /* Check for overflow. */
9935 {
9941 }
9943 /* Mask out the value and U bit. */
9946 /* Set the U bit if the value to go in the place is non-negative. */
9950 /* Encode the offset. */
9954 }
9963 {
9968 bfd_vma residual;
9969 bfd_signed_vma signed_value;
9972 /* Determine which groups of bits to calculate. */
9974 {
9992 }
9994 /* If REL, extract the addend from the insn. If RELA, it will
9995 have already been fetched for us. */
9997 {
10000 }
10002 /* Compute the value (X) to go in the place. */
10006 /* PC relative. */
10008 else
10009 /* Section base relative. */
10012 /* Calculate the value of the relevant G_{n-1} to obtain
10013 the residual at that stage. */
10016 /* Check for overflow. (The absolute value to go in the place must be
10017 divisible by four and, after having been divided by four, must
10018 fit in eight bits.) */
10020 {
10026 }
10028 /* Mask out the value and U bit. */
10031 /* Set the U bit if the value to go in the place is non-negative. */
10035 /* Encode the offset. */
10039 }
10044 }
10045 }
10047 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
10048 static void
10052 bfd_signed_vma increment)
10053 {
10054 bfd_signed_vma addend;
10058 {
10076 }
10077 else
10078 {
10079 bfd_vma contents;
10083 /* Get the (signed) value from the instruction. */
10086 {
10087 bfd_signed_vma mask;
10092 }
10094 /* Add in the increment, (which is a byte value). */
10096 {
10108 /* Should we check for overflow here ? */
10110 /* Drop any undesired bits. */
10113 }
10118 }
10119 }
10121 #define IS_ARM_TLS_RELOC(R_TYPE) \
10122 ((R_TYPE) == R_ARM_TLS_GD32 \
10123 || (R_TYPE) == R_ARM_TLS_LDO32 \
10124 || (R_TYPE) == R_ARM_TLS_LDM32 \
10125 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10126 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10127 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10128 || (R_TYPE) == R_ARM_TLS_LE32 \
10129 || (R_TYPE) == R_ARM_TLS_IE32 \
10130 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10132 /* Specific set of relocations for the gnu tls dialect. */
10133 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10134 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10135 || (R_TYPE) == R_ARM_TLS_CALL \
10136 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10137 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10138 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10140 /* Relocate an ARM ELF section. */
10142 static bfd_boolean
10151 {
10169 {
10176 bfd_vma relocation;
10177 bfd_reloc_status_type r;
10178 arelent bfd_reloc;
10199 {
10204 /* An object file might have a reference to a local
10205 undefined symbol. This is a daft object file, but we
10206 should at least do something about it. V4BX & NONE
10207 relocations do not use the symbol and are explicitly
10208 allowed to use the undefined symbol, so allow those.
10209 Likewise for relocations against STN_UNDEF. */
10215 {
10222 }
10225 {
10232 {
10237 {
10259 {
10265 }
10269 /* Get the (signed) value from the instruction. */
10272 {
10273 bfd_signed_vma mask;
10278 }
10280 }
10283 addend =
10288 /* Cases here must match those in the preceding
10289 switch statement. */
10291 {
10314 }
10315 }
10316 }
10317 else
10319 }
10320 else
10321 {
10322 bfd_boolean warned;
10330 }
10337 {
10338 /* This is a relocatable link. We don't have to change
10339 anything, unless the reloc is against a section symbol,
10340 in which case we have to adjust according to where the
10341 section symbol winds up in the output section. */
10343 {
10347 else
10349 }
10351 }
10355 else
10356 {
10357 name = (bfd_elf_string_from_elf_section
10361 }
10369 {
10374 input_bfd,
10375 input_section,
10378 name);
10379 }
10381 /* We call elf32_arm_final_link_relocate unless we're completely
10382 done, i.e., the relaxation produced the final output we want,
10383 and we won't let anybody mess with it. Also, we have to do
10384 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10385 both in relaxed and non-relaxed cases */
10391 {
10394 /* This may have been marked unresolved because it came from
10395 a shared library. But we've just dealt with that. */
10397 }
10398 else
10409 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10410 because such sections are not SEC_ALLOC and thus ld.so will
10411 not process them. */
10417 {
10420 input_bfd,
10421 input_section,
10426 }
10429 {
10431 {
10433 /* If the overflowing reloc was to an undefined symbol,
10434 we have already printed one error message and there
10435 is no point complaining again. */
10461 /* error_message should already be set. */
10466 /* Fall through. */
10468 common_error:
10475 }
10476 }
10477 }
10480 }
10482 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10483 adds the edit to the start of the list. (The list must be built in order of
10484 ascending TINDEX: the function's callers are primarily responsible for
10485 maintaining that condition). */
10487 static void
10490 arm_unwind_edit_type type,
10493 {
10502 {
10512 }
10513 else
10514 {
10521 }
10522 }
10526 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10527 static void
10529 {
10537 /* Adjust size of output section. */
10539 }
10541 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10542 static void
10544 {
10554 }
10556 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10557 made to those tables, such that:
10559 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10560 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10561 codes which have been inlined into the index).
10563 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10565 The edits are applied when the tables are written
10566 (in elf32_arm_write_section).
10567 */
10569 bfd_boolean
10573 bfd_boolean merge_exidx_entries)
10574 {
10581 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10582 text sections. */
10584 {
10588 {
10596 {
10597 Elf_Internal_Shdr *linked_hdr
10605 /* Link this .ARM.exidx section back from the text section it
10606 describes. */
10608 }
10609 }
10610 }
10612 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10613 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10614 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10617 {
10624 bfd_vma j;
10635 {
10636 /* Section has no unwind data. */
10640 /* Ignore zero sized sections. */
10647 }
10649 /* Skip /DISCARD/ sections. */
10666 /* An error? */
10670 {
10675 /* An EXIDX_CANTUNWIND entry. */
10677 {
10681 }
10682 /* Inlined unwinding data. Merge if equal to previous. */
10684 {
10690 }
10691 /* Normal table entry. In theory we could merge these too,
10692 but duplicate entries are likely to be much less common. */
10693 else
10697 {
10702 }
10705 }
10707 /* Free contents if we allocated it ourselves. */
10711 /* Record edits to be applied later (in elf32_arm_write_section). */
10720 }
10722 /* Add terminating CANTUNWIND entry. */
10727 }
10729 static bfd_boolean
10732 {
10748 }
10750 static bfd_boolean
10752 {
10759 /* Invoke the regular ELF backend linker to do all the work. */
10763 /* Process stub sections (eg BE8 encoding, ...). */
10767 {
10769 /* Only process it once, in its link_sec slot. */
10771 {
10777 }
10778 }
10780 /* Write out any glue sections now that we have created all the
10781 stubs. */
10783 {
10786 ARM2THUMB_GLUE_SECTION_NAME))
10791 THUMB2ARM_GLUE_SECTION_NAME))
10796 VFP11_ERRATUM_VENEER_SECTION_NAME))
10801 ARM_BX_GLUE_SECTION_NAME))
10803 }
10806 }
10808 /* Set the right machine number. */
10810 static bfd_boolean
10812 {
10823 else
10827 }
10829 /* Function to keep ARM specific flags in the ELF header. */
10831 static bfd_boolean
10833 {
10836 {
10838 {
10841 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
10842 abfd);
10843 else
10844 _bfd_error_handler
10846 abfd);
10847 }
10848 }
10849 else
10850 {
10853 }
10856 }
10858 /* Copy backend specific data from one object module to another. */
10860 static bfd_boolean
10862 {
10863 flagword in_flags;
10864 flagword out_flags;
10875 {
10876 /* Cannot mix APCS26 and APCS32 code. */
10880 /* Cannot mix float APCS and non-float APCS code. */
10884 /* If the src and dest have different interworking flags
10885 then turn off the interworking bit. */
10887 {
10889 _bfd_error_handler
10890 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
10894 }
10896 /* Likewise for PIC, though don't warn for this case. */
10899 }
10904 /* Also copy the EI_OSABI field. */
10908 /* Copy object attributes. */
10912 }
10914 /* Values for Tag_ABI_PCS_R9_use. */
10915 enum
10916 {
10917 AEABI_R9_V6,
10918 AEABI_R9_SB,
10919 AEABI_R9_TLS,
10920 AEABI_R9_unused
10921 };
10923 /* Values for Tag_ABI_PCS_RW_data. */
10924 enum
10925 {
10926 AEABI_PCS_RW_data_absolute,
10927 AEABI_PCS_RW_data_PCrel,
10928 AEABI_PCS_RW_data_SBrel,
10929 AEABI_PCS_RW_data_unused
10930 };
10932 /* Values for Tag_ABI_enum_size. */
10933 enum
10934 {
10935 AEABI_enum_unused,
10936 AEABI_enum_short,
10937 AEABI_enum_wide,
10938 AEABI_enum_forced_wide
10939 };
10941 /* Determine whether an object attribute tag takes an integer, a
10942 string or both. */
10944 static int
10946 {
10955 else
10957 }
10959 /* The ABI defines that Tag_conformance should be emitted first, and that
10960 Tag_nodefaults should be second (if either is defined). This sets those
10961 two positions, and bumps up the position of all the remaining tags to
10962 compensate. */
10963 static int
10965 {
10975 }
10977 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
10978 static bfd_boolean
10980 {
10982 {
10983 _bfd_error_handler
10988 }
10989 else
10990 {
10991 _bfd_error_handler
10995 }
10996 }
10998 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
10999 Returns -1 if no architecture could be read. */
11001 static int
11003 {
11007 /* Note: the tag and its argument below are uleb128 values, though
11008 currently-defined values fit in one byte for each. */
11015 /* This tag is "safely ignorable", so don't complain if it looks funny. */
11017 }
11019 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
11020 The tag is removed if ARCH is -1. */
11022 static void
11024 {
11029 {
11032 }
11034 /* Note: the tag and its argument below are uleb128 values, though
11035 currently-defined values fit in one byte for each. */
11041 }
11043 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
11044 into account. */
11046 static int
11049 {
11050 #define T(X) TAG_CPU_ARCH_##X
11053 {
11063 };
11065 {
11076 };
11078 {
11090 };
11092 {
11105 };
11107 {
11121 };
11123 {
11138 };
11140 {
11156 };
11158 {
11159 v6t2,
11160 v6k,
11161 v7,
11162 v6_m,
11163 v6s_m,
11164 v7e_m,
11165 /* Pseudo-architecture. */
11166 v4t_plus_v6_m
11167 };
11169 /* Check we've not got a higher architecture than we know about. */
11172 {
11175 }
11177 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11183 /* And override the new tag if we have a Tag_also_compatible_with on the
11184 input. */
11193 /* Architectures before V6KZ add features monotonically. */
11199 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11200 as the canonical version. */
11202 {
11205 }
11206 else
11210 {
11214 }
11217 #undef T
11218 }
11220 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11221 are conflicting attributes. */
11223 static bfd_boolean
11225 {
11228 /* Some tags have 0 = don't care, 1 = strong requirement,
11229 2 = weak requirement. */
11234 /* Skip the linker stubs file. This preserves previous behavior
11235 of accepting unknown attributes in the first input file - but
11236 is that a bug? */
11241 {
11242 /* This is the first object. Copy the attributes. */
11247 /* Use the Tag_null value to indicate the attributes have been
11248 initialized. */
11251 /* We do not output objects with Tag_MPextension_use_legacy - we move
11252 the attribute's value to Tag_MPextension_use. */
11254 {
11258 {
11259 _bfd_error_handler
11263 }
11269 }
11272 }
11276 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11278 {
11279 /* Ignore mismatches if the object doesn't use floating point. */
11283 {
11284 _bfd_error_handler
11289 }
11290 }
11293 {
11294 /* Merge this attribute with existing attributes. */
11296 {
11299 /* These are merged after Tag_CPU_arch. */
11304 /* Use the first value seen. */
11308 {
11312 /* These aren't real CPU names, but we can't guess
11313 that from the architecture version alone. */
11326 "ARM v6S-M"
11327 };
11329 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11335 secondary_compat);
11338 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11342 {
11343 /* The output architecture has been changed to match the
11344 input architecture. Use the input names. */
11351 }
11352 else
11353 {
11356 }
11358 /* If we still don't have a value for Tag_CPU_name,
11359 make one up now. Tag_CPU_raw_name remains blank. */
11364 }
11371 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11380 /* Use the largest value specified. */
11387 /* Use the smallest value specified. */
11396 {
11397 /* This error message should be enabled once all non-conformant
11398 binaries in the toolchain have had the attributes set
11399 properly.
11400 _bfd_error_handler
11401 (_("error: %B: 8-byte data alignment conflicts with %B"),
11402 obfd, ibfd);
11403 result = FALSE; */
11404 }
11405 /* Fall through. */
11408 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11409 value if greater than 2 (for future-proofing). */
11417 /* The virtualization tag effectively stores two bits of
11418 information: the intended use of TrustZone (in bit 0), and the
11419 intended use of Virtualization (in bit 1). */
11424 {
11427 else
11428 {
11429 _bfd_error_handler
11434 }
11435 }
11440 {
11441 /* 0 will merge with anything.
11442 'A' and 'S' merge to 'A'.
11443 'R' and 'S' merge to 'R'.
11444 'M' and 'A|R|S' is an error. */
11453 else
11454 {
11455 _bfd_error_handler
11457 ibfd,
11461 }
11462 }
11465 {
11466 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11467 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11468 when it's 0. It might mean absence of FP hardware if
11469 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11471 static const struct
11472 {
11476 {
11484 };
11489 /* If the output has no requirement about FP hardware,
11490 follow the requirement of the input. */
11492 {
11498 }
11499 /* If the input has no requirement about FP hardware, do
11500 nothing. */
11502 {
11505 }
11507 /* Both the input and the output have nonzero Tag_FP_arch.
11508 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11510 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11511 do nothing. */
11514 ;
11515 /* If the input and the output have different Tag_ABI_HardFP_use,
11516 the combination of them is 3 (SP & DP). */
11521 /* Now we can handle Tag_FP_arch. */
11523 /* Values greater than 6 aren't defined, so just pick the
11524 biggest */
11526 {
11529 }
11530 /* The output uses the superset of input features
11531 (ISA version) and registers. */
11538 /* This assumes all possible supersets are also a valid
11539 options. */
11541 {
11545 }
11547 }
11553 {
11554 /* It's sometimes ok to mix different configs, so this is only
11555 a warning. */
11556 _bfd_error_handler
11558 }
11564 {
11565 _bfd_error_handler
11568 }
11576 {
11577 _bfd_error_handler
11579 ibfd);
11581 }
11582 /* Use the smallest value specified. */
11589 {
11590 _bfd_error_handler
11591 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
11593 }
11599 {
11602 {
11603 /* The existing object is compatible with anything.
11604 Use whatever requirements the new object has. */
11606 }
11610 {
11621 _bfd_error_handler
11622 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
11624 }
11625 }
11628 /* Aready done. */
11632 {
11633 _bfd_error_handler
11637 }
11640 /* Merged in target-independent code. */
11643 /* This is handled along with Tag_FP_arch. */
11647 {
11649 {
11650 _bfd_error_handler
11654 }
11655 }
11661 /* This tag is set to zero if we can use UDIV and SDIV in Thumb
11662 mode on a v7-M or v7-R CPU; to one if we can not use UDIV or
11663 SDIV at all; and to two if we can use UDIV or SDIV on a v7-A
11664 CPU. We will merge as follows: If the input attribute's value
11665 is one then the output attribute's value remains unchanged. If
11666 the input attribute's value is zero or two then if the output
11667 attribute's value is one the output value is set to the input
11668 value, otherwise the output value must be the same as the
11669 inputs. */
11671 {
11673 {
11674 _bfd_error_handler
11678 }
11679 }
11687 /* We don't output objects with Tag_MPextension_use_legacy - we
11688 move the value to Tag_MPextension_use. */
11690 {
11692 {
11693 _bfd_error_handler
11696 ibfd);
11698 }
11699 }
11707 /* This tag is set if it exists, but the value is unused (and is
11708 typically zero). We don't actually need to do anything here -
11709 the merge happens automatically when the type flags are merged
11710 below. */
11713 /* Already done in Tag_CPU_arch. */
11716 /* Keep the attribute if it matches. Throw it away otherwise.
11717 No attribute means no claim to conform. */
11724 result
11726 }
11728 /* If out_attr was copied from in_attr then it won't have a type yet. */
11731 }
11733 /* Merge Tag_compatibility attributes and any common GNU ones. */
11737 /* Check for any attributes not known on ARM. */
11741 }
11744 /* Return TRUE if the two EABI versions are incompatible. */
11746 static bfd_boolean
11748 {
11749 /* v4 and v5 are the same spec before and after it was released,
11750 so allow mixing them. */
11756 }
11758 /* Merge backend specific data from an object file to the output
11759 object file when linking. */
11761 static bfd_boolean
11764 /* Display the flags field. */
11766 static bfd_boolean
11768 {
11774 /* Print normal ELF private data. */
11778 /* Ignore init flag - it may not be set, despite the flags field
11779 containing valid data. */
11781 /* xgettext:c-format */
11785 {
11787 /* The following flag bits are GNU extensions and not part of the
11788 official ARM ELF extended ABI. Hence they are only decoded if
11789 the EABI version is not set. */
11795 else
11802 else
11831 else
11842 else
11865 eabi:
11878 }
11896 }
11898 static int
11900 {
11902 {
11907 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
11908 This allows us to distinguish between data used by Thumb instructions
11909 and non-data (which is probably code) inside Thumb regions of an
11910 executable. */
11917 }
11920 }
11928 {
11931 {
11935 }
11938 }
11940 /* Update the got entry reference counts for the section being removed. */
11942 static bfd_boolean
11947 {
11971 {
11976 bfd_boolean call_reloc_p;
11977 bfd_boolean may_become_dynamic_p;
11978 bfd_boolean may_need_local_target_p;
11984 {
11989 }
11999 {
12005 {
12008 }
12010 {
12013 }
12034 {
12037 }
12038 /* Fall through. */
12051 /* Should the interworking branches be here also? */
12054 {
12057 {
12060 }
12061 else
12063 }
12064 else
12070 }
12074 {
12087 }
12090 {
12096 else
12097 {
12107 }
12110 {
12111 /* Everything must go for SEC. */
12114 }
12115 }
12116 }
12119 }
12121 /* Look through the relocs for a section during the first phase. */
12123 static bfd_boolean
12126 {
12134 bfd_boolean call_reloc_p;
12135 bfd_boolean may_become_dynamic_p;
12136 bfd_boolean may_need_local_target_p;
12150 /* Create dynamic sections for relocatable executables so that we can
12151 copy relocations. */
12154 {
12157 }
12172 {
12184 /* PR 9934: It is possible to have relocations that do not
12185 refer to symbols, thus it is also possible to have an
12186 object file containing relocations but no symbol table. */
12188 {
12190 r_symndx);
12192 }
12197 {
12199 {
12200 /* A local symbol. */
12205 }
12206 else
12207 {
12212 }
12213 }
12221 /* Could be done earlier, if h were already available. */
12224 {
12234 /* This symbol requires a global offset table entry. */
12235 {
12239 {
12250 }
12253 {
12256 }
12257 else
12258 {
12259 /* This is a global offset table entry for a local symbol. */
12264 }
12266 /* If a variable is accessed with both tls methods, two
12267 slots may be created. */
12272 /* We will already have issued an error message if there
12273 is a TLS/non-TLS mismatch, based on the symbol
12274 type. So just combine any TLS types needed. */
12279 /* If the symbol is accessed in both IE and GDESC
12280 method, we're able to relax. Turn off the GDESC flag,
12281 without messing up with any other kind of tls types
12282 that may be involved */
12287 {
12290 else
12292 }
12293 }
12294 /* Fall through. */
12299 /* Fall through. */
12321 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12322 ldr __GOTT_INDEX__ offsets. */
12324 {
12327 }
12328 /* Fall through. */
12335 {
12337 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12342 }
12344 /* Fall through. */
12354 /* Should the interworking branches be listed here? */
12357 {
12360 {
12361 /* In shared libraries and relocatable executables,
12362 we treat local relative references as calls;
12363 see the related SYMBOL_CALLS_LOCAL code in
12364 allocate_dynrelocs. */
12367 }
12368 else
12369 /* We are creating a shared library or relocatable
12370 executable, and this is a reloc against a global symbol,
12371 or a non-PC-relative reloc against a local symbol.
12372 We may need to copy the reloc into the output. */
12374 }
12375 else
12379 /* This relocation describes the C++ object vtable hierarchy.
12380 Reconstruct it for later use during GC. */
12386 /* This relocation describes which C++ vtable entries are actually
12387 used. Record for later use during GC. */
12394 }
12397 {
12399 /* We may need a .plt entry if the function this reloc
12400 refers to is in a different object, regardless of the
12401 symbol's type. We can't tell for sure yet, because
12402 something later might force the symbol local. */
12405 /* If this reloc is in a read-only section, we might
12406 need a copy reloc. We can't check reliably at this
12407 stage whether the section is read-only, as input
12408 sections have not yet been mapped to output sections.
12409 Tentatively set the flag for now, and correct in
12410 adjust_dynamic_symbol. */
12412 }
12416 {
12422 {
12425 }
12426 else
12427 {
12433 }
12435 /* If the symbol is a function that doesn't bind locally,
12436 this relocation will need a PLT entry. */
12442 /* It's too early to use htab->use_blx here, so we have to
12443 record possible blx references separately from
12444 relocs that definitely need a thumb stub. */
12452 }
12455 {
12458 /* Create a reloc section in dynobj. */
12460 {
12461 sreloc = _bfd_elf_make_dynamic_reloc_section
12467 /* BPABI objects never have dynamic relocations mapped. */
12469 {
12470 flagword flags;
12475 }
12476 }
12478 /* If this is a global symbol, count the number of
12479 relocations we need for this symbol. */
12482 else
12483 {
12487 }
12491 {
12502 }
12507 }
12508 }
12511 }
12513 /* Unwinding tables are not referenced directly. This pass marks them as
12514 required if the corresponding code section is marked. */
12516 static bfd_boolean
12518 elf_gc_mark_hook_fn gc_mark_hook)
12519 {
12522 bfd_boolean again;
12526 /* Marking EH data may cause additional code sections to be marked,
12527 requiring multiple passes. */
12530 {
12533 {
12541 {
12550 {
12554 }
12555 }
12556 }
12557 }
12560 }
12562 /* Treat mapping symbols as special target symbols. */
12564 static bfd_boolean
12566 {
12568 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
12569 }
12571 /* This is a copy of elf_find_function() from elf.c except that
12572 ARM mapping symbols are ignored when looking for function names
12573 and STT_ARM_TFUNC is considered to a function type. */
12575 static bfd_boolean
12579 bfd_vma offset,
12582 {
12589 {
12595 {
12604 /* Skip mapping symbols. */
12607 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
12609 /* Fall through. */
12613 {
12616 }
12618 }
12619 }
12630 }
12633 /* Find the nearest line to a particular section and offset, for error
12634 reporting. This code is a duplicate of the code in elf.c, except
12635 that it uses arm_elf_find_function. */
12637 static bfd_boolean
12641 bfd_vma offset,
12645 {
12648 /* We skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain uses it. */
12655 {
12659 functionname_ptr);
12662 }
12682 }
12684 static bfd_boolean
12689 {
12690 bfd_boolean found;
12695 }
12697 /* Adjust a symbol defined by a dynamic object and referenced by a
12698 regular object. The current definition is in some section of the
12699 dynamic object, but we're not including those sections. We have to
12700 change the definition to something the rest of the link can
12701 understand. */
12703 static bfd_boolean
12706 {
12718 /* Make sure we know what is going on here. */
12729 /* If this is a function, put it in the procedure linkage table. We
12730 will fill in the contents of the procedure linkage table later,
12731 when we know the address of the .got section. */
12733 {
12734 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
12735 symbol binds locally. */
12741 {
12742 /* This case can occur if we saw a PLT32 reloc in an input
12743 file, but the symbol was never referred to by a dynamic
12744 object, or if all references were garbage collected. In
12745 such a case, we don't actually need to build a procedure
12746 linkage table, and we can just do a PC24 reloc instead. */
12752 }
12755 }
12756 else
12757 {
12758 /* It's possible that we incorrectly decided a .plt reloc was
12759 needed for an R_ARM_PC24 or similar reloc to a non-function sym
12760 in check_relocs. We can't decide accurately between function
12761 and non-function syms in check-relocs; Objects loaded later in
12762 the link may change h->type. So fix it now. */
12767 }
12769 /* If this is a weak symbol, and there is a real definition, the
12770 processor independent code will have arranged for us to see the
12771 real definition first, and we can just use the same value. */
12773 {
12779 }
12781 /* If there are no non-GOT references, we do not need a copy
12782 relocation. */
12786 /* This is a reference to a symbol defined by a dynamic object which
12787 is not a function. */
12789 /* If we are creating a shared library, we must presume that the
12790 only references to the symbol are via the global offset table.
12791 For such cases we need not do anything here; the relocations will
12792 be handled correctly by relocate_section. Relocatable executables
12793 can reference data in shared objects directly, so we don't need to
12794 do anything here. */
12799 {
12803 }
12805 /* We must allocate the symbol in our .dynbss section, which will
12806 become part of the .bss section of the executable. There will be
12807 an entry for this symbol in the .dynsym section. The dynamic
12808 object will contain position independent code, so all references
12809 from the dynamic object to this symbol will go through the global
12810 offset table. The dynamic linker will use the .dynsym entry to
12811 determine the address it must put in the global offset table, so
12812 both the dynamic object and the regular object will refer to the
12813 same memory location for the variable. */
12817 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
12818 copy the initial value out of the dynamic object and into the
12819 runtime process image. We need to remember the offset into the
12820 .rel(a).bss section we are going to use. */
12822 {
12828 }
12831 }
12833 /* Allocate space in .plt, .got and associated reloc sections for
12834 dynamic relocs. */
12836 static bfd_boolean
12838 {
12856 {
12857 /* Make sure this symbol is output as a dynamic symbol.
12858 Undefined weak syms won't yet be marked as dynamic. */
12861 {
12864 }
12866 /* If the call in the PLT entry binds locally, the associated
12867 GOT entry should use an R_ARM_IRELATIVE relocation instead of
12868 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
12869 than the .plt section. */
12871 {
12875 /* All non-call references can be resolved directly.
12876 This means that they can (and in some cases, must)
12877 resolve directly to the run-time target, rather than
12878 to the PLT. That in turns means that any .got entry
12879 would be equal to the .igot.plt entry, so there's
12880 no point having both. */
12882 }
12887 {
12890 /* If this symbol is not defined in a regular file, and we are
12891 not generating a shared library, then set the symbol to this
12892 location in the .plt. This is required to make function
12893 pointers compare as equal between the normal executable and
12894 the shared library. */
12897 {
12901 /* Make sure the function is not marked as Thumb, in case
12902 it is the target of an ABS32 relocation, which will
12903 point to the PLT entry. */
12905 }
12909 /* VxWorks executables have a second set of relocations for
12910 each PLT entry. They go in a separate relocation section,
12911 which is processed by the kernel loader. */
12913 {
12914 /* There is a relocation for the initial PLT entry:
12915 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
12919 /* There are two extra relocations for each subsequent
12920 PLT entry: an R_ARM_32 relocation for the GOT entry,
12921 and an R_ARM_32 relocation for the PLT entry. */
12923 }
12924 }
12925 else
12926 {
12929 }
12930 }
12931 else
12932 {
12935 }
12941 {
12943 bfd_boolean dyn;
12947 /* Make sure this symbol is output as a dynamic symbol.
12948 Undefined weak syms won't yet be marked as dynamic. */
12951 {
12954 }
12957 {
12965 /* Non-TLS symbols need one GOT slot. */
12967 else
12968 {
12970 {
12971 /* R_ARM_TLS_DESC needs 2 GOT slots. */
12972 eh->tlsdesc_got
12977 /* plt.got_offset needs to know there's a TLS_DESC
12978 reloc in the middle of .got.plt. */
12980 }
12983 {
12984 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
12985 the symbol is both GD and GDESC, got.offset may
12986 have been overwritten. */
12989 }
12992 /* R_ARM_TLS_IE32 needs one GOT slot. */
12994 }
13008 {
13016 {
13018 /* GDESC needs a trampoline to jump to. */
13020 }
13022 /* Only GD needs it. GDESC just emits one relocation per
13023 2 entries. */
13026 }
13028 {
13030 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
13032 }
13035 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
13036 they all resolve dynamically instead. Reserve room for the
13037 GOT entry's R_ARM_IRELATIVE relocation. */
13040 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
13042 }
13043 }
13044 else
13047 /* Allocate stubs for exported Thumb functions on v4t. */
13052 {
13059 /* Create a new symbol to regist the real location of the function. */
13073 /* Point the symbol at the stub. */
13078 }
13083 /* In the shared -Bsymbolic case, discard space allocated for
13084 dynamic pc-relative relocs against symbols which turn out to be
13085 defined in regular objects. For the normal shared case, discard
13086 space for pc-relative relocs that have become local due to symbol
13087 visibility changes. */
13090 {
13091 /* The only relocs that use pc_count are R_ARM_REL32 and
13092 R_ARM_REL32_NOI, which will appear on something like
13093 ".long foo - .". We want calls to protected symbols to resolve
13094 directly to the function rather than going via the plt. If people
13095 want function pointer comparisons to work as expected then they
13096 should avoid writing assembly like ".long foo - .". */
13098 {
13102 {
13107 else
13109 }
13110 }
13113 {
13117 {
13120 else
13122 }
13123 }
13125 /* Also discard relocs on undefined weak syms with non-default
13126 visibility. */
13129 {
13133 /* Make sure undefined weak symbols are output as a dynamic
13134 symbol in PIEs. */
13137 {
13140 }
13141 }
13145 {
13146 /* Output absolute symbols so that we can create relocations
13147 against them. For normal symbols we output a relocation
13148 against the section that contains them. */
13151 }
13153 }
13154 else
13155 {
13156 /* For the non-shared case, discard space for relocs against
13157 symbols which turn out to need copy relocs or are not
13158 dynamic. */
13166 {
13167 /* Make sure this symbol is output as a dynamic symbol.
13168 Undefined weak syms won't yet be marked as dynamic. */
13171 {
13174 }
13176 /* If that succeeded, we know we'll be keeping all the
13177 relocs. */
13180 }
13184 keep: ;
13185 }
13187 /* Finally, allocate space. */
13189 {
13195 else
13197 }
13200 }
13202 /* Find any dynamic relocs that apply to read-only sections. */
13204 static bfd_boolean
13206 {
13212 {
13216 {
13221 /* Not an error, just cut short the traversal. */
13223 }
13224 }
13226 }
13228 void
13231 {
13239 }
13241 /* Set the sizes of the dynamic sections. */
13243 static bfd_boolean
13246 {
13249 bfd_boolean plt;
13250 bfd_boolean relocs;
13263 {
13264 /* Set the contents of the .interp section to the interpreter. */
13266 {
13271 }
13272 }
13274 /* Set up .got offsets for local syms, and space for local dynamic
13275 relocs. */
13277 {
13283 bfd_size_type locsymcount;
13293 {
13298 {
13301 {
13302 /* Input section has been discarded, either because
13303 it is a copy of a linkonce section or due to
13304 linker script /DISCARD/, so we'll be discarding
13305 the relocs too. */
13306 }
13310 {
13311 /* Relocations in vxworks .tls_vars sections are
13312 handled specially by the loader. */
13313 }
13315 {
13320 }
13321 }
13322 }
13340 {
13344 {
13348 {
13353 /* All references to the PLT are calls, so all
13354 non-call references can resolve directly to the
13355 run-time target. This means that the .got entry
13356 would be the same as the .igot.plt entry, so there's
13357 no point creating both. */
13359 }
13360 else
13361 {
13364 }
13367 {
13373 else
13375 }
13376 }
13378 {
13383 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13386 {
13391 /* plt.got_offset needs to know there's a TLS_DESC
13392 reloc in the middle of .got.plt. */
13394 }
13399 {
13400 /* If the symbol is both GD and GDESC, *local_got
13401 may have been overwritten. */
13404 }
13410 /* If all references to an STT_GNU_IFUNC PLT are calls,
13411 then all non-call references, including this GOT entry,
13412 resolve directly to the run-time target. */
13422 {
13425 }
13426 }
13427 else
13429 }
13430 }
13433 {
13434 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13435 for R_ARM_TLS_LDM32 relocations. */
13440 }
13441 else
13444 /* Allocate global sym .plt and .got entries, and space for global
13445 sym dynamic relocs. */
13448 /* Here we rummage through the found bfds to collect glue information. */
13450 {
13454 /* Initialise mapping tables for code/data. */
13459 /* xgettext:c-format */
13462 }
13464 /* Allocate space for the glue sections now that we've sized them. */
13467 /* For every jump slot reserved in the sgotplt, reloc_count is
13468 incremented. However, when we reserve space for TLS descriptors,
13469 it's not incremented, so in order to compute the space reserved
13470 for them, it suffices to multiply the reloc count by the jump
13471 slot size. */
13476 {
13483 /* If we're not using lazy TLS relocations, don't generate the
13484 PLT and GOT entries they require. */
13486 {
13492 }
13493 }
13495 /* The check_relocs and adjust_dynamic_symbol entry points have
13496 determined the sizes of the various dynamic sections. Allocate
13497 memory for them. */
13501 {
13507 /* It's OK to base decisions on the section name, because none
13508 of the dynobj section names depend upon the input files. */
13512 {
13513 /* Remember whether there is a PLT. */
13515 }
13517 {
13519 {
13520 /* Remember whether there are any reloc sections other
13521 than .rel(a).plt and .rela.plt.unloaded. */
13525 /* We use the reloc_count field as a counter if we need
13526 to copy relocs into the output file. */
13528 }
13529 }
13535 {
13536 /* It's not one of our sections, so don't allocate space. */
13538 }
13541 {
13542 /* If we don't need this section, strip it from the
13543 output file. This is mostly to handle .rel(a).bss and
13544 .rel(a).plt. We must create both sections in
13545 create_dynamic_sections, because they must be created
13546 before the linker maps input sections to output
13547 sections. The linker does that before
13548 adjust_dynamic_symbol is called, and it is that
13549 function which decides whether anything needs to go
13550 into these sections. */
13553 }
13558 /* Allocate memory for the section contents. */
13562 }
13565 {
13566 /* Add some entries to the .dynamic section. We fill in the
13567 values later, in elf32_arm_finish_dynamic_sections, but we
13568 must add the entries now so that we get the correct size for
13569 the .dynamic section. The DT_DEBUG entry is filled in by the
13570 dynamic linker and used by the debugger. */
13571 #define add_dynamic_entry(TAG, VAL) \
13572 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
13575 {
13578 }
13581 {
13593 }
13596 {
13598 {
13603 }
13604 else
13605 {
13610 }
13611 }
13613 /* If any dynamic relocs apply to a read-only section,
13614 then we need a DT_TEXTREL entry. */
13617 info);
13620 {
13623 }
13627 }
13628 #undef add_dynamic_entry
13631 }
13633 /* Size sections even though they're not dynamic. We use it to setup
13634 _TLS_MODULE_BASE_, if needed. */
13636 static bfd_boolean
13639 {
13648 {
13651 tlsbase = elf_link_hash_lookup
13655 {
13671 }
13672 }
13674 }
13676 /* Finish up dynamic symbol handling. We set the contents of various
13677 dynamic sections here. */
13679 static bfd_boolean
13684 {
13695 {
13697 {
13701 }
13704 {
13705 /* Mark the symbol as undefined, rather than as defined in
13706 the .plt section. Leave the value alone. */
13708 /* If the symbol is weak, we do need to clear the value.
13709 Otherwise, the PLT entry would provide a definition for
13710 the symbol even if the symbol wasn't defined anywhere,
13711 and so the symbol would never be NULL. */
13714 }
13716 {
13717 /* At least one non-call relocation references this .iplt entry,
13718 so the .iplt entry is the function's canonical address. */
13726 }
13727 }
13730 {
13732 Elf_Internal_Rela rel;
13734 /* This symbol needs a copy reloc. Set it up. */
13748 }
13750 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
13751 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
13752 to the ".got" section. */
13758 }
13760 static void
13764 {
13768 {
13771 /* Emit mov pc,rx if bx is not permitted. */
13775 }
13776 }
13778 /* Finish up the dynamic sections. */
13780 static bfd_boolean
13782 {
13795 /* A broken linker script might have discarded the dynamic sections.
13796 Catch this here so that we do not seg-fault later on. */
13802 {
13814 {
13815 Elf_Internal_Dyn dyn;
13822 {
13855 get_vma:
13860 else
13861 /* In the BPABI, tags in the PT_DYNAMIC section point
13862 at the file offset, not the memory address, for the
13863 convenience of the post linker. */
13868 get_vma_if_bpabi:
13883 {
13884 /* My reading of the SVR4 ABI indicates that the
13885 procedure linkage table relocs (DT_JMPREL) should be
13886 included in the overall relocs (DT_REL). This is
13887 what Solaris does. However, UnixWare can not handle
13888 that case. Therefore, we override the DT_RELSZ entry
13889 here to make it not include the JMPREL relocs. Since
13890 the linker script arranges for .rel(a).plt to follow all
13891 other relocation sections, we don't have to worry
13892 about changing the DT_REL entry. */
13898 }
13899 /* Fall through. */
13903 /* In the BPABI, the DT_REL tag must point at the file
13904 offset, not the VMA, of the first relocation
13905 section. So, we use code similar to that in
13906 elflink.c, but do not check for SHF_ALLOC on the
13907 relcoation section, since relocations sections are
13908 never allocated under the BPABI. The comments above
13909 about Unixware notwithstanding, we include all of the
13910 relocations here. */
13912 {
13918 {
13919 Elf_Internal_Shdr *hdr
13922 {
13929 }
13930 }
13932 }
13949 /* Set the bottom bit of DT_INIT/FINI if the
13950 corresponding function is Thumb. */
13956 get_sym:
13957 /* If it wasn't set by elf_bfd_final_link
13958 then there is nothing to adjust. */
13960 {
13966 {
13969 }
13970 }
13972 }
13973 }
13975 /* Fill in the first entry in the procedure linkage table. */
13977 {
13981 /* Calculate the addresses of the GOT and PLT. */
13986 {
13987 /* The VxWorks GOT is relocated by the dynamic linker.
13988 Therefore, we must emit relocations rather than simply
13989 computing the values now. */
13990 Elf_Internal_Rela rel;
14001 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
14007 }
14008 else
14009 {
14022 #ifdef FOUR_WORD_PLT
14023 /* The displacement value goes in the otherwise-unused
14024 last word of the second entry. */
14026 #else
14028 #endif
14029 }
14030 }
14032 /* UnixWare sets the entsize of .plt to 4, although that doesn't
14033 really seem like the right value. */
14038 {
14039 bfd_vma got_address
14043 bfd_vma plt_address
14059 }
14062 {
14066 #ifdef FOUR_WORD_PLT
14069 #endif
14070 }
14073 {
14074 /* Correct the .rel(a).plt.unloaded relocations. They will have
14075 incorrect symbol indexes. */
14084 {
14085 Elf_Internal_Rela rel;
14096 }
14097 }
14098 }
14100 /* Fill in the first three entries in the global offset table. */
14102 {
14104 {
14107 else
14113 }
14116 }
14119 }
14121 static void
14122 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14123 {
14131 else
14136 {
14140 }
14141 }
14143 static enum elf_reloc_type_class
14145 {
14147 {
14156 }
14157 }
14159 static void
14161 {
14163 }
14165 /* Return TRUE if this is an unwinding table entry. */
14167 static bfd_boolean
14169 {
14172 }
14175 /* Set the type and flags for an ARM section. We do this by
14176 the section name, which is a hack, but ought to work. */
14178 static bfd_boolean
14180 {
14186 {
14189 }
14191 }
14193 /* Handle an ARM specific section when reading an object file. This is
14194 called when bfd_section_from_shdr finds a section with an unknown
14195 type. */
14197 static bfd_boolean
14202 {
14203 /* There ought to be a place to keep ELF backend specific flags, but
14204 at the moment there isn't one. We just keep track of the
14205 sections by their name, instead. Fortunately, the ABI gives
14206 names for all the ARM specific sections, so we will probably get
14207 away with this. */
14209 {
14217 }
14223 }
14227 {
14230 else
14232 }
14235 {
14244 enum map_symbol_type
14245 {
14246 ARM_MAP_ARM,
14247 ARM_MAP_THUMB,
14248 ARM_MAP_DATA
14249 };
14252 /* Output a single mapping symbol. */
14254 static bfd_boolean
14257 bfd_vma offset)
14258 {
14260 Elf_Internal_Sym sym;
14272 }
14274 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14275 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14277 static bfd_boolean
14279 bfd_boolean is_iplt_entry_p,
14282 {
14294 {
14297 }
14298 else
14299 {
14302 }
14308 {
14313 }
14315 {
14324 }
14325 else
14326 {
14327 bfd_boolean thumb_stub_p;
14331 {
14334 }
14335 #ifdef FOUR_WORD_PLT
14340 #else
14341 /* A three-word PLT with no Thumb thunk contains only Arm code,
14342 so only need to output a mapping symbol for the first PLT entry and
14343 entries with thumb thunks. */
14345 {
14348 }
14349 #endif
14350 }
14353 }
14355 /* Output mapping symbols for PLT entries associated with H. */
14357 static bfd_boolean
14359 {
14367 /* When warning symbols are created, they **replace** the "real"
14368 entry in the hash table, thus we never get to see the real
14369 symbol in a hash traversal. So look at it now. */
14375 }
14377 /* Output a single local symbol for a generated stub. */
14379 static bfd_boolean
14382 {
14383 Elf_Internal_Sym sym;
14394 }
14396 static bfd_boolean
14399 {
14402 bfd_vma addr;
14411 /* Massage our args to the form they really have. */
14417 /* Ensure this stub is attached to the current section being
14418 processed. */
14427 {
14441 }
14446 {
14448 {
14465 }
14468 {
14472 }
14475 {
14492 }
14493 }
14496 }
14498 /* Output mapping symbols for linker generated sections,
14499 and for those data-only sections that do not have a
14500 $d. */
14502 static bfd_boolean
14507 Elf_Internal_Sym *,
14508 asection *,
14510 {
14511 output_arch_syminfo osi;
14513 bfd_vma offset;
14514 bfd_size_type size;
14527 /* Add a $d mapping symbol to data-only sections that
14528 don't have any mapping symbol. This may result in (harmless) redundant
14529 mapping symbols. */
14533 {
14538 {
14543 == SEC_HAS_CONTENTS
14548 {
14553 }
14554 }
14555 }
14557 /* ARM->Thumb glue. */
14559 {
14561 ARM2THUMB_GLUE_SECTION_NAME);
14570 else
14574 {
14577 }
14578 }
14580 /* Thumb->ARM glue. */
14582 {
14584 THUMB2ARM_GLUE_SECTION_NAME);
14591 {
14594 }
14595 }
14597 /* ARMv4 BX veneers. */
14599 {
14601 ARM_BX_GLUE_SECTION_NAME);
14607 }
14609 /* Long calls stubs. */
14611 {
14617 {
14618 /* Ignore non-stub sections. */
14628 }
14629 }
14631 /* Finally, output mapping symbols for the PLT. */
14633 {
14638 /* Output mapping symbols for the plt header. SymbianOS does not have a
14639 plt header. */
14641 {
14642 /* VxWorks shared libraries have no PLT header. */
14644 {
14649 }
14650 }
14652 {
14655 #ifndef FOUR_WORD_PLT
14658 #endif
14659 }
14660 }
14663 {
14668 {
14674 {
14682 }
14683 }
14684 }
14686 {
14687 /* Mapping symbols for the lazy tls trampoline. */
14694 }
14696 {
14697 /* Mapping symbols for the tls trampoline. */
14700 #ifdef FOUR_WORD_PLT
14704 #endif
14705 }
14708 }
14710 /* Allocate target specific section data. */
14712 static bfd_boolean
14714 {
14716 {
14724 }
14727 }
14730 /* Used to order a list of mapping symbols by address. */
14732 static int
14734 {
14743 /* Ensure results do not depend on the host qsort for objects with
14744 multiple mapping symbols at the same address by sorting on type
14745 after vma. */
14749 else
14751 }
14753 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
14755 static unsigned long
14757 {
14759 }
14761 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
14762 relocations. */
14764 static void
14766 {
14770 /* High bit of first word is supposed to be zero. */
14774 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
14775 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
14781 }
14783 /* Data for make_branch_to_a8_stub(). */
14788 };
14791 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
14792 places for a particular section. */
14794 static bfd_boolean
14797 {
14803 bfd_signed_vma branch_offset;
14832 /* We attempt to avoid this condition by setting stubs_always_after_branch
14833 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
14834 This check is just to be on the safe side... */
14836 {
14840 }
14843 {
14854 {
14859 jump24:
14861 {
14862 /* There's not much we can do apart from complain if this
14863 happens. */
14867 }
14869 /* i1 = not(j1 eor s), so:
14870 not i1 = j1 eor s
14871 j1 = (not i1) eor s. */
14883 }
14889 }
14895 }
14897 /* Do code byteswapping. Return FALSE afterwards so that the section is
14898 written out as normal. */
14900 static bfd_boolean
14905 {
14911 bfd_vma ptr;
14912 bfd_vma end;
14914 bfd_byte tmp;
14920 /* If this section has not been allocated an _arm_elf_section_data
14921 structure then we cannot record anything. */
14931 {
14936 {
14940 {
14942 {
14943 bfd_vma branch_to_veneer;
14944 /* Original condition code of instruction, plus bit mask for
14945 ARM B instruction. */
14949 /* The instruction is before the label. */
14952 /* Above offset included in -4 below. */
14966 }
14970 {
14971 bfd_vma branch_from_veneer;
14974 /* Take size of veneer into account. */
14983 /* Original instruction. */
14990 /* Branch back to insn after original insn. */
14996 }
15001 }
15002 }
15003 }
15006 {
15007 arm_unwind_table_edit *edit_node
15009 /* Now, sec->size is the size of the section we will write. The original
15010 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
15011 markers) was sec->rawsize. (This isn't the case if we perform no
15012 edits, then rawsize will be zero and we should use size). */
15019 {
15021 {
15025 {
15028 out_index++;
15029 in_index++;
15030 }
15034 {
15036 {
15038 in_index++;
15043 {
15051 /* Note: this is meant to be equivalent to an
15052 R_ARM_PREL31 relocation. These synthetic
15053 EXIDX_CANTUNWIND markers are not relocated by the
15054 usual BFD method. */
15058 /* First address we can't unwind. */
15062 /* Code for EXIDX_CANTUNWIND. */
15066 out_index++;
15068 }
15070 }
15073 }
15074 }
15075 else
15076 {
15077 /* No more edits, copy remaining entries verbatim. */
15080 out_index++;
15081 in_index++;
15082 }
15083 }
15087 edited_contents,
15091 }
15093 /* Fix code to point to Cortex-A8 erratum stubs. */
15095 {
15103 }
15109 {
15114 {
15117 else
15121 {
15123 /* Byte swap code words. */
15125 {
15133 }
15137 /* Byte swap code halfwords. */
15139 {
15144 }
15148 /* Leave data alone. */
15150 }
15152 }
15153 }
15161 }
15163 /* Mangle thumb function symbols as we read them in. */
15165 static bfd_boolean
15170 {
15174 /* New EABI objects mark thumb function symbols by setting the low bit of
15175 the address. */
15178 {
15180 {
15183 }
15184 else
15186 }
15188 {
15191 }
15194 else
15198 }
15201 /* Mangle thumb function symbols as we write them out. */
15203 static void
15208 {
15209 Elf_Internal_Sym newsym;
15211 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15212 of the address set, as per the new EABI. We do this unconditionally
15213 because objcopy does not set the elf header flags until after
15214 it writes out the symbol table. */
15216 {
15221 {
15222 /* Do this only for defined symbols. At link type, the static
15223 linker will simulate the work of dynamic linker of resolving
15224 symbols and will carry over the thumbness of found symbols to
15225 the output symbol table. It's not clear how it happens, but
15226 the thumbness of undefined symbols can well be different at
15227 runtime, and writing '1' for them will be confusing for users
15228 and possibly for dynamic linker itself.
15229 */
15231 }
15234 }
15236 }
15238 /* Add the PT_ARM_EXIDX program header. */
15240 static bfd_boolean
15243 {
15249 {
15250 /* If there is already a PT_ARM_EXIDX header, then we do not
15251 want to add another one. This situation arises when running
15252 "strip"; the input binary already has the header. */
15257 {
15268 }
15269 }
15272 }
15274 /* We may add a PT_ARM_EXIDX program header. */
15276 static int
15279 {
15285 else
15287 }
15289 /* Hook called by the linker routine which adds symbols from an object
15290 file. */
15292 static bfd_boolean
15296 {
15308 }
15310 /* We use this to override swap_symbol_in and swap_symbol_out. */
15312 {
15325 bfd_elf32_write_out_phdrs,
15326 bfd_elf32_write_shdrs_and_ehdr,
15327 bfd_elf32_checksum_contents,
15328 bfd_elf32_write_relocs,
15329 elf32_arm_swap_symbol_in,
15330 elf32_arm_swap_symbol_out,
15331 bfd_elf32_slurp_reloc_table,
15332 bfd_elf32_slurp_symbol_table,
15333 bfd_elf32_swap_dyn_in,
15334 bfd_elf32_swap_dyn_out,
15335 bfd_elf32_swap_reloc_in,
15336 bfd_elf32_swap_reloc_out,
15337 bfd_elf32_swap_reloca_in,
15338 bfd_elf32_swap_reloca_out
15339 };
15341 #define ELF_ARCH bfd_arch_arm
15342 #define ELF_TARGET_ID ARM_ELF_DATA
15343 #define ELF_MACHINE_CODE EM_ARM
15344 #ifdef __QNXTARGET__
15345 #define ELF_MAXPAGESIZE 0x1000
15346 #else
15347 #define ELF_MAXPAGESIZE 0x8000
15348 #endif
15349 #define ELF_MINPAGESIZE 0x1000
15350 #define ELF_COMMONPAGESIZE 0x1000
15352 #define bfd_elf32_mkobject elf32_arm_mkobject
15354 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
15355 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
15356 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
15357 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
15358 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
15359 #define bfd_elf32_bfd_link_hash_table_free elf32_arm_hash_table_free
15360 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
15361 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
15362 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
15363 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
15364 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
15365 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
15366 #define bfd_elf32_bfd_final_link elf32_arm_final_link
15368 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
15369 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
15370 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
15371 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
15372 #define elf_backend_check_relocs elf32_arm_check_relocs
15373 #define elf_backend_relocate_section elf32_arm_relocate_section
15374 #define elf_backend_write_section elf32_arm_write_section
15375 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
15376 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
15377 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
15378 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
15379 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
15380 #define elf_backend_always_size_sections elf32_arm_always_size_sections
15381 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
15382 #define elf_backend_post_process_headers elf32_arm_post_process_headers
15383 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
15384 #define elf_backend_object_p elf32_arm_object_p
15385 #define elf_backend_fake_sections elf32_arm_fake_sections
15386 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
15387 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15388 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
15389 #define elf_backend_size_info elf32_arm_size_info
15390 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
15391 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
15392 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
15393 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
15394 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
15396 #define elf_backend_can_refcount 1
15397 #define elf_backend_can_gc_sections 1
15398 #define elf_backend_plt_readonly 1
15399 #define elf_backend_want_got_plt 1
15400 #define elf_backend_want_plt_sym 0
15401 #define elf_backend_may_use_rel_p 1
15402 #define elf_backend_may_use_rela_p 0
15403 #define elf_backend_default_use_rela_p 0
15405 #define elf_backend_got_header_size 12
15407 #undef elf_backend_obj_attrs_vendor
15409 #undef elf_backend_obj_attrs_section
15411 #undef elf_backend_obj_attrs_arg_type
15412 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
15413 #undef elf_backend_obj_attrs_section_type
15414 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
15415 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
15416 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
15420 /* VxWorks Targets. */
15422 #undef TARGET_LITTLE_SYM
15423 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_vxworks_vec
15424 #undef TARGET_LITTLE_NAME
15426 #undef TARGET_BIG_SYM
15427 #define TARGET_BIG_SYM bfd_elf32_bigarm_vxworks_vec
15428 #undef TARGET_BIG_NAME
15431 /* Like elf32_arm_link_hash_table_create -- but overrides
15432 appropriately for VxWorks. */
15436 {
15441 {
15446 }
15448 }
15450 static void
15452 {
15455 }
15457 #undef elf32_bed
15458 #define elf32_bed elf32_arm_vxworks_bed
15460 #undef bfd_elf32_bfd_link_hash_table_create
15461 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
15462 #undef elf_backend_final_write_processing
15463 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
15464 #undef elf_backend_emit_relocs
15465 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
15467 #undef elf_backend_may_use_rel_p
15468 #define elf_backend_may_use_rel_p 0
15469 #undef elf_backend_may_use_rela_p
15470 #define elf_backend_may_use_rela_p 1
15471 #undef elf_backend_default_use_rela_p
15472 #define elf_backend_default_use_rela_p 1
15473 #undef elf_backend_want_plt_sym
15474 #define elf_backend_want_plt_sym 1
15475 #undef ELF_MAXPAGESIZE
15476 #define ELF_MAXPAGESIZE 0x1000
15481 /* Merge backend specific data from an object file to the output
15482 object file when linking. */
15484 static bfd_boolean
15486 {
15487 flagword out_flags;
15488 flagword in_flags;
15492 /* Check if we have the same endianness. */
15502 /* The input BFD must have had its flags initialised. */
15503 /* The following seems bogus to me -- The flags are initialized in
15504 the assembler but I don't think an elf_flags_init field is
15505 written into the object. */
15506 /* BFD_ASSERT (elf_flags_init (ibfd)); */
15511 /* In theory there is no reason why we couldn't handle this. However
15512 in practice it isn't even close to working and there is no real
15513 reason to want it. */
15517 {
15519 ibfd);
15521 }
15524 {
15525 /* If the input is the default architecture and had the default
15526 flags then do not bother setting the flags for the output
15527 architecture, instead allow future merges to do this. If no
15528 future merges ever set these flags then they will retain their
15529 uninitialised values, which surprise surprise, correspond
15530 to the default values. */
15543 }
15545 /* Determine what should happen if the input ARM architecture
15546 does not match the output ARM architecture. */
15550 /* Identical flags must be compatible. */
15554 /* Check to see if the input BFD actually contains any sections. If
15555 not, its flags may not have been initialised either, but it
15556 cannot actually cause any incompatiblity. Do not short-circuit
15557 dynamic objects; their section list may be emptied by
15558 elf_link_add_object_symbols.
15560 Also check to see if there are no code sections in the input.
15561 In this case there is no need to check for code specific flags.
15562 XXX - do we need to worry about floating-point format compatability
15563 in data sections ? */
15565 {
15570 {
15571 /* Ignore synthetic glue sections. */
15574 {
15582 }
15583 }
15587 }
15589 /* Complain about various flag mismatches. */
15592 {
15593 _bfd_error_handler
15599 }
15601 /* Not sure what needs to be checked for EABI versions >= 1. */
15602 /* VxWorks libraries do not use these flags. */
15606 {
15608 {
15609 _bfd_error_handler
15615 }
15618 {
15620 _bfd_error_handler
15621 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
15623 else
15624 _bfd_error_handler
15625 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
15629 }
15632 {
15634 _bfd_error_handler
15637 else
15638 _bfd_error_handler
15643 }
15646 {
15648 _bfd_error_handler
15651 else
15652 _bfd_error_handler
15657 }
15659 #ifdef EF_ARM_SOFT_FLOAT
15661 {
15662 /* We can allow interworking between code that is VFP format
15663 layout, and uses either soft float or integer regs for
15664 passing floating point arguments and results. We already
15665 know that the APCS_FLOAT flags match; similarly for VFP
15666 flags. */
15669 {
15671 _bfd_error_handler
15674 else
15675 _bfd_error_handler
15680 }
15681 }
15682 #endif
15684 /* Interworking mismatch is only a warning. */
15686 {
15688 {
15689 _bfd_error_handler
15692 }
15693 else
15694 {
15695 _bfd_error_handler
15698 }
15699 }
15700 }
15703 }
15706 /* Symbian OS Targets. */
15708 #undef TARGET_LITTLE_SYM
15709 #define TARGET_LITTLE_SYM bfd_elf32_littlearm_symbian_vec
15710 #undef TARGET_LITTLE_NAME
15712 #undef TARGET_BIG_SYM
15713 #define TARGET_BIG_SYM bfd_elf32_bigarm_symbian_vec
15714 #undef TARGET_BIG_NAME
15717 /* Like elf32_arm_link_hash_table_create -- but overrides
15718 appropriately for Symbian OS. */
15722 {
15727 {
15730 /* There is no PLT header for Symbian OS. */
15732 /* The PLT entries are each one instruction and one word. */
15735 /* Symbian uses armv5t or above, so use_blx is always true. */
15738 }
15740 }
15742 static const struct bfd_elf_special_section
15743 elf32_arm_symbian_special_sections[] =
15744 {
15745 /* In a BPABI executable, the dynamic linking sections do not go in
15746 the loadable read-only segment. The post-linker may wish to
15747 refer to these sections, but they are not part of the final
15748 program image. */
15754 /* These sections do not need to be writable as the SymbianOS
15755 postlinker will arrange things so that no dynamic relocation is
15756 required. */
15761 };
15763 static void
15766 {
15767 /* BPABI objects are never loaded directly by an OS kernel; they are
15768 processed by a postlinker first, into an OS-specific format. If
15769 the D_PAGED bit is set on the file, BFD will align segments on
15770 page boundaries, so that an OS can directly map the file. With
15771 BPABI objects, that just results in wasted space. In addition,
15772 because we clear the D_PAGED bit, map_sections_to_segments will
15773 recognize that the program headers should not be mapped into any
15774 loadable segment. */
15777 }
15779 static bfd_boolean
15782 {
15786 /* BPABI shared libraries and executables should have a PT_DYNAMIC
15787 segment. However, because the .dynamic section is not marked
15788 with SEC_LOAD, the generic ELF code will not create such a
15789 segment. */
15792 {
15798 {
15802 }
15803 }
15805 /* Also call the generic arm routine. */
15807 }
15809 /* Return address for Ith PLT stub in section PLT, for relocation REL
15810 or (bfd_vma) -1 if it should not be included. */
15812 static bfd_vma
15815 {
15817 }
15820 #undef elf32_bed
15821 #define elf32_bed elf32_arm_symbian_bed
15823 /* The dynamic sections are not allocated on SymbianOS; the postlinker
15824 will process them and then discard them. */
15825 #undef ELF_DYNAMIC_SEC_FLAGS
15826 #define ELF_DYNAMIC_SEC_FLAGS \
15827 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
15829 #undef elf_backend_emit_relocs
15831 #undef bfd_elf32_bfd_link_hash_table_create
15832 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
15833 #undef elf_backend_special_sections
15834 #define elf_backend_special_sections elf32_arm_symbian_special_sections
15835 #undef elf_backend_begin_write_processing
15836 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
15837 #undef elf_backend_final_write_processing
15838 #define elf_backend_final_write_processing elf32_arm_final_write_processing
15840 #undef elf_backend_modify_segment_map
15841 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
15843 /* There is no .got section for BPABI objects, and hence no header. */
15844 #undef elf_backend_got_header_size
15845 #define elf_backend_got_header_size 0
15847 /* Similarly, there is no .got.plt section. */
15848 #undef elf_backend_want_got_plt
15849 #define elf_backend_want_got_plt 0
15851 #undef elf_backend_plt_sym_val
15852 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
15854 #undef elf_backend_may_use_rel_p
15855 #define elf_backend_may_use_rel_p 1
15856 #undef elf_backend_may_use_rela_p
15857 #define elf_backend_may_use_rela_p 0
15858 #undef elf_backend_default_use_rela_p
15859 #define elf_backend_default_use_rela_p 0
15860 #undef elf_backend_want_plt_sym
15861 #define elf_backend_want_plt_sym 0
15862 #undef ELF_MAXPAGESIZE
15863 #define ELF_MAXPAGESIZE 0x8000