devices/attiny28

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="2048"/>
   6     <iospace start="$20" stop="$5F"/>
   7     <sram size="0"/>
   8     <eram size="0"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="SREG" address="$3F"/>
  12     <ioreg name="PORTA" address="$1B"/>
  13     <ioreg name="PACR" address="$1A"/>
  14     <ioreg name="PINA" address="$19"/>
  15     <ioreg name="PINB" address="$16"/>
  16     <ioreg name="PORTD" address="$12"/>
  17     <ioreg name="DDRD" address="$11"/>
  18     <ioreg name="PIND" address="$10"/>
  19     <ioreg name="ACSR" address="$08"/>
  20     <ioreg name="MCUCS" address="$07"/>
  21     <ioreg name="ICR" address="$06"/>
  22     <ioreg name="IFR" address="$05"/>
  23     <ioreg name="TCCR0" address="$04"/>
  24     <ioreg name="TCNT0" address="$03"/>
  25     <ioreg name="MODCR" address="$02"/>
  26     <ioreg name="WDTCR" address="$01"/>
  27     <ioreg name="OSCCAL" address="$00"/>
  28   </ioregisters>
  29   <interrupts num="6">
  30     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
  31     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
  32     <interrupt vector="3" address="$002" name="INT1">External Interrupt 1</interrupt>
  33     <interrupt vector="4" address="$003" name="LOW-LEVEL I/O PINS">Low-level Input on Port B</interrupt>
  34     <interrupt vector="5" address="$004" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  35     <interrupt vector="6" address="$005" name="ANA_COMP">Analog Comparator</interrupt>
  36   </interrupts>
  37   <packages>
  38     <package name="TQFP" pins="32">
  39       <pin id="1" name="[PD3]"/>
  40       <pin id="2" name="[PD4]"/>
  41       <pin id="3" name="[NC]"/>
  42       <pin id="4" name="[VCC]"/>
  43       <pin id="5" name="[GND]"/>
  44       <pin id="6" name="[NC]"/>
  45       <pin id="7" name="[XTAL1]"/>
  46       <pin id="8" name="[XTAL2]"/>
  47       <pin id="9" name="[PD5]"/>
  48       <pin id="10" name="[PD6]"/>
  49       <pin id="11" name="[PD7]"/>
  50       <pin id="12" name="[AIN0:PB0]"/>
  51       <pin id="13" name="[AIN1:PB1]"/>
  52       <pin id="14" name="[T0:PB2]"/>
  53       <pin id="15" name="[INT0:PB3]"/>
  54       <pin id="16" name="[INT1:PB4]"/>
  55       <pin id="17" name="[PB5]"/>
  56       <pin id="18" name="[VCC]"/>
  57       <pin id="19" name="[NC]"/>
  58       <pin id="20" name="[NC]"/>
  59       <pin id="21" name="[GND]"/>
  60       <pin id="22" name="[NC]"/>
  61       <pin id="23" name="[PB6]"/>
  62       <pin id="24" name="[PB7]"/>
  63       <pin id="25" name="[PA2:IR]"/>
  64       <pin id="26" name="[PA3]"/>
  65       <pin id="27" name="[PA1]"/>
  66       <pin id="28" name="[PA0]"/>
  67       <pin id="29" name="[RESET]"/>
  68       <pin id="30" name="[PD0]"/>
  69       <pin id="31" name="[PD1]"/>
  70       <pin id="32" name="[PD2]"/>
  71     </package>
  72   </packages>
  73   <hardware>
  74 <!--Everything after this needs editing!!!-->
  75     <module class="FUSE">
  76       <registers name="FUSE" memspace="FUSE">
  77           <reg size="1" name="LOW" offset="0x00">
  78             <bitfield name="INTCAP" mask="0x10" text="Internal load capacitors between XTAL1/XTAL2 and GND" icon=""/>
  79             <bitfield name="CKSEL" mask="0x0F" text="Clock Select" icon="" enum="ENUM1"/>
  80           </reg>
  81         </registers>
  82     </module>
  83     <module class="LOCKBIT">
  84       <registers name="LOCKBIT" memspace="LOCKBIT">
  85           <reg size="1" name="LOCKBIT" offset="0x00">
  86             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
  87           </reg>
  88         </registers>
  89     </module>
  90     <module class="PORTD">
  91       <registers name="PORTD" memspace="IOMEM" text="" icon="io_port.bmp">
  92           <reg size="1" name="PORTD" offset="0x12" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
  93           <reg size="1" name="DDRD" offset="0x11" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
  94           <reg size="1" name="PIND" offset="0x10" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
  95         </registers>
  96     </module>
  97     <module class="CPU">
  98       <registers name="CPU" memspace="IOMEM" text="" icon="io_cpu.com">
  99           <reg size="1" name="SREG" offset="0x3F" text="Status Register" icon="io_sreg.bmp">
 100             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 101             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 102             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 103             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 104             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 105             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 106             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 107             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 108           </reg>
 109           <reg size="1" name="ICR" offset="0x06" text="Interrupt Control Register" icon="io_cpu.bmp">
 110             <bitfield name="ICS1" mask="0x0C" text="Interrupt Sense Control 1 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 111             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 112           </reg>
 113           <reg size="1" name="MCUCS" offset="0x07" text="MCU Control and Status Register" icon="io_cpu.bmp">
 114             <bitfield name="PLUPB" mask="0x80" text="Pull-up Enable Port B" icon=""/>
 115             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 116             <bitfield name="SM" mask="0x10" text="Sleep Mode" icon=""/>
 117             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 118             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 119             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 120           </reg>
 121           <reg size="1" name="OSCCAL" offset="0x00" text="Status Register" icon="io_sreg.bmp" mask="0xFF"/>
 122         </registers>
 123     </module>
 124     <module class="ANALOG_COMPARATOR">
 125       <registers name="ANALOG_COMPARATOR" memspace="IOMEM" text="" icon="io_analo.bmp">
 126           <reg size="1" name="ACSR" offset="0x08" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 127             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 128             <bitfield name="ACO" mask="0x20" text="Analog Comparator Output" icon=""/>
 129             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 130             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 131             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 132           </reg>
 133         </registers>
 134     </module>
 135     <module class="TIMER_COUNTER_0">
 136       <registers name="TIMER_COUNTER_0" memspace="IOMEM" text="" icon="io_timer.bmp">
 137           <reg size="1" name="ICR" offset="0x06" text="Interrupt Control Register" icon="io_flag.bmp">
 138             <bitfield name="TOIE0" mask="0x10" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 139           </reg>
 140           <reg size="1" name="IFR" offset="0x05" text="Interrupt Flag register" icon="io_flag.bmp">
 141             <bitfield name="TOV0" mask="0x10" text="Timer/Counter0 Overflow Flag" icon=""/>
 142           </reg>
 143           <reg size="1" name="TCCR0" offset="0x04" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 144             <bitfield name="FOV0" mask="0x80" text="Force Overflow" icon=""/>
 145             <bitfield name="OOM0" mask="0x18" text="Overflow Output Mode, Bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 146             <bitfield name="CS0" mask="0x07" text="Clock Select0 bits" icon="" enum="CLK_SEL_3BIT_EXT_MOD"/>
 147           </reg>
 148           <reg size="1" name="TCNT0" offset="0x03" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 149         </registers>
 150     </module>
 151     <module class="WATCHDOG">
 152       <registers name="WATCHDOG" memspace="IOMEM" text="" icon="io_watch.bmp">
 153           <reg size="1" name="WDTCR" offset="0x01" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 154             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 155             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 156             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 157           </reg>
 158         </registers>
 159     </module>
 160     <module class="EXTERNAL_INTERRUPT">
 161       <registers name="EXTERNAL_INTERRUPT" memspace="IOMEM" text="" icon="io_ext.bmp">
 162           <reg size="1" name="ICR" offset="0x06" text="Interrupt Control Register" icon="io_flag.bmp">
 163             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 164             <bitfield name="LLIE" mask="0x20" text="Low-level Input Interrupt Enable" icon=""/>
 165           </reg>
 166           <reg size="1" name="IFR" offset="0x05" text="Interrupt Flag register" icon="io_flag.bmp">
 167             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 168           </reg>
 169         </registers>
 170     </module>
 171     <module class="PORTA">
 172       <registers name="PORTA" memspace="IOMEM" text="" icon="io_port.bmp">
 173           <reg size="1" name="PORTA" offset="0x1B" text="Port A Data Register" icon="io_port.bmp" mask="0x0F"/>
 174           <reg size="1" name="PACR" offset="0x1A" text="Port A Control Register" icon="io_flag.bmp" mask="0x0F"/>
 175           <reg size="1" name="PINA" offset="0x19" text="Port A Input Pins" icon="io_port.bmp" mask="0x0B"/>
 176         </registers>
 177     </module>
 178     <module class="PORTB">
 179       <registers name="PORTB" memspace="IOMEM" text="" icon="io_port.bmp">
 180           <reg size="1" name="PINB" offset="0x16" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 181         </registers>
 182     </module>
 183     <module class="MODULATOR">
 184       <registers name="MODULATOR" memspace="IOMEM" text="" icon="io_poer.bmp">
 185           <reg size="1" name="MODCR" offset="0x02" text="Modulation Control Register" icon="io_flag.bmp">
 186             <bitfield name="ONTIM4" mask="0x80" text="Modulation On-time Bit 4" icon=""/>
 187             <bitfield name="OTIM3" mask="0x40" text="Modulation On-time Bit 3" icon=""/>
 188             <bitfield name="ONTIM" mask="0x38" text="Modulation On-time Bits" icon=""/>
 189             <bitfield name="MCONF" mask="0x07" text="Modulation Configuration Bits" icon=""/>
 190           </reg>
 191         </registers>
 192     </module>
 193   </hardware>
 194 </device>