devices/at90pwm2b

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="32">
   5     <interrupt vector="1" address="$0000" name="RESET">External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</interrupt>
   6     <interrupt vector="2" address="$0001" name="PSC2 CAPT">PSC2 Capture Event</interrupt>
   7     <interrupt vector="3" address="$0002" name="PSC2 EC">PSC2 End Cycle</interrupt>
   8     <interrupt vector="4" address="$0003" name="PSC1 CAPT">PSC1 Capture Event</interrupt>
   9     <interrupt vector="5" address="$0004" name="PSC1 EC">PSC1 End Cycle</interrupt>
  10     <interrupt vector="6" address="$0005" name="PSC0 CAPT">PSC0 Capture Event</interrupt>
  11     <interrupt vector="7" address="$0006" name="PSC0 EC">PSC0 End Cycle</interrupt>
  12     <interrupt vector="8" address="$0007" name="ANALOG COMP 0">Analog Comparator 0</interrupt>
  13     <interrupt vector="9" address="$0008" name="ANALOG COMP 1">Analog Comparator 1</interrupt>
  14     <interrupt vector="10" address="$0009" name="ANALOG COMP 2">Analog Comparator 2</interrupt>
  15     <interrupt vector="11" address="$000A" name="INT0">External Interrupt Request 0</interrupt>
  16     <interrupt vector="12" address="$000B" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  17     <interrupt vector="13" address="$000C" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  18     <interrupt vector="14" address="$000D" name="TIMER1 COMPB">Timer/Counter Compare Match B</interrupt>
  19     <interrupt vector="15" address="$000E" name="RESERVED15"/>
  20     <interrupt vector="16" address="$000F" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  21     <interrupt vector="17" address="$0010" name="TIMER0 COMP A">Timer/Counter0 Compare Match A</interrupt>
  22     <interrupt vector="18" address="$0011" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  23     <interrupt vector="19" address="$0012" name="ADC">ADC Conversion Complete</interrupt>
  24     <interrupt vector="20" address="$0013" name="INT1">External Interrupt Request 1</interrupt>
  25     <interrupt vector="21" address="$0014" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
  26     <interrupt vector="22" address="$0015" name="USART, RX">USART, Rx Complete</interrupt>
  27     <interrupt vector="23" address="$0016" name="USART, UDRE">USART Data Register Empty</interrupt>
  28     <interrupt vector="24" address="$0017" name="USART, TX">USART, Tx Complete</interrupt>
  29     <interrupt vector="25" address="$0018" name="INT2">External Interrupt Request 2</interrupt>
  30     <interrupt vector="26" address="$0019" name="WDT">Watchdog Timeout Interrupt</interrupt>
  31     <interrupt vector="27" address="$001A" name="EE READY">EEPROM Ready</interrupt>
  32     <interrupt vector="28" address="$001B" name="TIMER0 COMPB">Timer Counter 0 Compare Match B</interrupt>
  33     <interrupt vector="29" address="$001C" name="INT3">External Interrupt Request 3</interrupt>
  34     <interrupt vector="30" address="$001D" name="RESERVED30"/>
  35     <interrupt vector="31" address="$001E" name="RESERVED31"/>
  36     <interrupt vector="32" address="$001F" name="SPM READY">Store Program Memory Read</interrupt>
  37   </interrupts>
  38   <packages/>
  39   <memory>
  40     <flash size="8192"/>
  41     <iospace start="$0020" stop="$00FF"/>
  42     <sram size="512"/>
  43     <eram size="0"/>
  44   </memory>
  45   <ioregisters>
  46     <ioreg name="PINB" address="$03"/>
  47     <ioreg name="DDRB" address="$04"/>
  48     <ioreg name="PORTB" address="$05"/>
  49     <ioreg name="PINC" address="$06"/>
  50     <ioreg name="DDRC" address="$07"/>
  51     <ioreg name="PORTC" address="$08"/>
  52     <ioreg name="PIND" address="$09"/>
  53     <ioreg name="DDRD" address="$0A"/>
  54     <ioreg name="PORTD" address="$0B"/>
  55     <ioreg name="PINE" address="$0C"/>
  56     <ioreg name="DDRE" address="$0D"/>
  57     <ioreg name="PORTE" address="$0E"/>
  58     <ioreg name="TIFR0" address="$15"/>
  59     <ioreg name="TIFR1" address="$16"/>
  60     <ioreg name="GPIOR1" address="$19"/>
  61     <ioreg name="GPIOR2" address="$1A"/>
  62     <ioreg name="GPIOR3" address="$1B"/>
  63     <ioreg name="EIFR" address="$1C"/>
  64     <ioreg name="EIMSK" address="$1D"/>
  65     <ioreg name="GPIOR0" address="$1E"/>
  66     <ioreg name="EECR" address="$1F"/>
  67     <ioreg name="EEDR" address="$20"/>
  68     <ioreg name="EEARL" address="$21"/>
  69     <ioreg name="EEARH" address="$22"/>
  70     <ioreg name="GTCCR" address="$23"/>
  71     <ioreg name="TCCR0A" address="$24"/>
  72     <ioreg name="TCCR0B" address="$25"/>
  73     <ioreg name="TCNT0" address="$26"/>
  74     <ioreg name="OCR0A" address="$27"/>
  75     <ioreg name="OCR0B" address="$28"/>
  76     <ioreg name="PLLCSR" address="$29"/>
  77     <ioreg name="SPCR" address="$2C"/>
  78     <ioreg name="SPSR" address="$2D"/>
  79     <ioreg name="SPDR" address="$2E"/>
  80     <ioreg name="ACSR" address="$30"/>
  81     <ioreg name="SMCR" address="$33"/>
  82     <ioreg name="MCUSR" address="$34"/>
  83     <ioreg name="MCUCR" address="$35"/>
  84     <ioreg name="SPMCSR" address="$37"/>
  85     <ioreg name="SPL" address="$3D"/>
  86     <ioreg name="SPH" address="$3E"/>
  87     <ioreg name="SREG" address="$3F"/>
  88     <ioreg name="WDTCSR" address="$60"/>
  89     <ioreg name="CLKPR" address="$61"/>
  90     <ioreg name="PRR" address="$64"/>
  91     <ioreg name="OSCCAL" address="$66"/>
  92     <ioreg name="EICRA" address="$69"/>
  93     <ioreg name="TIMSK0" address="$6E"/>
  94     <ioreg name="TIMSK1" address="$6F"/>
  95     <ioreg name="AMP0CSR" address="$76"/>
  96     <ioreg name="AMP1CSR" address="$77"/>
  97     <ioreg name="ADCL" address="$78"/>
  98     <ioreg name="ADCH" address="$79"/>
  99     <ioreg name="ADCSRA" address="$7A"/>
 100     <ioreg name="ADCSRB" address="$7B"/>
 101     <ioreg name="ADMUX" address="$7C"/>
 102     <ioreg name="DIDR0" address="$7E"/>
 103     <ioreg name="DIDR1" address="$7F"/>
 104     <ioreg name="TCCR1A" address="$80"/>
 105     <ioreg name="TCCR1B" address="$81"/>
 106     <ioreg name="TCCR1C" address="$82"/>
 107     <ioreg name="TCNT1L" address="$84"/>
 108     <ioreg name="TCNT1H" address="$85"/>
 109     <ioreg name="ICR1L" address="$86"/>
 110     <ioreg name="ICR1H" address="$87"/>
 111     <ioreg name="OCR1AL" address="$88"/>
 112     <ioreg name="OCR1AH" address="$89"/>
 113     <ioreg name="OCR1BL" address="$8A"/>
 114     <ioreg name="OCR1BH" address="$8B"/>
 115     <ioreg name="PIFR0" address="$A0"/>
 116     <ioreg name="PIM0" address="$A1"/>
 117     <ioreg name="PIFR1" address="$A2"/>
 118     <ioreg name="PIM1" address="$A3"/>
 119     <ioreg name="PIFR2" address="$A4"/>
 120     <ioreg name="PIM2" address="$A5"/>
 121     <ioreg name="DACON" address="$AA"/>
 122     <ioreg name="DACL" address="$AB"/>
 123     <ioreg name="DACH" address="$AC"/>
 124     <ioreg name="AC0CON" address="$AD"/>
 125     <ioreg name="AC1CON" address="$AE"/>
 126     <ioreg name="AC2CON" address="$AF"/>
 127     <ioreg name="UCSRA" address="0xC0"/>
 128     <ioreg name="UCSRB" address="0xC1"/>
 129     <ioreg name="UCSRC" address="0xC2"/>
 130     <ioreg name="UBRRL" address="0xC4"/>
 131     <ioreg name="UBRRH" address="0xC5"/>
 132     <ioreg name="UDR" address="0xC6"/>
 133     <ioreg name="EUCSRA" address="0xC8"/>
 134     <ioreg name="EUCSRB" address="0xC9"/>
 135     <ioreg name="EUCSRC" address="0xCA"/>
 136     <ioreg name="MUBRRL" address="0xCC"/>
 137     <ioreg name="MUBRRH" address="0xCD"/>
 138     <ioreg name="EUDR" address="0xCE"/>
 139     <ioreg name="PSOC0" address="0xD0"/>
 140     <ioreg name="OCR0SAL" address="0xD2"/>
 141     <ioreg name="OCR0SAH" address="0xD3"/>
 142     <ioreg name="OCR0RAL" address="0xD4"/>
 143     <ioreg name="OCR0RAH" address="0xD5"/>
 144     <ioreg name="OCR0SBL" address="0xD6"/>
 145     <ioreg name="OCR0SBH" address="0xD7"/>
 146     <ioreg name="OCR0RBL" address="0xD8"/>
 147     <ioreg name="OCR0RBH" address="0xD9"/>
 148     <ioreg name="PCNF0" address="0xDA"/>
 149     <ioreg name="PCTL0" address="0xDB"/>
 150     <ioreg name="PFRC0A" address="0xDC"/>
 151     <ioreg name="PFRC0B" address="0xDD"/>
 152     <ioreg name="PICR0L" address="0xDE"/>
 153     <ioreg name="PICR0H" address="0xDF"/>
 154     <ioreg name="PSOC2" address="0xF0"/>
 155     <ioreg name="POM2" address="0xF1"/>
 156     <ioreg name="OCR2SAL" address="0xF2"/>
 157     <ioreg name="OCR2SAH" address="0xF3"/>
 158     <ioreg name="OCR2RAL" address="0xF4"/>
 159     <ioreg name="OCR2RAH" address="0xF5"/>
 160     <ioreg name="OCR2SBL" address="0xF6"/>
 161     <ioreg name="OCR2SBH" address="0xF7"/>
 162     <ioreg name="OCR2RBL" address="0xF8"/>
 163     <ioreg name="OCR2RBH" address="0xF9"/>
 164     <ioreg name="PCNF2" address="0xFA"/>
 165     <ioreg name="PCTL2" address="0xFB"/>
 166     <ioreg name="PFRC2A" address="0xFC"/>
 167     <ioreg name="PFRC2B" address="0xFD"/>
 168     <ioreg name="PICR2L" address="0xFE"/>
 169     <ioreg name="PICR2H" address="0xFF"/>
 170   </ioregisters>
 171   <hardware>
 172 <!--Everything after this needs editing!!!-->
 173     <module class="FUSE">
 174       <registers name="FUSE" memspace="FUSE">
 175           <reg size="1" name="EXTENDED" offset="0x02">
 176             <bitfield name="PSC2RB" mask="0x80" text="PSC2 Reset Behavior" icon=""/>
 177             <bitfield name="PSC1RB" mask="0x40" text="PSC1 Reset Behavior" icon=""/>
 178             <bitfield name="PSC0RB" mask="0x20" text="PSC0 Reset Behavior" icon=""/>
 179             <bitfield name="PSCRV" mask="0x10" text="PSCOUT Reset Value" icon=""/>
 180             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 181             <bitfield name="BOOTRST" mask="0x01" text="Select Reset Vector" icon=""/>
 182           </reg>
 183           <reg size="1" name="HIGH" offset="0x01">
 184             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PC6 as i/o pin)" icon=""/>
 185             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 186             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 187             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
 188             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 189             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector Trigger Level" icon="" enum="ENUM_BODLEVEL"/>
 190           </reg>
 191           <reg size="1" name="LOW" offset="0x00">
 192             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 193             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB0" icon=""/>
 194             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 195           </reg>
 196         </registers>
 197     </module>
 198     <module class="LOCKBIT">
 199       <registers name="LOCKBIT" memspace="LOCKBIT">
 200           <reg size="1" name="LOCKBIT" offset="0x00">
 201             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 202             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 203             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 204           </reg>
 205         </registers>
 206     </module>
 207     <module class="PORTB">
 208       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 209           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 210           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 211           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 212         </registers>
 213     </module>
 214     <module class="PORTD">
 215       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 216           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 217           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 218           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 219         </registers>
 220     </module>
 221     <module class="BOOT_LOAD">
 222       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 223           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 224             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 225             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 226             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 227             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 228             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 229             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 230             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 231           </reg>
 232         </registers>
 233     </module>
 234     <module class="EUSART">
 235       <registers name="EUSART" memspace="DATAMEM" text="" icon="io_com.bmp">
 236           <reg size="1" name="EUDR" offset="0xCE" text="EUSART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 237           <reg size="1" name="EUCSRA" offset="0xC8" text="EUSART Control and Status Register A" icon="io_flag.bmp">
 238             <bitfield name="UTxS" mask="0xF0" text="EUSART Control and Status Register A Bits" icon="" enum="COMM_TRANS_CHAR_SIZE"/>
 239             <bitfield name="URxS" mask="0x0F" text="EUSART Control and Status Register A Bits" icon="" enum="COMM_TRANS_CHAR_SIZE2"/>
 240           </reg>
 241           <reg size="1" name="EUCSRB" offset="0xC9" text="EUSART Control Register B" icon="io_flag.bmp">
 242             <bitfield name="EUSART" mask="0x10" text="EUSART Enable Bit" icon=""/>
 243             <bitfield name="EUSBS" mask="0x08" text="EUSBS Enable Bit" icon=""/>
 244             <bitfield name="EMCH" mask="0x02" text="Manchester Mode Bit" icon=""/>
 245             <bitfield name="BODR" mask="0x01" text="Order Bit" icon=""/>
 246           </reg>
 247           <reg size="1" name="EUCSRC" offset="0xCA" text="EUSART Status Register C" icon="io_flag.bmp">
 248             <bitfield name="FEM" mask="0x08" text="Frame Error Manchester Bit" icon=""/>
 249             <bitfield name="F1617" mask="0x04" text="F1617 Bit" icon=""/>
 250             <bitfield name="STP" mask="0x03" text="Stop Bits" icon=""/>
 251           </reg>
 252           <reg size="1" name="MUBRRH" offset="0xCD" text="Manchester Receiver Baud Rate Register High Byte" icon="io_com.bmp">
 253             <bitfield name="MUBRR" mask="0xFF" text="Manchester Receiver Baud Rate Register Bits" icon="" lsb="8"/>
 254           </reg>
 255           <reg size="1" name="MUBRRL" offset="0xCC" text="Manchester Receiver Baud Rate Register Low Byte" icon="io_com.bmp">
 256             <bitfield name="MUBRR" mask="0xFF" text="Manchester Receiver Baud Rate Register Bits" icon=""/>
 257           </reg>
 258         </registers>
 259     </module>
 260     <module class="ANALOG_COMPARATOR">
 261       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 262           <reg size="1" name="AC0CON" offset="0xAD" text="Analog Comparator 0 Control Register" icon="io_flag.bmp">
 263             <bitfield name="AC0EN" mask="0x80" text="Analog Comparator 0 Enable Bit" icon=""/>
 264             <bitfield name="AC0IE" mask="0x40" text="Analog Comparator 0 Interrupt Enable Bit" icon=""/>
 265             <bitfield name="AC0IS" mask="0x30" text="Analog Comparator 0  Interrupt Select Bit" icon=""/>
 266             <bitfield name="AC0M" mask="0x07" text="Analog Comparator 0 Multiplexer Register" icon=""/>
 267           </reg>
 268           <reg size="1" name="AC1CON" offset="0xAE" text="Analog Comparator 1 Control Register" icon="io_flag.bmp">
 269             <bitfield name="AC1EN" mask="0x80" text="Analog Comparator 1 Enable Bit" icon=""/>
 270             <bitfield name="AC1IE" mask="0x40" text="Analog Comparator 1 Interrupt Enable Bit" icon=""/>
 271             <bitfield name="AC1IS" mask="0x30" text="Analog Comparator 1  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 272             <bitfield name="AC1ICE" mask="0x08" text="Analog Comparator 1 Interrupt Capture Enable Bit" icon=""/>
 273             <bitfield name="AC1M" mask="0x07" text="Analog Comparator 1 Multiplexer Register" icon=""/>
 274           </reg>
 275           <reg size="1" name="AC2CON" offset="0xAF" text="Analog Comparator 2 Control Register" icon="io_flag.bmp">
 276             <bitfield name="AC2EN" mask="0x80" text="Analog Comparator 2 Enable Bit" icon=""/>
 277             <bitfield name="AC2IE" mask="0x40" text="Analog Comparator 2 Interrupt Enable Bit" icon=""/>
 278             <bitfield name="AC2IS" mask="0x30" text="Analog Comparator 2  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 279             <bitfield name="AC2M" mask="0x07" text="Analog Comparator 2 Multiplexer Register" icon=""/>
 280           </reg>
 281           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Status Register" icon="io_flag.bmp">
 282             <bitfield name="ACCKDIV" mask="0x80" text="Analog Comparator Clock Divider" icon=""/>
 283             <bitfield name="AC2IF" mask="0x40" text="Analog Comparator 2 Interrupt Flag Bit" icon=""/>
 284             <bitfield name="AC1IF" mask="0x20" text="Analog Comparator 1  Interrupt Flag Bit" icon=""/>
 285             <bitfield name="AC0IF" mask="0x10" text="Analog Comparator 0 Interrupt Flag Bit" icon=""/>
 286             <bitfield name="AC2O" mask="0x04" text="Analog Comparator 2 Output Bit" icon=""/>
 287             <bitfield name="AC1O" mask="0x02" text="Analog Comparator 1 Output Bit" icon=""/>
 288             <bitfield name="AC0O" mask="0x01" text="Analog Comparator 0 Output Bit" icon=""/>
 289           </reg>
 290         </registers>
 291     </module>
 292     <module class="DA_CONVERTER">
 293       <registers name="DA_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 294           <reg size="1" name="DACH" offset="0xAC" text="DAC Data Register High Byte" icon="io_analo.bmp">
 295             <bitfield name="DACH" mask="0xFF" text="DAC Data Register High Byte Bits" icon=""/>
 296           </reg>
 297           <reg size="1" name="DACL" offset="0xAB" text="DAC Data Register Low Byte" icon="io_analo.bmp">
 298             <bitfield name="DACL" mask="0xFF" text="DAC Data Register Low Byte Bits" icon=""/>
 299           </reg>
 300           <reg size="1" name="DACON" offset="0xAA" text="DAC Control Register" icon="io_analo.bmp">
 301             <bitfield name="DAATE" mask="0x80" text="DAC Auto Trigger Enable Bit" icon=""/>
 302             <bitfield name="DATS" mask="0x70" text="DAC Trigger Selection Bits" icon="" enum="ANALIG_DAC_AUTO_TRIGGER"/>
 303             <bitfield name="DALA" mask="0x04" text="DAC Left Adjust" icon=""/>
 304             <bitfield name="DAEN" mask="0x01" text="DAC Enable Bit" icon=""/>
 305           </reg>
 306         </registers>
 307     </module>
 308     <module class="CPU">
 309       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 310           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 311             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 312             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 313             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 314             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 315             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 316             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 317             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 318             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 319           </reg>
 320           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 321           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 322             <bitfield name="SPIPS" mask="0x80" text="SPI Pin Select" icon=""/>
 323             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 324             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 325             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 326           </reg>
 327           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 328             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 329             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 330             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 331             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 332           </reg>
 333           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0x7F"/>
 334           <reg size="1" name="CLKPR" offset="0x61" text="" icon="io_cpu.bmp">
 335             <bitfield name="CLKPCE" mask="0x80" text="" icon=""/>
 336             <bitfield name="CLKPS" mask="0x0F" text="" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 337           </reg>
 338           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 339             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS4"/>
 340             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 341           </reg>
 342           <reg size="1" name="GPIOR3" offset="0x3B" text="General Purpose IO Register 3" icon="io_cpu.bmp">
 343             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 3 bis" icon="" lsb="30"/>
 344           </reg>
 345           <reg size="1" name="GPIOR2" offset="0x3A" text="General Purpose IO Register 2" icon="io_cpu.bmp">
 346             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 2 bis" icon="" lsb="20"/>
 347           </reg>
 348           <reg size="1" name="GPIOR1" offset="0x39" text="General Purpose IO Register 1" icon="io_cpu.bmp">
 349             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 1 bis" icon="" lsb="10"/>
 350           </reg>
 351           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp">
 352             <bitfield name="GPIOR07" mask="0x80" text="General Purpose IO Register 0 bit 7" icon=""/>
 353             <bitfield name="GPIOR06" mask="0x40" text="General Purpose IO Register 0 bit 6" icon=""/>
 354             <bitfield name="GPIOR05" mask="0x20" text="General Purpose IO Register 0 bit 5" icon=""/>
 355             <bitfield name="GPIOR04" mask="0x10" text="General Purpose IO Register 0 bit 4" icon=""/>
 356             <bitfield name="GPIOR03" mask="0x08" text="General Purpose IO Register 0 bit 3" icon=""/>
 357             <bitfield name="GPIOR02" mask="0x04" text="General Purpose IO Register 0 bit 2" icon=""/>
 358             <bitfield name="GPIOR01" mask="0x02" text="General Purpose IO Register 0 bit 1" icon=""/>
 359             <bitfield name="GPIOR00" mask="0x01" text="General Purpose IO Register 0 bit 0" icon=""/>
 360           </reg>
 361           <reg size="1" name="PLLCSR" offset="0x49" text="PLL Control And Status Register" icon="io_sreg.bmp">
 362             <bitfield name="PLLF" mask="0x04" text="PLL Factor" icon=""/>
 363             <bitfield name="PLLE" mask="0x02" text="PLL Enable" icon=""/>
 364             <bitfield name="PLOCK" mask="0x01" text="PLL Lock Detector" icon=""/>
 365           </reg>
 366           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 367             <bitfield name="PRPSC" mask="0xE0" text="Power Reduction PSC2" icon=""/>
 368             <bitfield name="PRTIM1" mask="0x10" text="Power Reduction Timer/Counter1" icon=""/>
 369             <bitfield name="PRTIM0" mask="0x08" text="Power Reduction Timer/Counter0" icon=""/>
 370             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 371             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 372             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 373           </reg>
 374         </registers>
 375     </module>
 376     <module class="PORTE">
 377       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 378           <reg size="1" name="PORTE" offset="0x2E" text="Port E Data Register" icon="io_port.bmp" mask="0x07"/>
 379           <reg size="1" name="DDRE" offset="0x2D" text="Port E Data Direction Register" icon="io_flag.bmp" mask="0x07"/>
 380           <reg size="1" name="PINE" offset="0x2C" text="Port E Input Pins" icon="io_port.bmp" mask="0x07"/>
 381         </registers>
 382     </module>
 383     <module class="TIMER_COUNTER_0">
 384       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 385           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 386             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 387             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 388             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 389           </reg>
 390           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 391             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 392             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 393             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 394           </reg>
 395           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 396             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 397             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 398             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 399           </reg>
 400           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 401             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 402             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 403             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 404             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 405           </reg>
 406           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 407           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 408           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 409           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 410             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 411             <bitfield name="ICPSEL1" mask="0x40" text="Timer1 Input Capture Selection Bit" icon=""/>
 412             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 413           </reg>
 414         </registers>
 415     </module>
 416     <module class="TIMER_COUNTER_1">
 417       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 418           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 419             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 420             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 421             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 422             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 423           </reg>
 424           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 425             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 426             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 427             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 428             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 429           </reg>
 430           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 431             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 432             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 433             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 434           </reg>
 435           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 436             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 437             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 438             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 439             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 440           </reg>
 441           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter1 Control Register C" icon="io_flag.bmp">
 442             <bitfield name="FOC1A" mask="0x80" text="" icon=""/>
 443             <bitfield name="FOC1B" mask="0x40" text="" icon=""/>
 444           </reg>
 445           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 446           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 447           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 448           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 449           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 450             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 451             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 452           </reg>
 453         </registers>
 454     </module>
 455     <module class="AD_CONVERTER">
 456       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 457           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 458             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 459             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 460             <bitfield name="MUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 461           </reg>
 462           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 463             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 464             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 465             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 466             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 467             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 468             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon=""/>
 469           </reg>
 470           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 471           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp" mask="0x9F"/>
 472           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp" mask="0xFF"/>
 473           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 0" icon="">
 474             <bitfield name="ACMP0D" mask="0x20" text="" icon=""/>
 475             <bitfield name="AMP0PD" mask="0x10" text="" icon=""/>
 476             <bitfield name="AMP0ND" mask="0x08" text="" icon=""/>
 477             <bitfield name="ADC10D" mask="0x04" text="" icon=""/>
 478             <bitfield name="ADC9D" mask="0x02" text="" icon=""/>
 479             <bitfield name="ADC8D" mask="0x01" text="" icon=""/>
 480           </reg>
 481           <reg size="1" name="AMP0CSR" offset="0x76" text="" icon="io_analo.bmp">
 482             <bitfield name="AMP0EN" mask="0x80" text="" icon=""/>
 483             <bitfield name="AMP0IS" mask="0x40" text="" icon=""/>
 484             <bitfield name="AMP0G" mask="0x30" text="" icon=""/>
 485             <bitfield name="AMP0TS" mask="0x03" text="" icon=""/>
 486           </reg>
 487           <reg size="1" name="AMP1CSR" offset="0x77" text="" icon="io_analo.bmp">
 488             <bitfield name="AMP1EN" mask="0x80" text="" icon=""/>
 489             <bitfield name="AMP1IS" mask="0x40" text="" icon=""/>
 490             <bitfield name="AMP1G" mask="0x30" text="" icon=""/>
 491             <bitfield name="AMP1TS" mask="0x03" text="" icon=""/>
 492           </reg>
 493         </registers>
 494     </module>
 495     <module class="USART">
 496       <registers name="USART" memspace="DATAMEM" text="" icon="io_com.bmp">
 497           <reg size="1" name="UDR" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 498           <reg size="1" name="UCSRA" offset="0xC0" text="USART Control and Status register A" icon="io_flag.bmp">
 499             <bitfield name="RXC" mask="0x80" text="USART Receive Complete" icon=""/>
 500             <bitfield name="TXC" mask="0x40" text="USART Transmitt Complete" icon=""/>
 501             <bitfield name="UDRE" mask="0x20" text="USART Data Register Empty" icon=""/>
 502             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 503             <bitfield name="DOR" mask="0x08" text="Data Overrun" icon=""/>
 504             <bitfield name="UPE" mask="0x04" text="USART Parity Error" icon=""/>
 505             <bitfield name="U2X" mask="0x02" text="Double USART Transmission Bit" icon=""/>
 506             <bitfield name="MPCM" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 507           </reg>
 508           <reg size="1" name="UCSRB" offset="0xC1" text="USART Control an Status register B" icon="io_flag.bmp">
 509             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 510             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 511             <bitfield name="UDRIE" mask="0x20" text="USART Data Register Empty Interrupt Enable" icon=""/>
 512             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 513             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 514             <bitfield name="UCSZ2" mask="0x04" text="Character Size" icon=""/>
 515             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 516             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 517           </reg>
 518           <reg size="1" name="UCSRC" offset="0xC2" text="USART Control an Status register C" icon="io_flag.bmp">
 519             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon=""/>
 520             <bitfield name="UPM" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 521             <bitfield name="USBS" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 522             <bitfield name="UCSZ" mask="0x06" text="Character Size Bits" icon=""/>
 523             <bitfield name="UCPOL" mask="0x01" text="Clock Polarity" icon=""/>
 524           </reg>
 525           <reg size="1" name="UBRRH" offset="0xC5" text="USART Baud Rate Register High Byte" icon="io_com.bmp">
 526             <bitfield name="UBRR" mask="0x0F" text="USART Baud Rate Register Bits" icon="" lsb="8"/>
 527           </reg>
 528           <reg size="1" name="UBRRL" offset="0xC4" text="USART Baud Rate Register Low Byte" icon="io_com.bmp">
 529             <bitfield name="UBRR" mask="0xFF" text="USART Baud Rate Register bits" icon=""/>
 530           </reg>
 531         </registers>
 532     </module>
 533     <module class="SPI">
 534       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 535           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 536             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 537             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 538             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 539             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 540             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 541             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 542             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 543           </reg>
 544           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 545             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 546             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 547             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 548           </reg>
 549           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 550         </registers>
 551     </module>
 552     <module class="WATCHDOG">
 553       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 554           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 555             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 556             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 557             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 558             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 559             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 560           </reg>
 561         </registers>
 562     </module>
 563     <module class="EXTERNAL_INTERRUPT">
 564       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 565           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 566             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 567             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 568             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 569           </reg>
 570           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 571             <bitfield name="INT" mask="0x07" text="External Interrupt Request 2 Enable" icon=""/>
 572           </reg>
 573           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 574             <bitfield name="INTF" mask="0x07" text="External Interrupt Flags" icon=""/>
 575           </reg>
 576         </registers>
 577     </module>
 578     <module class="EEPROM">
 579       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 580           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x0FFF"/>
 581           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 582           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 583             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 584             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 585             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 586             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 587           </reg>
 588         </registers>
 589     </module>
 590     <module class="PSC0">
 591       <registers name="PSC0" memspace="DATAMEM" text="" icon="io_com.bmp">
 592           <reg size="2" name="PICR0" offset="0xDE" text="PSC 0 Input Capture Register " icon="register.bmp" mask="0x8FFF"/>
 593           <reg size="1" name="PFRC0B" offset="0xDD" text="PSC 0 Input B Control" icon="register.bmp">
 594             <bitfield name="PCAE0B" mask="0x80" text="PSC 0 Capture Enable Input Part B" icon=""/>
 595             <bitfield name="PISEL0B" mask="0x40" text="PSC 0 Input Select for Part B" icon=""/>
 596             <bitfield name="PELEV0B" mask="0x20" text="PSC 0 Edge Level Selector on Input Part B" icon=""/>
 597             <bitfield name="PFLTE0B" mask="0x10" text="PSC 0 Filter Enable on Input Part B" icon=""/>
 598             <bitfield name="PRFM0B" mask="0x0F" text="PSC 0 Retrigger and Fault Mode for Part B" icon=""/>
 599           </reg>
 600           <reg size="1" name="PFRC0A" offset="0xDC" text="PSC 0 Input A Control" icon="register.bmp">
 601             <bitfield name="PCAE0A" mask="0x80" text="PSC 0 Capture Enable Input Part A" icon=""/>
 602             <bitfield name="PISEL0A" mask="0x40" text="PSC 0 Input Select for Part A" icon=""/>
 603             <bitfield name="PELEV0A" mask="0x20" text="PSC 0 Edge Level Selector on Input Part A" icon=""/>
 604             <bitfield name="PFLTE0A" mask="0x10" text="PSC 0 Filter Enable on Input Part A" icon=""/>
 605             <bitfield name="PRFM0A" mask="0x0F" text="PSC 0 Retrigger and Fault Mode for Part A" icon=""/>
 606           </reg>
 607           <reg size="1" name="PCTL0" offset="0xDB" text="PSC 0 Control Register" icon="register.bmp">
 608             <bitfield name="PPRE0" mask="0xC0" text="PSC 0 Prescaler Selects" icon=""/>
 609             <bitfield name="PBFM0" mask="0x20" text="PSC 0 Balance Flank Width Modulation" icon=""/>
 610             <bitfield name="PAOC0B" mask="0x10" text="PSC 0 Asynchronous Output Control B" icon=""/>
 611             <bitfield name="PAOC0A" mask="0x08" text="PSC 0 Asynchronous Output Control A" icon=""/>
 612             <bitfield name="PARUN0" mask="0x04" text="PSC0 Auto Run" icon=""/>
 613             <bitfield name="PCCYC0" mask="0x02" text="PSC0 Complete Cycle" icon=""/>
 614             <bitfield name="PRUN0" mask="0x01" text="PSC 0 Run" icon=""/>
 615           </reg>
 616           <reg size="1" name="PCNF0" offset="0xDA" text="PSC 0 Configuration Register" icon="register.bmp">
 617             <bitfield name="PFIFTY0" mask="0x80" text="PSC 0 Fifty" icon=""/>
 618             <bitfield name="PALOCK0" mask="0x40" text="PSC 0 Autolock" icon=""/>
 619             <bitfield name="PLOCK0" mask="0x20" text="PSC 0 Lock" icon=""/>
 620             <bitfield name="PMODE0" mask="0x18" text="PSC 0 Mode" icon=""/>
 621             <bitfield name="POP0" mask="0x04" text="PSC 0 Output Polarity" icon=""/>
 622             <bitfield name="PCLKSEL0" mask="0x02" text="PSC 0 Input Clock Select" icon=""/>
 623           </reg>
 624           <reg size="2" name="OCR0RB" offset="0xD8" text="Output Compare RB Register " icon="register.bmp" mask="0xFFFF"/>
 625           <reg size="2" name="OCR0SB" offset="0xD6" text="Output Compare SB Register " icon="register.bmp" mask="0x0FFF"/>
 626           <reg size="2" name="OCR0RA" offset="0xD4" text="Output Compare RA Register " icon="register.bmp" mask="0x0FFF"/>
 627           <reg size="2" name="OCR0SA" offset="0xD2" text="Output Compare SA Register " icon="register.bmp" mask="0x0FFF"/>
 628           <reg size="1" name="PSOC0" offset="0xD0" text="PSC0 Synchro and Output Configuration" icon="register.bmp">
 629             <bitfield name="PSYNC0" mask="0x30" text="Synchronization Out for ADC Selection" icon=""/>
 630             <bitfield name="POEN0B" mask="0x04" text="PSCOUT01 Output Enable" icon=""/>
 631             <bitfield name="POEN0A" mask="0x01" text="PSCOUT00 Output Enable" icon=""/>
 632           </reg>
 633           <reg size="1" name="PIM0" offset="0xA1" text="PSC0 Interrupt Mask Register" icon="register.bmp">
 634             <bitfield name="PSEIE0" mask="0x20" text="PSC 0 Synchro Error Interrupt Enable" icon=""/>
 635             <bitfield name="PEVE0B" mask="0x10" text="External Event B Interrupt Enable" icon=""/>
 636             <bitfield name="PEVE0A" mask="0x08" text="External Event A Interrupt Enable" icon=""/>
 637             <bitfield name="PEOPE0" mask="0x01" text="End of Cycle Interrupt Enable" icon=""/>
 638           </reg>
 639           <reg size="1" name="PIFR0" offset="0xA0" text="PSC0 Interrupt Flag Register" icon="register.bmp">
 640             <bitfield name="POAC0B" mask="0x80" text="PSC 0 Output A Activity" icon=""/>
 641             <bitfield name="POAC0A" mask="0x40" text="PSC 0 Output A Activity" icon=""/>
 642             <bitfield name="PSEI0" mask="0x20" text="PSC 0 Synchro Error Interrupt" icon=""/>
 643             <bitfield name="PEV0B" mask="0x10" text="External Event B Interrupt" icon=""/>
 644             <bitfield name="PEV0A" mask="0x08" text="External Event A Interrupt" icon=""/>
 645             <bitfield name="PRN0" mask="0x06" text="Ramp Number" icon=""/>
 646             <bitfield name="PEOP0" mask="0x01" text="End of PSC0 Interrupt" icon=""/>
 647           </reg>
 648         </registers>
 649     </module>
 650     <module class="PSC2">
 651       <registers name="PSC2" memspace="DATAMEM" text="" icon="io_com.bmp">
 652           <reg size="2" name="PICR2" offset="0xFE" text="PSC 2 Input Capture Register " icon="register.bmp" mask="0x8FFF"/>
 653           <reg size="1" name="PFRC2B" offset="0xFD" text="PSC 2 Input B Control" icon="register.bmp">
 654             <bitfield name="PCAE2B" mask="0x80" text="PSC 2 Capture Enable Input Part B" icon=""/>
 655             <bitfield name="PISEL2B" mask="0x40" text="PSC 2 Input Select for Part B" icon=""/>
 656             <bitfield name="PELEV2B" mask="0x20" text="PSC 2 Edge Level Selector on Input Part B" icon=""/>
 657             <bitfield name="PFLTE2B" mask="0x10" text="PSC 2 Filter Enable on Input Part B" icon=""/>
 658             <bitfield name="PRFM2B" mask="0x0F" text="PSC 2 Retrigger and Fault Mode for Part B" icon=""/>
 659           </reg>
 660           <reg size="1" name="PFRC2A" offset="0xFC" text="PSC 2 Input B Control" icon="register.bmp">
 661             <bitfield name="PCAE2A" mask="0x80" text="PSC 2 Capture Enable Input Part A" icon=""/>
 662             <bitfield name="PISEL2A" mask="0x40" text="PSC 2 Input Select for Part A" icon=""/>
 663             <bitfield name="PELEV2A" mask="0x20" text="PSC 2 Edge Level Selector on Input Part A" icon=""/>
 664             <bitfield name="PFLTE2A" mask="0x10" text="PSC 2 Filter Enable on Input Part A" icon=""/>
 665             <bitfield name="PRFM2A" mask="0x0F" text="PSC 2 Retrigger and Fault Mode for Part A" icon=""/>
 666           </reg>
 667           <reg size="1" name="PCTL2" offset="0xFB" text="PSC 2 Control Register" icon="register.bmp">
 668             <bitfield name="PPRE2" mask="0xC0" text="PSC 2 Prescaler Selects" icon=""/>
 669             <bitfield name="PBFM2" mask="0x20" text="Balance Flank Width Modulation" icon=""/>
 670             <bitfield name="PAOC2B" mask="0x10" text="PSC 2 Asynchronous Output Control B" icon=""/>
 671             <bitfield name="PAOC2A" mask="0x08" text="PSC 2 Asynchronous Output Control A" icon=""/>
 672             <bitfield name="PARUN2" mask="0x04" text="PSC2 Auto Run" icon=""/>
 673             <bitfield name="PCCYC2" mask="0x02" text="PSC2 Complete Cycle" icon=""/>
 674             <bitfield name="PRUN2" mask="0x01" text="PSC 2 Run" icon=""/>
 675           </reg>
 676           <reg size="1" name="PCNF2" offset="0xFA" text="PSC 2 Configuration Register" icon="register.bmp">
 677             <bitfield name="PFIFTY2" mask="0x80" text="PSC 2 Fifty" icon=""/>
 678             <bitfield name="PALOCK2" mask="0x40" text="PSC 2 Autolock" icon=""/>
 679             <bitfield name="PLOCK2" mask="0x20" text="PSC 2 Lock" icon=""/>
 680             <bitfield name="PMODE2" mask="0x18" text="PSC 2 Mode" icon=""/>
 681             <bitfield name="POP2" mask="0x04" text="PSC 2 Output Polarity" icon=""/>
 682             <bitfield name="PCLKSEL2" mask="0x02" text="PSC 2 Input Clock Select" icon=""/>
 683             <bitfield name="POME2" mask="0x01" text="PSC 2 Output Matrix Enable" icon=""/>
 684           </reg>
 685           <reg size="2" name="OCR2RB" offset="0xF8" text="Output Compare RB Register " icon="register.bmp" mask="0xFFFF"/>
 686           <reg size="2" name="OCR2SB" offset="0xF6" text="Output Compare SB Register " icon="register.bmp" mask="0x0FFF"/>
 687           <reg size="2" name="OCR2RA" offset="0xF4" text="Output Compare RA Register " icon="register.bmp" mask="0x0FFF"/>
 688           <reg size="2" name="OCR2SA" offset="0xF2" text="Output Compare SA Register " icon="register.bmp" mask="0x0FFF"/>
 689           <reg size="1" name="POM2" offset="0xF1" text="PSC 2 Output Matrix" icon="register.bmp">
 690             <bitfield name="POMV2B" mask="0xF0" text="Output Matrix Output B Ramps" icon=""/>
 691             <bitfield name="POMV2A" mask="0x0F" text="Output Matrix Output A Ramps" icon=""/>
 692           </reg>
 693           <reg size="1" name="PSOC2" offset="0xF0" text="PSC2 Synchro and Output Configuration" icon="register.bmp">
 694             <bitfield name="POS2" mask="0xC0" text="PSC 2 Output 23 Select" icon="" lsb="2"/>
 695             <bitfield name="PSYNC2_" mask="0x30" text="Synchronization Out for ADC Selection" icon=""/>
 696             <bitfield name="POEN2D" mask="0x08" text="PSCOUT23 Output Enable" icon=""/>
 697             <bitfield name="POEN2B" mask="0x04" text="PSCOUT21 Output Enable" icon=""/>
 698             <bitfield name="POEN2C" mask="0x02" text="PSCOUT22 Output Enable" icon=""/>
 699             <bitfield name="POEN2A" mask="0x01" text="PSCOUT20 Output Enable" icon=""/>
 700           </reg>
 701           <reg size="1" name="PIM2" offset="0xA5" text="PSC2 Interrupt Mask Register" icon="register.bmp">
 702             <bitfield name="PSEIE2" mask="0x20" text="PSC 2 Synchro Error Interrupt Enable" icon=""/>
 703             <bitfield name="PEVE2B" mask="0x10" text="External Event B Interrupt Enable" icon=""/>
 704             <bitfield name="PEVE2A" mask="0x08" text="External Event A Interrupt Enable" icon=""/>
 705             <bitfield name="PEOPE2" mask="0x01" text="End of Cycle Interrupt Enable" icon=""/>
 706           </reg>
 707           <reg size="1" name="PIFR2" offset="0xA4" text="PSC2 Interrupt Flag Register" icon="register.bmp">
 708             <bitfield name="POAC2B" mask="0x80" text="PSC 2 Output A Activity" icon=""/>
 709             <bitfield name="POAC2A" mask="0x40" text="PSC 2 Output A Activity" icon=""/>
 710             <bitfield name="PSEI2" mask="0x20" text="PSC 2 Synchro Error Interrupt" icon=""/>
 711             <bitfield name="PEV2B" mask="0x10" text="External Event B Interrupt" icon=""/>
 712             <bitfield name="PEV2A" mask="0x08" text="External Event A Interrupt" icon=""/>
 713             <bitfield name="PRN2" mask="0x06" text="Ramp Number" icon=""/>
 714             <bitfield name="PEOP2" mask="0x01" text="End of PSC2 Interrupt" icon=""/>
 715           </reg>
 716         </registers>
 717     </module>
 718   </hardware>
 719 </device>