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Bug fix: check if vm exists
[avr-sim.git] / Instructions.h
blob01772158740f42fb58885f2842e36b594233fc8d
1 #ifndef AVR_INSTRUCTIONS_H
2 #define AVR_INSTRUCTIONS_H
3
4 #include "Instruction.h"
5 #include "Types.h"
6
7 #include <iostream>
8
9 namespace avr {
10
11 class Register;
12 class Core;
13
14 namespace op {
15
16 class ADC : public Instruction {
17 /*
18 * Add with Carry.
19 *
20 * Opcode : 0001 11rd dddd rrrr
21 * Usage : ADC Rd, Rr
22 * Operation : Rd <- Rd + Rr + C
23 * Flags : Z,C,N,V,S,H
24 * Num Clocks : 1
25 */
26
27 public:
28 ADC(word opcode);
29
30 public:
31 int operator()(Core *core);
32 int trace(Core *core, std::ostream & ostr);
33
34 protected:
35 unsigned char Rd;
36 unsigned char Rr;
37 unsigned char S;
38
39 };
40
41 class ADD : public Instruction {
42 /*
43 * Add without Carry.
44 *
45 * Opcode : 0000 11rd dddd rrrr
46 * Usage : ADD Rd, Rr
47 * Operation : Rd <- Rd + Rr
48 * Flags : Z,C,N,V,S,H
49 * Num Clocks : 1
50 */
51
52 public:
53 ADD(word opcode);
54
55 public:
56 int operator ()(Core *core);
57 int trace(Core *core, std::ostream & ostr);
58
59 protected:
60 unsigned char Rd;
61 unsigned char Rr;
62 unsigned char S;
63 };
64
65 class ADIW : public Instruction {
66 /*
67 * Add Immediate to Word.
68 *
69 * Opcode : 1001 0110 KKdd KKKK
70 * Usage : ADIW Rd, K
71 * Operation : Rd+1:Rd <- Rd+1:Rd + K
72 * Flags : Z,C,N,V,S
73 * Num Clocks : 2
74 */
75
76 public:
77 ADIW(word opcode);
78
79 public:
80 int operator ()(Core *core);
81 int trace(Core *core, std::ostream & ostr);
82
83 protected:
84 unsigned char Rl;
85 unsigned char Rh;
86 unsigned char K;
87 unsigned char S;
88 };
89
90 class AND : public Instruction {
91 /*
92 * Logical AND.
93 *
94 * Opcode : 0010 00rd dddd rrrr
95 * Usage : AND Rd, Rr
96 * Operation : Rd <- Rd & Rr
97 * Flags : Z,N,V,S
98 * Num Clocks : 1
99 */
100
101 public:
102 AND(word opcode);
103
104 public:
105 int operator()(Core *core);
106 int trace(Core *core, std::ostream & ostr);
107
108 protected:
109 unsigned char Rd;
110 unsigned char Rr;
111 unsigned char S;
112 };
113
114 class ANDI : public Instruction {
115 /*
116 * Logical AND with Immed.
117 *
118 * Opcode : 0111 KKKK dddd KKKK
119 * Usage : ANDI Rd, K
120 * Operation : Rd <- Rd & K
121 * Flags : Z,N,V,S
122 * Num Clocks : 1
123 */
124
125 public:
126 ANDI(word opcode);
127
128 public:
129 int operator()(Core *core);
130 int trace(Core *core, std::ostream & ostr);
131
132 protected:
133 unsigned char Rd;
134 unsigned char K;
135 unsigned char S;
136 };
137
138 class ASR : public Instruction {
139 /*
140 * Arithmetic Shift Right.
141 *
142 * Opcode : 1001 010d dddd 0101
143 * Usage : ASR Rd
144 * Operation : Rd(n) <- Rd(n+1), n=0..6
145 * Flags : Z,C,N,V,S
146 * Num Clocks : 1
147 */
148
149 public:
150 ASR(word opcode);
151
152 public:
153 int operator()(Core *core);
154 int trace(Core *core, std::ostream & ostr);
155
156 protected:
157 unsigned char Rd;
158 unsigned char S;
159 };
160
161 class BCLR : public Instruction {
162 /*
163 * Clear a single flag or bit in SREG.
164 *
165 * Opcode : 1001 0100 1sss 1000
166 * Usage : BCLR
167 * Operation : SREG(s) <- 0
168 * Flags : SREG(s)
169 * Num Clocks : 1
170 */
171
172 public:
173 BCLR(word opcode);
174
175 public:
176 int operator()(Core *core);
177 int trace(Core *core, std::ostream & ostr);
178
179 protected:
180 unsigned char K;
181 unsigned char S;
182 };
183
184 class BLD : public Instruction {
185 /* Bit load from T to Register.
186 *
187 * Opcode : 1111 100d dddd 0bbb
188 * Usage : BLD Rd, b
189 * Operation : Rd(b) <- T
190 * Flags : None
191 * Num Clocks : 1
192 */
193
194 public:
195 BLD(word opcode);
196
197 public:
198 int operator()(Core *core);
199 int trace(Core *core, std::ostream & ostr);
200
201 protected:
202 unsigned char Rd;
203 unsigned char Kadd, Kremove;
204 unsigned char S;
205 };
206
207 class BRBC : public Instruction {
208 /*
209 * Branch if Status Flag Cleared.
210 *
211 * Pass control directly to the specific bit operation.
212 *
213 * Opcode : 1111 01kk kkkk ksss
214 * Usage : BRBC s, k
215 * Operation : if (SREG(s) = 0) then PC <- PC + k + 1
216 * Flags : None
217 * Num Clocks : 1 / 2
218 *
219 * k is an relative address represented in two's complements.
220 * (64 < k <= 64)
221 */
222
223 public:
224 BRBC(word opcode);
225
226 public:
227 int operator()(Core *core);
228 int trace(Core *core, std::ostream & ostr);
229
230 protected:
231 unsigned char bitmask;
232 signed char offset;
233 unsigned char S;
234 };
235
236 class BRBS : public Instruction {
237 /*
238 * Branch if Status Flag Set.
239 *
240 * Pass control directly to the specific bit operation.
241 *
242 * Opcode : 1111 00kk kkkk ksss
243 * Usage : BRBS s, k
244 * Operation : if (SREG(s) = 1) then PC <- PC + k + 1
245 * Flags : None
246 * Num Clocks : 1 / 2
247 *
248 * k is an relative address represented in two's complements.
249 * (64 < k <= 64)
250 */
251
252 public:
253 BRBS(word opcode);
254
255 public:
256 int operator()(Core *core);
257 int trace(Core *core, std::ostream & ostr);
258
259 protected:
260 unsigned char bitmask;
261 signed char offset;
262 unsigned char S;
263 };
264
265 class BSET : public Instruction {
266 /*
267 * Set a single flag or bit in SREG.
268 *
269 * Opcode : 1001 0100 0sss 1000
270 * Usage : BSET
271 * Operation : SREG(s) <- 1
272 * Flags : SREG(s)
273 * Num Clocks : 1
274 */
275
276 public:
277 BSET(word opcode);
278
279 public:
280 int operator()(Core *core);
281 int trace(Core *core, std::ostream & ostr);
282
283 protected:
284 unsigned char K;
285 unsigned char S;
286 };
287
288 class BST:public Instruction
289 {
290 /*
291 * Bit Store from Register to T.
292 *
293 * Opcode : 1111 101d dddd 0bbb
294 * Usage : BST Rd, b
295 * Operation : T <- Rd(b)
296 * Flags : T
297 * Num Clocks : 1
298 */
299
300 public:
301 BST(word opcode);
302
303 public:
304 int operator()(Core *core);
305 int trace(Core *core, std::ostream & ostr);
306
307 protected:
308 unsigned char Rd;
309 unsigned char K;
310 unsigned char S;
311
312 };
313
314 class CALL : public Instruction {
315 /*
316 * Call Subroutine.
317 *
318 * Opcode : 1001 010k kkkk 111k kkkk kkkk kkkk kkkk
319 * Usage : CALL k
320 * Operation : PC <- k
321 * Flags : None
322 * Num Clocks : 4 / 5
323 */
324
325 public:
326 CALL(word opcode);
327
328 public:
329 int operator()(Core *core);
330 int trace(Core *core, std::ostream & ostr);
331 bool is2Word() const { return true; }
332
333 protected:
334 unsigned char KH;
335 };
336
337 class CBI : public Instruction {
338 /*
339 * Clear Bit in I/O Register.
340 *
341 * Opcode : 1001 1000 AAAA Abbb
342 * Usage : CBI A, b
343 * Operation : I/O(A, b) <- 0
344 * Flags : None
345 * Num Clocks : 2
346 */
347
348 public:
349 CBI (word opcode);
350 int operator()(Core *core);
351 int trace(Core *core, std::ostream & ostr);
352
353 protected:
354 unsigned char ioreg;
355 unsigned char K;
356 };
357
358 class COM : public Instruction {
359 /*
360 * One's Complement.
361 *
362 * Opcode : 1001 010d dddd 0000
363 * Usage : COM Rd
364 * Operation : Rd <- $FF - Rd
365 * Flags : Z,C,N,V,S
366 * Num Clocks : 1
367 */
368
369 public:
370 COM (word opcode);
371
372 public:
373 int operator()(Core *core);
374 int trace(Core *core, std::ostream & ostr);
375
376 protected:
377 unsigned char Rd;
378 unsigned char S;
379 };
380
381 class CP : public Instruction {
382 /*
383 * Compare.
384 *
385 * Opcode : 0001 01rd dddd rrrr
386 * Usage : CP Rd, Rr
387 * Operation : Rd - Rr
388 * Flags : Z,C,N,V,S,H
389 * Num Clocks : 1
390 */
391
392 public:
393 CP (word opcode);
394
395 public:
396 int operator()(Core *core);
397 int trace(Core *core, std::ostream & ostr);
398
399 protected:
400 unsigned char Rd;
401 unsigned char Rr;
402 unsigned char S;
403 };
404
405 class CPC : public Instruction {
406 /*
407 * Compare with Carry.
408 *
409 * Opcode : 0000 01rd dddd rrrr
410 * Usage : CPC Rd, Rr
411 * Operation : Rd - Rr - C
412 * Flags : Z,C,N,V,S,H
413 * Num Clocks : 1
414 */
415
416 public:
417 CPC (word opcode);
418 int operator()(Core *core);
419 int trace(Core *core, std::ostream & ostr);
420
421 protected:
422 unsigned char Rd;
423 unsigned char Rr;
424 unsigned char S;
425 };
426
427 class CPI : public Instruction {
428 /*
429 * Compare with Immediate.
430 *
431 * Opcode : 0011 KKKK dddd KKKK
432 * Usage : CPI Rd, K
433 * Operation : Rd - K
434 * Flags : Z,C,N,V,S,H
435 * Num Clocks : 1
436 */
437
438 public:
439 CPI (word opcode);
440
441 public:
442 int operator()(Core *core);
443 int trace(Core *core, std::ostream & ostr);
444
445
446 protected:
447 unsigned char Rd;
448 unsigned char K;
449 unsigned char S;
450 };
451
452 class CPSE : public Instruction {
453 /*
454 * Compare, Skip if Equal.
455 *
456 * Opcode : 0001 00rd dddd rrrr
457 * Usage : CPSE Rd, Rr
458 * Operation : if (Rd = Rr) PC <- PC + 2 or 3
459 * Flags : None
460 * Num Clocks : 1 / 2 / 3
461 */
462
463 public:
464 CPSE (word opcode);
465
466 public:
467 int operator()(Core *core);
468 int trace(Core *core, std::ostream & ostr);
469
470 protected:
471 unsigned char Rd;
472 unsigned char Rr;
473 unsigned char S;
474 };
475
476 class DEC : public Instruction {
477 /*
478 * Decrement.
479 *
480 * Opcode : 1001 010d dddd 1010
481 * Usage : DEC Rd
482 * Operation : Rd <- Rd - 1
483 * Flags : Z,N,V,S
484 * Num Clocks : 1
485 */
486
487 public:
488 DEC (word opcode);
489 int operator()(Core *core);
490 int trace(Core *core, std::ostream & ostr);
491
492 protected:
493 unsigned char Rd;
494 unsigned char S;
495 };
496
497 class EICALL : public Instruction {
498 /*
499 * Extended Indirect Call to (Z).
500 *
501 * Opcode : 1001 0101 0001 1001
502 * Usage : EICALL
503 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
504 * Flags : None
505 * Num Clocks : 4
506 */
507
508 public:
509 EICALL(word opcode);
510
511 public:
512 int operator()(Core *core);
513 int trace(Core *core, std::ostream & ostr);
514
515 protected:
516 unsigned char Rl;
517 unsigned char Rh;
518 unsigned char eind;
519 };
520
521 class EIJMP : public Instruction {
522 /*
523 * Extended Indirect Jmp to (Z).
524 *
525 * Opcode : 1001 0100 0001 1001
526 * Usage : EIJMP
527 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
528 * Flags : None
529 * Num Clocks : 2
530 */
531
532 public:
533 EIJMP (word opcode);
534
535 public:
536 int operator()(Core *core);
537 int trace(Core *core, std::ostream & ostr);
538
539 protected:
540 unsigned char Rl;
541 unsigned char Rh;
542 unsigned char eind;
543 };
544
545 class ELPM_Z : public Instruction {
546 /*
547 * Extended Load Program Memory.
548 *
549 * Opcode : 1001 000d dddd 0110
550 * Usage : ELPM Rd, Z
551 * Operation : R <- (RAMPZ:Z)
552 * Flags : None
553 * Num Clocks : 3
554 */
555
556 public:
557 ELPM_Z (word opcode);
558
559 public:
560 int operator()(Core *core);
561 int trace(Core *core, std::ostream & ostr);
562
563 protected:
564 unsigned char Rl;
565 unsigned char Rh;
566 unsigned char Rd;
567 };
568
569 class ELPM_Z_incr:public Instruction {
570 /*
571 * Extended Ld Prg Mem and Post-Incr.
572 *
573 * Opcode : 1001 000d dddd 0111
574 * Usage : ELPM Rd, Z+
575 * Operation : Rd <- (RAMPZ:Z), Z <- Z + 1
576 * Flags : None
577 * Num Clocks : 3
578 */
579
580 public:
581 ELPM_Z_incr(word opcode);
582
583 public:
584 int operator()(Core *core);
585 int trace(Core *core, std::ostream & ostr);
586
587 protected:
588 unsigned char Rl;
589 unsigned char Rh;
590 unsigned char Rd;
591 };
592
593 class ELPM : public Instruction {
594 /*
595 * Extended Load Program Memory.
596 *
597 *
598 * Opcode : 1001 0101 1101 1000
599 * Usage : ELPM
600 * Operation : R0 <- (RAMPZ:Z)
601 * Flags : None
602 * Num Clocks : 3
603 */
604
605 public:
606 ELPM(word opcode);
607
608 public:
609 int operator()(Core *core);
610 int trace(Core *core, std::ostream & ostr);
611
612 protected:
613 unsigned char Rl;
614 unsigned char Rh;
615 unsigned char R0;
616 };
617
618 class EOR:public Instruction {
619 /*
620 * Exclusive OR.
621 *
622 * Opcode : 0010 01rd dddd rrrr
623 * Usage : EOR Rd, Rr
624 * Operation : Rd <- Rd ^ Rr
625 * Flags : Z,N,V,S
626 * Num Clocks : 1
627 */
628
629 public:
630 EOR(word opcode);
631
632 public:
633 int operator()(Core *core);
634 int trace(Core *core, std::ostream & ostr);
635
636 protected:
637 unsigned char Rd;
638 unsigned char Rr;
639 unsigned char S;
640 };
641
642 class ESPM : public Instruction {
643 /*
644 * Extended Store Program Memory.
645 *
646 * Opcode : 1001 0101 1111 1000
647 * Usage : ESPM
648 * Operation : Z <- R1:R0
649 * Flags : None
650 * Num Clocks : -
651 */
652
653 public:
654 ESPM(word opcode);
655
656 public:
657 int operator()(Core *core);
658 int trace(Core *core, std::ostream & ostr);
659
660 protected:
661 unsigned char R0;
662 unsigned char R1;
663 };
664
665 class FMUL:public Instruction {
666 /*
667 * Fractional Mult Unsigned.
668 *
669 * Opcode : 0000 0011 0ddd 1rrr
670 * Usage : FMUL Rd, Rr
671 * Operation : R1:R0 <- (Rd * Rr)<<1 (UU)
672 * Flags : Z,C
673 * Num Clocks : 2
674 */
675
676 public:
677 FMUL(word opcode);
678
679 public:
680 int operator()(Core *core);
681 int trace(Core *core, std::ostream & ostr);
682
683 protected:
684 unsigned char R0;
685 unsigned char R1;
686 unsigned char Rd;
687 unsigned char Rr;
688 unsigned char S;
689 };
690
691 class FMULS : public Instruction {
692 /*
693 * Fractional Mult Signed.
694 *
695 * Opcode : 0000 0011 1ddd 0rrr
696 * Usage : FMULS Rd, Rr
697 * Operation : R1:R0 <- (Rd * Rr)<<1 (SS)
698 * Flags : Z,C
699 * Num Clocks : 2
700 */
701
702 public:
703 FMULS(word opcode);
704
705 public:
706 int operator()(Core *core);
707 int trace(Core *core, std::ostream & ostr);
708
709 protected:
710 unsigned char R0;
711 unsigned char R1;
712 unsigned char Rd;
713 unsigned char Rr;
714 unsigned char S;
715 };
716
717 class FMULSU : public Instruction {
718 /*
719 * Fract Mult Signed w/ Unsigned.
720 *
721 * Opcode : 0000 0011 1ddd 1rrr
722 * Usage : FMULSU Rd, Rr
723 * Operation : R1:R0 <- (Rd * Rr)<<1 (SU)
724 * Flags : Z,C
725 * Num Clocks : 2
726 */
727
728 public:
729 FMULSU (word opcode);
730
731 public:
732 int operator()(Core *core);
733 int trace(Core *core, std::ostream & ostr);
734
735 protected:
736 unsigned char R0;
737 unsigned char R1;
738 unsigned char Rd;
739 unsigned char Rr;
740 unsigned char S;
741 };
742
743 class ICALL : public Instruction {
744 /*
745 * Indirect Call to (Z).
746 *
747 * Opcode : 1001 0101 0000 1001
748 * Usage : ICALL
749 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
750 * Flags : None
751 * Num Clocks : 3 / 4
752 */
753
754 public:
755 ICALL(word opcode);
756
757 public:
758 int operator()(Core *core);
759 int trace(Core *core, std::ostream & ostr);
760
761 protected:
762 unsigned char Rl;
763 unsigned char Rh;
764 };
765
766 class IJMP : public Instruction {
767 /*
768 * Indirect Jump to (Z).
769 *
770 * Opcode : 1001 0100 0000 1001
771 * Usage : IJMP
772 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
773 * Flags : None
774 * Num Clocks : 2
775 */
776
777 public:
778 IJMP(word opcode);
779
780 public:
781 int operator()(Core *core);
782 int trace(Core *core, std::ostream & ostr);
783
784 protected:
785 unsigned char Rl;
786 unsigned char Rh;
787 };
788
789 class IN : public Instruction {
790 /*
791 * In From I/O Location.
792 *
793 * Opcode : 1011 0AAd dddd AAAA
794 * Usage : IN Rd, A
795 * Operation : Rd <- I/O(A)
796 * Flags : None
797 * Num Clocks : 1
798 */
799
800 public:
801 IN (word opcode);
802
803 public:
804 int operator()(Core *core);
805 int trace(Core *core, std::ostream & ostr);
806
807 protected:
808 unsigned char Rd;
809 unsigned char ioreg;
810 };
811
812 class INC : public Instruction {
813 /*
814 * Increment.
815 *
816 * Opcode : 1001 010d dddd 0011
817 * Usage : INC Rd
818 * Operation : Rd <- Rd + 1
819 * Flags : Z,N,V,S
820 * Num Clocks : 1
821 */
822
823 public:
824 INC (word opcode);
825
826 public:
827 int operator()(Core *core);
828 int trace(Core *core, std::ostream & ostr);
829
830 protected:
831 unsigned char Rd;
832 unsigned char S;
833 };
834
835 class JMP : public Instruction {
836 /*
837 * Jump.
838 *
839 * Opcode : 1001 010k kkkk 110k kkkk kkkk kkkk kkkk
840 * Usage : JMP k
841 * Operation : PC <- k
842 * Flags : None
843 * Num Clocks : 3
844 */
845
846 public:
847 JMP(word opcode);
848
849 public:
850 int operator()(Core *core);
851 int trace(Core *core, std::ostream & ostr);
852 bool is2Word() const { return true; }
853
854 protected:
855 unsigned int K;
856 };
857
858 class LDD_Y : public Instruction {
859 /*
860 * Load Indirect with Displacement using index Y.
861 *
862 * Opcode : 10q0 qq0d dddd 1qqq
863 * Usage : LDD Rd, Y+q
864 * Operation : Rd <- (Y + q)
865 * Flags : None
866 * Num Clocks : 2
867 */
868
869 public:
870 LDD_Y(word opcode);
871
872 public:
873 int operator()(Core *core);
874 int trace(Core *core, std::ostream & ostr);
875
876 protected:
877 unsigned char Rl;
878 unsigned char Rh;
879 unsigned char Rd;
880 unsigned char K;
881 };
882
883 class LDD_Z : public Instruction {
884 /*
885 * Load Indirect with Displacement using index Z.
886 *
887 * Opcode : 10q0 qq0d dddd 0qqq
888 * Usage : LDD Rd, Z+q
889 * Operation : Rd <- (Z + q)
890 * Flags : None
891 * Num Clocks : 2
892 */
893
894 public:
895 LDD_Z(word opcode);
896
897 public:
898 int operator()(Core *core);
899 int trace(Core *core, std::ostream & ostr);
900
901 protected:
902 unsigned char Rl;
903 unsigned char Rh;
904 unsigned char Rd;
905 unsigned char K;
906 };
907
908 class LDI : public Instruction {
909 /*
910 * Load Immediate.
911 *
912 * Opcode : 1110 KKKK dddd KKKK
913 * Usage : LDI Rd, K
914 * Operation : Rd <- K
915 * Flags : None
916 * Num Clocks : 1
917 */
918
919 public:
920 LDI(word opcode);
921
922 public:
923 int operator()(Core *core);
924 int trace(Core *core, std::ostream & ostr);
925
926 protected:
927 unsigned char Rd;
928 unsigned char K;
929 };
930
931 class LDS : public Instruction {
932 /*
933 * Load Direct from data space.
934 *
935 * Opcode : 1001 000d dddd 0000 kkkk kkkk kkkk kkkk
936 * Usage : LDS Rd, k
937 * Operation : Rd <- (k)
938 * Flags : None
939 * Num Clocks : 2
940 */
941
942 public:
943 LDS(word opcode);
944
945 public:
946 int operator()(Core *core);
947 int trace(Core *core, std::ostream & ostr);
948 bool is2Word() const { return true; }
949
950 protected:
951 unsigned char Rd;
952 };
953
954 class LD_X : public Instruction {
955 /*
956 * Load Indirect using index X.
957 *
958 * Opcode : 1001 000d dddd 1100
959 * Usage : LD Rd, X
960 * Operation : Rd <- (X)
961 * Flags : None
962 * Num Clocks : 2
963 */
964
965 public:
966 LD_X(word opcode);
967
968 public:
969 int operator()(Core *core);
970 int trace(Core *core, std::ostream & ostr);
971
972 protected:
973 unsigned char Rl;
974 unsigned char Rh;
975 unsigned char Rd;
976 };
977
978 class LD_X_decr : public LD_X {
979 /*
980 * Load Indirect and Pre-Decrement using index X.
981 *
982 * Opcode : 1001 000d dddd 1110
983 * Usage : LD Rd, -X
984 * Operation : X <- X - 1, Rd <- (X)
985 * Flags : None
986 * Num Clocks : 2
987 */
988
989 public:
990 LD_X_decr(word opcode);
991
992 public:
993 int operator()(Core *core);
994 int trace(Core *core, std::ostream & ostr);
995 };
996
997 class LD_X_incr : public LD_X {
998 /*
999 * Load Indirect and Post-Increment using index X.
1000 *
1001 * Opcode : 1001 000d dddd 1101
1002 * Usage : LD Rd, X+
1003 * Operation : Rd <- (X), X <- X + 1
1004 * Flags : None
1005 * Num Clocks : 2
1006 */
1007
1008 public:
1009 LD_X_incr(word opcode);
1010
1011 public:
1012 int operator()(Core *core);
1013 int trace(Core *core, std::ostream & ostr);
1014 };
1015
1016 class LD_Y_decr : public Instruction {
1017 /*
1018 * Load Indirect and PreDecrement using index Y.
1019 *
1020 * Opcode : 1001 000d dddd 1010
1021 * Usage : LD Rd, -Y
1022 * Operation : Y <- Y - 1, Rd <- (Y)
1023 * Flags : None
1024 * Num Clocks : 2
1025 */
1026
1027 public:
1028 LD_Y_decr(word opcode);
1029
1030 public:
1031 int operator()(Core *core);
1032 int trace(Core *core, std::ostream & ostr);
1033
1034 protected:
1035 unsigned char Rl;
1036 unsigned char Rh;
1037 unsigned char Rd;
1038 };
1039
1040 class LD_Y_incr : public Instruction {
1041 /*
1042 * Load Indirect and Post-Increment using index Y.
1043 *
1044 * Opcode : 1001 000d dddd 1001
1045 * Usage : LD Rd, Y+
1046 * Operation : Rd <- (Y), Y <- Y + 1
1047 * Flags : None
1048 * Num Clocks : 2
1049 */
1050
1051 public:
1052 LD_Y_incr(word opcode);
1053
1054 public:
1055 int operator()(Core *core);
1056 int trace(Core *core, std::ostream & ostr);
1057
1058 protected:
1059 unsigned char Rl;
1060 unsigned char Rh;
1061 unsigned char Rd;
1062 };
1063
1064 class LD_Z_incr : public Instruction {
1065 /*
1066 * Load Indirect and Post-Increment using index Z.
1067 *
1068 * Opcode : 1001 000d dddd 0001
1069 * Usage : LD Rd, Z+
1070 * Operation : Rd <- (Z), Z <- Z+1
1071 * Flags : None
1072 * Num Clocks : 2
1073 */
1074
1075 public:
1076 LD_Z_incr(word opcode);
1077
1078 public:
1079 int operator()(Core *core);
1080 int trace(Core *core, std::ostream & ostr);
1081
1082 protected:
1083 unsigned char Rl;
1084 unsigned char Rh;
1085 unsigned char Rd;
1086 };
1087
1088 class LD_Z_decr : public Instruction {
1089 /*
1090 * Load Indirect and Pre-Decrement using index Z.
1091 *
1092 * Opcode : 1001 000d dddd 0010
1093 * Usage : LD Rd, -Z
1094 * Operation : Z <- Z - 1, Rd <- (Z)
1095 * Flags : None
1096 * Num Clocks : 2
1097 */
1098
1099 public:
1100 LD_Z_decr(word opcode);
1101
1102 public:
1103 int operator()(Core *core);
1104 int trace(Core *core, std::ostream & ostr);
1105
1106 protected:
1107 unsigned char Rl;
1108 unsigned char Rh;
1109 unsigned char Rd;
1110 };
1111
1112 class LPM_Z : public Instruction {
1113 /*
1114 * Load Program Memory.
1115 *
1116 * Opcode : 1001 000d dddd 0100
1117 * Usage : LPM Rd, Z
1118 * Operation : Rd <- (Z)
1119 * Flags : None
1120 * Num Clocks : 3
1121 */
1122
1123 public:
1124 LPM_Z(word opcode);
1125
1126 public:
1127 int operator()(Core *core);
1128 int trace(Core *core, std::ostream & ostr);
1129
1130 protected:
1131 unsigned char Rl;
1132 unsigned char Rh;
1133 unsigned char Rd;
1134 };
1135
1136 class LPM : public Instruction {
1137 /* Load Program Memory.
1138 *
1139 * This the same as LPM_Z:public Instruction
1140 *
1141 * Opcode : 1001 0101 1100 1000
1142 * Usage : LPM
1143 * Operation : R0 <- (Z)
1144 * Flags : None
1145 * Num Clocks : 3
1146 */
1147
1148 public:
1149 LPM(word opcode);
1150
1151 public:
1152 int operator()(Core *core);
1153 int trace(Core *core, std::ostream & ostr);
1154
1155 protected:
1156 unsigned char Rl;
1157 unsigned char Rh;
1158 unsigned char Rd;
1159 };
1160
1161 class LPM_Z_incr : public Instruction {
1162 /*
1163 * Load Program Memory and Post-Incr.
1164 *
1165 * Opcode : 1001 000d dddd 0101
1166 * Usage : LPM Rd, Z+
1167 * Operation : Rd <- (Z), Z <- Z + 1
1168 * Flags : None
1169 * Num Clocks : 3
1170 */
1171
1172 public:
1173 LPM_Z_incr(word opcode);
1174
1175 public:
1176 int operator()(Core *core);
1177 int trace(Core *core, std::ostream & ostr);
1178
1179 protected:
1180 unsigned char Rl;
1181 unsigned char Rh;
1182 unsigned char Rd;
1183 };
1184
1185 class LSR : public Instruction {
1186 /*
1187 * Logical Shift Right.
1188 *
1189 * Opcode : 1001 010d dddd 0110
1190 * Usage : LSR Rd
1191 * Operation : Rd(n) <- Rd(n+1), Rd(7) <- 0, C <- Rd(0)
1192 * Flags : Z,C,N,V,S
1193 * Num Clocks : 1
1194 */
1195
1196 public:
1197 LSR(word opcode);
1198
1199 public:
1200 int operator()(Core *core);
1201 int trace(Core *core, std::ostream & ostr);
1202
1203 protected:
1204 unsigned char Rd;
1205 unsigned char S;
1206 };
1207
1208 class MOV:public Instruction {
1209 /* Copy Register.
1210 *
1211 * Opcode : 0010 11rd dddd rrrr
1212 * Usage : MOV Rd, Rr
1213 * Operation : Rd <- Rr
1214 * Flags : None
1215 * Num Clocks : 1
1216 */
1217
1218 public:
1219 MOV(word opcode);
1220
1221 public:
1222 int operator()(Core *core);
1223 int trace(Core *core, std::ostream & ostr);
1224
1225 protected:
1226 unsigned char Rd;
1227 unsigned char Rr;
1228 };
1229
1230 class MOVW:public Instruction {
1231 /*
1232 *Copy Register Pair.
1233 *
1234 * Opcode : 0000 0001 dddd rrrr
1235 * Usage : MOVW Rd, Rr
1236 * Operation : Rd+1:Rd <- Rr+1:Rr
1237 * Flags : None
1238 * Num Clocks : 1
1239 */
1240
1241 public:
1242 MOVW(word opcode);
1243
1244 public:
1245 int operator()(Core *core);
1246 int trace(Core *core, std::ostream & ostr);
1247
1248 protected:
1249 unsigned char Rdl;
1250 unsigned char Rdh;
1251 unsigned char Rrl;
1252 unsigned char Rrh;
1253 };
1254
1255 class MUL : public Instruction {
1256 /*
1257 * Mult Unsigned.
1258 *
1259 * Opcode : 1001 11rd dddd rrrr
1260 * Usage : MUL Rd, Rr
1261 * Operation : R1:R0 <- Rd * Rr (UU)
1262 * Flags : Z,C
1263 * Num Clocks : 2
1264 */
1265
1266 public:
1267 MUL(word opcode);
1268
1269 public:
1270 int operator()(Core *core);
1271 int trace(Core *core, std::ostream & ostr);
1272
1273 protected:
1274 unsigned char R0;
1275 unsigned char R1;
1276 unsigned char Rd;
1277 unsigned char Rr;
1278 unsigned char S;
1279 };
1280
1281 class MULS : public Instruction {
1282 /*
1283 * Mult Signed.
1284 *
1285 * Opcode : 0000 0010 dddd rrrr
1286 * Usage : MULS Rd, Rr
1287 * Operation : R1:R0 <- Rd * Rr (SS)
1288 * Flags : Z,C
1289 * Num Clocks : 2
1290 */
1291
1292 public:
1293 MULS(word opcode);
1294
1295 public:
1296 int operator()(Core *core);
1297 int trace(Core *core, std::ostream & ostr);
1298
1299 protected:
1300 unsigned char R0;
1301 unsigned char R1;
1302 unsigned char Rd;
1303 unsigned char Rr;
1304 unsigned char S;
1305 };
1306
1307 class MULSU:public Instruction {
1308 /*
1309 * Mult Signed with Unsigned.
1310 *
1311 * Rd(unsigned),Rr(signed), result (signed)
1312 *
1313 * Opcode : 0000 0011 0ddd 0rrr
1314 * Usage : MULSU Rd, Rr
1315 * Operation : R1:R0 <- Rd * Rr (SU)
1316 * Flags : Z,C
1317 * Num Clocks : 2
1318 */
1319
1320 public:
1321 MULSU(word opcode);
1322
1323 public:
1324 int operator()(Core *core);
1325 int trace(Core *core, std::ostream & ostr);
1326
1327 protected:
1328 unsigned char R0;
1329 unsigned char R1;
1330 unsigned char Rd;
1331 unsigned char Rr;
1332 unsigned char S;
1333 };
1334
1335 class NEG : public Instruction {
1336 /*
1337 * Two's Complement.
1338 *
1339 * Opcode : 1001 010d dddd 0001
1340 * Usage : NEG Rd
1341 * Operation : Rd <- $00 - Rd
1342 * Flags : Z,C,N,V,S,H
1343 * Num Clocks : 1
1344 */
1345
1346 public:
1347 NEG (word opcode);
1348
1349 public:
1350 int operator()(Core *core);
1351 int trace(Core *core, std::ostream & ostr);
1352
1353 protected:
1354 unsigned char Rd;
1355 unsigned char S;
1356 };
1357
1358 class NOP : public Instruction {
1359 /*
1360 * No Operation.
1361 *
1362 * Opcode : 0000 0000 0000 0000
1363 * Usage : NOP
1364 * Operation : None
1365 * Flags : None
1366 * Num Clocks : 1
1367 */
1368
1369 public:
1370 NOP(word opcode);
1371
1372 public:
1373 int operator()(Core *core);
1374 int trace(Core *core, std::ostream & ostr);
1375 };
1376
1377 class OR:public Instruction {
1378 /*
1379 * Logical OR.
1380 *
1381 * Opcode : 0010 10rd dddd rrrr
1382 * Usage : OR Rd, Rr
1383 * Operation : Rd <- Rd or Rr
1384 * Flags : Z,N,V,S
1385 * Num Clocks : 1
1386 */
1387
1388 public:
1389 OR(word opcode);
1390
1391 public:
1392 int operator()(Core *core);
1393 int trace(Core *core, std::ostream & ostr);
1394
1395 protected:
1396 unsigned char Rd;
1397 unsigned char Rr;
1398 unsigned char S;
1399 };
1400
1401 class ORI : public Instruction {
1402 /*
1403 * Logical OR with Immed.
1404 *
1405 * Opcode : 0110 KKKK dddd KKKK
1406 * Usage : ORI Rd, K
1407 * Operation : Rd <- Rd or K
1408 * Flags : Z,N,V,S
1409 * Num Clocks : 1
1410 */
1411
1412 public:
1413 ORI (word opcode);
1414
1415 public:
1416 int operator()(Core *core);
1417 int trace(Core *core, std::ostream & ostr);
1418
1419 protected:
1420 unsigned char Rd;
1421 unsigned char K;
1422 unsigned char S;
1423 };
1424
1425 class OUT : public Instruction {
1426 /*
1427 * Out To I/O Location.
1428 *
1429 * Opcode : 1011 1AAd dddd AAAA
1430 * Usage : OUT A Rd
1431 * Operation : I/O(A) <- Rd
1432 * Flags : None
1433 * Num Clocks : 1
1434 */
1435
1436 public:
1437 OUT(word opcode);
1438
1439 public:
1440 int operator()(Core *core);
1441 int trace(Core *core, std::ostream & ostr);
1442
1443 protected:
1444 unsigned char Rd;
1445 unsigned char ioreg;
1446 };
1447
1448 class POP : public Instruction {
1449 /*
1450 * Pop Register from Stack.
1451 *
1452 * Opcode : 1001 000d dddd 1111
1453 * Usage : POP Rd
1454 * Operation : Rd <- STACK
1455 * Flags : None
1456 * Num Clocks : 2
1457 */
1458
1459 public:
1460 POP(word opcode);
1461
1462 public:
1463 int operator()(Core *core);
1464 int trace(Core *core, std::ostream & ostr);
1465
1466 protected:
1467 unsigned char Rd;
1468 };
1469
1470 class PUSH : public Instruction {
1471 /*
1472 * Push Register on Stack.
1473 *
1474 * Opcode : 1001 001d dddd 1111
1475 * Usage : PUSH Rd
1476 * Operation : STACK <- Rd
1477 * Flags : None
1478 * Num Clocks : 2
1479 */
1480
1481 public:
1482 PUSH(word opcode);
1483
1484 public:
1485 int operator()(Core *core);
1486 int trace(Core *core, std::ostream & ostr);
1487
1488 protected:
1489 unsigned char Rd;
1490 };
1491
1492 class RCALL : public Instruction {
1493 /*
1494 * Relative Call Subroutine.
1495 *
1496 * Opcode : 1101 kkkk kkkk kkkk
1497 * Usage : RCALL k
1498 * Operation : PC <- PC + k + 1
1499 * Flags : None
1500 * Num Clocks : 3 / 4
1501 */
1502
1503 public:
1504 RCALL(word opcode);
1505
1506 public:
1507 int operator()(Core *core);
1508 int trace(Core *core, std::ostream & ostr);
1509
1510 protected:
1511 signed int K;
1512 };
1513
1514 class RET : public Instruction {
1515 /*
1516 * Subroutine Return.
1517 *
1518 * Opcode : 1001 0101 0000 1000
1519 * Usage : RET
1520 * Operation : PC <- STACK
1521 * Flags : None
1522 * Num Clocks : 4 / 5
1523 */
1524
1525 public:
1526 RET(word opcode);
1527
1528 public:
1529 int operator()(Core *core);
1530 int trace(Core *core, std::ostream & ostr);
1531 };
1532
1533 class RETI : public Instruction {
1534 /*
1535 * Interrupt Return.
1536 *
1537 * Opcode : 1001 0101 0001 1000
1538 * Usage : RETI
1539 * Operation : PC <- STACK
1540 * Flags : I
1541 * Num Clocks : 4 / 5
1542 */
1543
1544 public:
1545 RETI(word opcode);
1546
1547 public:
1548 int operator()(Core *core);
1549 int trace(Core *core, std::ostream & ostr);
1550
1551 protected:
1552 unsigned char S;
1553 };
1554
1555 class RJMP : public Instruction {
1556 /*
1557 * Relative Jump.
1558 *
1559 * Opcode : 1100 kkkk kkkk kkkk
1560 * Usage : RJMP k
1561 * Operation : PC <- PC + k + 1
1562 * Flags : None
1563 * Num Clocks : 2
1564 */
1565
1566 public:
1567 RJMP(word opcode);
1568
1569 public:
1570 int operator()(Core *core);
1571 int trace(Core *core, std::ostream & ostr);
1572
1573 protected:
1574 signed int K;
1575 };
1576
1577 class ROR : public Instruction {
1578 /*
1579 * Rotate Right Though Carry.
1580 *
1581 * Opcode : 1001 010d dddd 0111
1582 * Usage : ROR Rd
1583 * Operation : Rd(7) <- C, Rd(n) <- Rd(n+1), C <- Rd(0)
1584 * Flags : Z,C,N,V,S
1585 * Num Clocks : 1
1586 */
1587
1588 public:
1589 ROR(word opcode);
1590
1591 public:
1592 int operator()(Core *core);
1593 int trace(Core *core, std::ostream & ostr);
1594
1595 protected:
1596 unsigned char Rd;
1597 unsigned char S;
1598 };
1599
1600 class SBC : public Instruction {
1601 /*
1602 * Subtract with Carry.
1603 *
1604 * Opcode : 0000 10rd dddd rrrr
1605 * Usage : SBC Rd, Rr
1606 * Operation : Rd <- Rd - Rr - C
1607 * Flags : Z,C,N,V,S,H
1608 * Num Clocks : 1
1609 */
1610
1611 public:
1612 SBC(word opcode);
1613
1614 public:
1615 int operator()(Core *core);
1616 int trace(Core *core, std::ostream & ostr);
1617
1618 protected:
1619 unsigned char Rd;
1620 unsigned char Rr;
1621 unsigned char S;
1622 };
1623
1624 class SBCI : public Instruction {
1625 /*
1626 * Subtract Immediate with Carry.
1627 *
1628 * Opcode : 0100 KKKK dddd KKKK
1629 * Usage : SBCI Rd, K
1630 * Operation : Rd <- Rd - K - C
1631 * Flags : Z,C,N,V,S,H
1632 * Num Clocks : 1
1633 */
1634
1635 public:
1636 SBCI(word opcode);
1637
1638 public:
1639 int operator()(Core *core);
1640 int trace(Core *core, std::ostream & ostr);
1641
1642 protected:
1643 unsigned char Rd;
1644 unsigned char K;
1645 unsigned char S;
1646 };
1647
1648 class SBI : public Instruction {
1649 /*
1650 * Set Bit in I/O Register.
1651 *
1652 * Opcode : 1001 1010 AAAA Abbb
1653 * Usage : SBI A, b
1654 * Operation : I/O(A, b) <- 1
1655 * Flags : None
1656 * Num Clocks : 2
1657 */
1658
1659 public:
1660 SBI(word opcode);
1661
1662 public:
1663 int operator()(Core *core);
1664 int trace(Core *core, std::ostream & ostr);
1665
1666 protected:
1667 unsigned char ioreg;
1668 unsigned char K;
1669 };
1670
1671 class SBIC : public Instruction {
1672 /*
1673 * Skip if Bit in I/O Reg Cleared.
1674 *
1675 * Opcode : 1001 1001 AAAA Abbb
1676 * Usage : SBIC A, b
1677 * Operation : if (I/O(A,b) = 0) PC <- PC + 2 or 3
1678 * Flags : None
1679 * Num Clocks : 1 / 2 / 3
1680 */
1681
1682 public:
1683 SBIC(word opcode);
1684
1685 public:
1686 int operator()(Core *core);
1687 int trace(Core *core, std::ostream & ostr);
1688
1689 protected:
1690 unsigned char ioreg;
1691 unsigned char K;
1692 };
1693
1694 class SBIS : public Instruction {
1695 /*
1696 * Skip if Bit in I/O Reg Set.
1697 *
1698 * Opcode : 1001 1011 AAAA Abbb
1699 * Usage : SBIS A, b
1700 * Operation : if (I/O(A,b) = 1) PC <- PC + 2 or 3
1701 * Flags : None
1702 * Num Clocks : 1 / 2 / 3
1703 */
1704
1705 public:
1706 SBIS(word opcode);
1707
1708 public:
1709 int operator()(Core *core);
1710 int trace(Core *core, std::ostream & ostr);
1711
1712 protected:
1713 unsigned char ioreg;
1714 unsigned char K;
1715 };
1716
1717 class SBIW : public Instruction {
1718 /*
1719 * Subtract Immed from Word.
1720 *
1721 * Opcode : 1001 0111 KKdd KKKK
1722 * Usage : SBIW Rd, K
1723 * Operation : Rd+1:Rd <- Rd+1:Rd - K
1724 * Flags : Z,C,N,V,S
1725 * Num Clocks : 2
1726 */
1727
1728 public:
1729 SBIW (word opcode);
1730
1731 public:
1732 int operator()(Core *core);
1733 int trace(Core *core, std::ostream & ostr);
1734
1735 protected:
1736 unsigned char Rl;
1737 unsigned char Rh;
1738 unsigned char K;
1739 unsigned char S;
1740 };
1741
1742 class SBRC : public Instruction {
1743 /*
1744 * Skip if Bit in Reg Cleared.
1745 *
1746 * Opcode : 1111 110d dddd 0bbb
1747 * Usage : SBRC Rd, b
1748 * Operation : if (Rd(b) = 0) PC <- PC + 2 or 3
1749 * Flags : None
1750 * Num Clocks : 1 / 2 / 3
1751 */
1752
1753 public:
1754 SBRC (word opcode);
1755
1756 public:
1757 int operator()(Core *core);
1758 int trace(Core *core, std::ostream & ostr);
1759
1760 protected:
1761 unsigned char Rd;
1762 unsigned char K;
1763 };
1764
1765 class SBRS : public Instruction {
1766 /*
1767 * Skip if Bit in Reg Set.
1768 *
1769 * Opcode : 1111 111d dddd 0bbb
1770 * Usage : SBRS Rd, b
1771 * Operation : if (Rd(b) = 1) PC <- PC + 2 or 3
1772 * Flags : None
1773 * Num Clocks : 1 / 2 / 3
1774 */
1775
1776 public:
1777 SBRS (word opcode);
1778
1779 public:
1780 int operator()(Core *core);
1781 int trace(Core *core, std::ostream & ostr);
1782
1783 protected:
1784 unsigned char Rd;
1785 unsigned char K;
1786 };
1787
1788 class SLEEP : public Instruction {
1789 /*
1790 * Sleep.
1791 *
1792 * This is device specific and should be overridden by sub-class.
1793 *
1794 * Opcode : 1001 0101 1000 1000
1795 * Usage : SLEEP
1796 * Operation : (see specific hardware specification for Sleep)
1797 * Flags : None
1798 * Num Clocks : 1
1799 */
1800
1801
1802 public:
1803 SLEEP(word opcode);
1804
1805 public:
1806 int operator()(Core *core);
1807 int trace(Core *core, std::ostream & ostr);
1808 };
1809
1810 class SPM : public Instruction {
1811 /*
1812 * Store Program Memory.
1813 *
1814 * Opcode : 1001 0101 1110 1000
1815 * Usage : SPM
1816 * Operation : (Z) <- R1:R0
1817 * Flags : None
1818 * Num Clocks : -
1819 */
1820
1821 public:
1822 SPM(word opcode);
1823
1824 public:
1825 int operator()(Core *core);
1826 int trace(Core *core, std::ostream & ostr);
1827
1828 protected:
1829 unsigned char R0;
1830 unsigned char R1;
1831 unsigned char Rl;
1832 unsigned char Rh;
1833 };
1834
1835 class STD_Y : public Instruction {
1836 /*
1837 * Store Indirect with Displacement.
1838 *
1839 * Opcode : 10q0 qq1d dddd 1qqq
1840 * Usage : STD Y+q, Rd
1841 * Operation : (Y + q) <- Rd
1842 * Flags : None
1843 * Num Clocks : 2
1844 */
1845
1846 public:
1847 STD_Y(word opcode);
1848
1849 public:
1850 int operator()(Core *core);
1851 int trace(Core *core, std::ostream & ostr);
1852
1853 protected:
1854 unsigned char Rl;
1855 unsigned char Rh;
1856 unsigned char Rd;
1857 unsigned char K;
1858 };
1859
1860 class STD_Z : public Instruction {
1861 /*
1862 * Store Indirect with Displacement.
1863 *
1864 * Opcode : 10q0 qq1d dddd 0qqq
1865 * Usage : STD Z+q, Rd
1866 * Operation : (Z + q) <- Rd
1867 * Flags : None
1868 * Num Clocks : 2
1869 */
1870
1871 public:
1872 STD_Z(word opcode);
1873
1874 public:
1875 int operator()(Core *core);
1876 int trace(Core *core, std::ostream & ostr);
1877
1878 protected:
1879 unsigned char Rl;
1880 unsigned char Rh;
1881 unsigned char Rd;
1882 unsigned char K;
1883 };
1884
1885 class STS : public Instruction {
1886 /*
1887 * Store Direct to data space.
1888 *
1889 * Opcode : 1001 001d dddd 0000 kkkk kkkk kkkk kkkk
1890 * Usage : STS k, Rd
1891 * Operation : (k) <- Rd
1892 * Flags : None
1893 * Num Clocks : 2
1894 */
1895
1896 public:
1897 STS(word opcode);
1898
1899 public:
1900 int operator()(Core *core);
1901 int trace(Core *core, std::ostream & ostr);
1902 bool is2Word() const { return true; }
1903
1904 protected:
1905 unsigned char Rd;
1906 };
1907
1908 class ST_X : public Instruction {
1909 /*
1910 * Store Indirect using index X.
1911 *
1912 * Opcode : 1001 001d dddd 1100
1913 * Usage : ST X, Rd
1914 * Operation : (X) <- Rd
1915 * Flags : None
1916 * Num Clocks : 2
1917 */
1918
1919 public:
1920 ST_X(word opcode);
1921
1922 public:
1923 int operator()(Core *core);
1924 int trace(Core *core, std::ostream & ostr);
1925
1926 protected:
1927 unsigned char Rl;
1928 unsigned char Rh;
1929 unsigned char Rd;
1930 };
1931
1932 class ST_X_decr : public ST_X {
1933 /*
1934 * Store Indirect and Pre-Decrement using index X.
1935 *
1936 * Opcode : 1001 001d dddd 1110
1937 * Usage : ST -X, Rd
1938 * Operation : X <- X - 1, (X) <- Rd
1939 * Flags : None
1940 * Num Clocks : 2
1941 */
1942
1943 public:
1944 ST_X_decr(word opcode);
1945
1946 public:
1947 int operator()(Core *core);
1948 int trace(Core *core, std::ostream & ostr);
1949 };
1950
1951 class ST_X_incr : public ST_X {
1952 /*
1953 * Store Indirect and Post-Increment using index X.
1954 *
1955 * Opcode : 1001 001d dddd 1101
1956 * Usage : ST X+, Rd
1957 * Operation : (X) <- Rd, X <- X + 1
1958 * Flags : None
1959 * Num Clocks : 2
1960 */
1961
1962 public:
1963 ST_X_incr(word opcode);
1964
1965 public:
1966 int operator()(Core *core);
1967 int trace(Core *core, std::ostream & ostr);
1968 };
1969
1970 class ST_Y_decr : public Instruction {
1971 /*
1972 * Store Indirect and Pre-Decrement using index Y.
1973 *
1974 * Opcode : 1001 001d dddd 1010
1975 * Usage : ST -Y, Rd
1976 * Operation : Y <- Y - 1, (Y) <- Rd
1977 * Flags : None
1978 * Num Clocks : 2
1979 */
1980
1981 public:
1982 ST_Y_decr (word opcode);
1983
1984 public:
1985 int operator()(Core *core);
1986 int trace(Core *core, std::ostream & ostr);
1987
1988 protected:
1989 unsigned char Rl;
1990 unsigned char Rh;
1991 unsigned char Rd;
1992 };
1993
1994 class ST_Y_incr : public Instruction {
1995 /*
1996 * Store Indirect and Post-Increment using index Y.
1997 *
1998 * Opcode : 1001 001d dddd 1001
1999 * Usage : ST Y+, Rd
2000 * Operation : (Y) <- Rd, Y <- Y + 1
2001 * Flags : None
2002 * Num Clocks : 2
2003 */
2004
2005 public:
2006 ST_Y_incr (word opcode);
2007
2008 public:
2009 int operator()(Core *core);
2010 int trace(Core *core, std::ostream & ostr);
2011
2012 protected:
2013 unsigned char Rl;
2014 unsigned char Rh;
2015 unsigned char Rd;
2016 };
2017
2018 class ST_Z_decr : public Instruction {
2019 /*
2020 * Store Indirect and Pre-Decrement using index Z.
2021 *
2022 * Opcode : 1001 001d dddd 0010
2023 * Usage : ST -Z, Rd
2024 * Operation : Z <- Z - 1, (Z) <- Rd
2025 * Flags : None
2026 * Num Clocks : 2
2027 */
2028
2029 public:
2030 ST_Z_decr (word opcode);
2031
2032 public:
2033 int operator()(Core *core);
2034 int trace(Core *core, std::ostream & ostr);
2035
2036 protected:
2037 unsigned char Rl;
2038 unsigned char Rh;
2039 unsigned char Rd;
2040 };
2041
2042 class ST_Z_incr : public Instruction {
2043 /*
2044 * Store Indirect and Post-Increment using index Z.
2045 *
2046 * Opcode : 1001 001d dddd 0001
2047 * Usage : ST Z+, Rd
2048 * Operation : (Z) <- Rd, Z <- Z + 1
2049 * Flags : None
2050 * Num Clocks : 2
2051 */
2052
2053 public:
2054 ST_Z_incr (word opcode);
2055
2056 public:
2057 int operator()(Core *core);
2058 int trace(Core *core, std::ostream & ostr);
2059
2060 protected:
2061 unsigned char Rl;
2062 unsigned char Rh;
2063 unsigned char Rd;
2064 };
2065
2066 class SUB : public Instruction {
2067 /*
2068 * Subtract without Carry.
2069 *
2070 * Opcode : 0001 10rd dddd rrrr
2071 * Usage : SUB Rd, Rr
2072 * Operation : Rd <- Rd - Rr
2073 * Flags : Z,C,N,V,S,H
2074 * Num Clocks : 1
2075 */
2076
2077 public:
2078 SUB(word opcode);
2079
2080 public:
2081 int operator()(Core *core);
2082 int trace(Core *core, std::ostream & ostr);
2083
2084 protected:
2085 unsigned char Rd;
2086 unsigned char Rr;
2087 };
2088
2089 class SUBI : public Instruction {
2090 /*
2091 * Subtract Immediate.
2092 *
2093 * Opcode : 0101 KKKK dddd KKKK
2094 * Usage : SUBI Rd, K
2095 * Operation : Rd <- Rd - K
2096 * Flags : Z,C,N,V,S,H
2097 * Num Clocks : 1
2098 */
2099
2100 public:
2101 SUBI(word opcode);
2102
2103 public:
2104 int operator()(Core *core);
2105 int trace(Core *core, std::ostream & ostr);
2106
2107 protected:
2108 unsigned char Rd;
2109 unsigned char K;
2110 unsigned char S;
2111 };
2112
2113 class SWAP : public Instruction {
2114 /*
2115 * Swap Nibbles.
2116 *
2117 * Opcode : 1001 010d dddd 0010
2118 * Usage : SWAP Rd
2119 * Operation : Rd(3..0) <--> Rd(7..4)
2120 * Flags : None
2121 * Num Clocks : 1
2122 */
2123
2124 public:
2125 SWAP(word opcode);
2126
2127 public:
2128 int operator()(Core *core);
2129 int trace(Core *core, std::ostream & ostr);
2130
2131 protected:
2132 unsigned char Rd;
2133 };
2134
2135 class WDR : public Instruction {
2136 /*
2137 * Watchdog Reset.
2138 *
2139 * This is device specific and must be overridden by sub-class.
2140 *
2141 * Opcode : 1001 0101 1010 1000
2142 * Usage : WDR
2143 * Operation : (see specific hardware specification for WDR)
2144 * Flags : None
2145 * Num Clocks : 1
2146 */
2147
2148 public:
2149 WDR(word opcode);
2150
2151 public:
2152 int operator()(Core *core);
2153 int trace(Core *core, std::ostream & ostr);
2154 };
2155
2156 class BREAK : public Instruction {
2157 /*
2158 * On-chip Debug system break.
2159 *
2160 * Opcode : 1001 0101 1001 1000
2161 * Usage : BREAK
2162 * Operation : (see specific hardware specification for BREAK)
2163 * Flags : None
2164 * Num Clocks : 1
2165 */
2166
2167 public:
2168 BREAK(word opcode);
2169
2170 public:
2171 int operator()(Core *core);
2172 int trace(Core *core, std::ostream & ostr);
2173 };
2174
2175 class ILLEGAL : public Instruction {
2176 //illegal instruction
2177
2178 public:
2179 ILLEGAL(word opcode);
2180
2181 public:
2182 int operator()(Core *core);
2183 int trace(Core *core, std::ostream & ostr);
2184
2185 private:
2186 word opcode;
2187 };
2188
2189 }
2190
2191 }
2192
2193 #endif /*AVR_INSTRUCTIONS_H*/
Atmel AVR simulator