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Devices are printed in a pretty way.
[avr-sim.git] / devices / atxmega128a1
blob3113ce4898bfe8dd11764046110cc94e4ae47a5e
1 <?xml version="1.0"?>
2 <!DOCTYPE device SYSTEM "device.dtd">
3 <device>
4 <memory>
5 <flash size="139264"/>
6 <iospace start="0" stop="4095"/>
7 <sram size="8192"/>
8 <eram size="16760832"/>
9 </memory>
10 <ioregisters>
11 <ioreg name="SPL" address="0x3D"/>
12 <ioreg name="SPH" address="0x3E"/>
13 <ioreg name="SREG" address="0x3F"/>
14 </ioregisters>
15 <interrupts num="0"/>
16 <packages/>
17 <hardware>
18 <!--Everything after this needs editing!!!-->
19 <module class="GPIO">
20 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="GPIO" text="General Purpose IO Registers" globalregs="true">
21 <reg size="1" name="GPIO0" offset="0x00" text="General Purpose IO Register 0"/>
22 <reg size="1" name="GPIO1" offset="0x01" text="General Purpose IO Register 1"/>
23 <reg size="1" name="GPIO2" offset="0x02" text="General Purpose IO Register 2"/>
24 <reg size="1" name="GPIO3" offset="0x03" text="General Purpose IO Register 3"/>
25 <reg size="1" name="GPIO4" offset="0x04" text="General Purpose IO Register 4"/>
26 <reg size="1" name="GPIO5" offset="0x05" text="General Purpose IO Register 5"/>
27 <reg size="1" name="GPIO6" offset="0x06" text="General Purpose IO Register 6"/>
28 <reg size="1" name="GPIO7" offset="0x07" text="General Purpose IO Register 7"/>
29 <reg size="1" name="GPIO8" offset="0x08" text="General Purpose IO Register 8"/>
30 <reg size="1" name="GPIO9" offset="0x09" text="General Purpose IO Register 9"/>
31 <reg size="1" name="GPIOA" offset="0x0A" text="General Purpose IO Register 10"/>
32 <reg size="1" name="GPIOB" offset="0x0B" text="General Purpose IO Register 11"/>
33 <reg size="1" name="GPIOC" offset="0x0C" text="General Purpose IO Register 12"/>
34 <reg size="1" name="GPIOD" offset="0x0D" text="General Purpose IO Register 13"/>
35 <reg size="1" name="GPIOE" offset="0x0E" text="General Purpose IO Register 14"/>
36 <reg size="1" name="GPIOF" offset="0x0F" text="General Purpose IO Register 15"/>
37 </registers>
38 </module>
39 <module class="XOCD">
40 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="OCD" text="On-Chip Debug System">
41 <reg size="1" name="OCDR0" offset="0x00" text="OCD Register 0"/>
42 <reg size="1" name="OCDR1" offset="0x01" text="OCD Register 1">
43 <bitfield name="OCDRD" mask="0x01" text="OCDR Dirty"/>
44 </reg>
45 </registers>
46 </module>
47 <module class="CPU">
48 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="CPU" text="CPU registers" globalregs="true">
49 <reg offset="0x00"/>
50 <reg offset="0x01"/>
51 <reg offset="0x02"/>
52 <reg offset="0x03"/>
53 <reg size="1" name="CCP" offset="0x04" text="Configuration Change Protection">
54 <bitfield name="CCP" mask="0xFF" text="CCP signature" enum="CCP"/>
55 </reg>
56 <reg offset="0x05"/>
57 <reg offset="0x06"/>
58 <reg offset="0x07"/>
59 <reg size="1" name="RAMPD" offset="0x08" text="Ramp D"/>
60 <reg size="1" name="RAMPX" offset="0x09" text="Ramp X"/>
61 <reg size="1" name="RAMPY" offset="0x0A" text="Ramp Y"/>
62 <reg size="1" name="RAMPZ" offset="0x0B" text="Ramp Z"/>
63 <reg size="1" name="EIND" offset="0x0C" text="Extended Indirect Jump"/>
64 <reg size="1" name="SPL" offset="0x0D" text="Stack Pointer Low"/>
65 <reg size="1" name="SPH" offset="0x0E" text="Stack Pointer High"/>
66 <reg size="1" name="SREG" offset="0x0F" text="Status Register">
67 <bitfield name="I" mask="0x80" text="Global Interrupt Enable Flag"/>
68 <bitfield name="T" mask="0x40" text="Transfer Bit"/>
69 <bitfield name="H" mask="0x20" text="Half Carry Flag"/>
70 <bitfield name="S" mask="0x10" text="N Exclusive Or V Flag"/>
71 <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag"/>
72 <bitfield name="N" mask="0x04" text="Negative Flag"/>
73 <bitfield name="Z" mask="0x02" text="Zero Flag"/>
74 <bitfield name="C" mask="0x01" text="Carry Flag"/>
75 </reg>
76 </registers>
77 </module>
78 <module class="CLK">
79 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="CLK" text="Clock System">
80 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
81 <bitfield name="SCLKSEL" mask="0x07" text="System Clock Selection" enum="CLK_SCLKSEL"/>
82 </reg>
83 <reg size="1" name="PSCTRL" offset="0x01" text="Prescaler Control Register"><bitfield name="PSADIV" mask="0x7C" text="Prescaler A Division Factor" enum="CLK_PSADIV"/><bitfield name="PSBCDIV" mask="0x03" text="Prescaler B and D Division factor" enum="CLK_PSBCDIV"/>/&gt;
84 </reg>
85 <reg size="1" name="LOCK" offset="0x02" text="Lock register">
86 <bitfield name="LOCK" mask="0x01" text="Clock System Lock"/>
87 </reg>
88 <reg size="1" name="RTCCTRL" offset="0x03" text="RTC Control Register">
89 <bitfield name="RTCSRC" mask="0x0E" text="Clock Source" enum="CLK_RTCSRC"/>
90 <bitfield name="RTCEN" mask="0x01" text="RTC Clock Source Enable"/>
91 </reg>
92 </registers>
93 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="PR" text="Power Reduction">
94 <reg size="1" name="PR" offset="0x00" text="General Power Reduction">
95 <bitfield name="EBI" mask="0x08" text="External Bus Interface"/>
96 <bitfield name="RTC" mask="0x04" text="Real-time Counter"/>
97 <bitfield name="EVSYS" mask="0x02" text="Event System"/>
98 <bitfield name="DMA" mask="0x01" text="DMA-Controller"/>
99 </reg>
100 <reg size="1" name="PRPA" offset="0x01" text="Power Reduction Port A">
101 <bitfield name="DAC" mask="0x04" text="Port A DAC"/>
102 <bitfield name="ADC" mask="0x02" text="Port A ADC"/>
103 <bitfield name="AC" mask="0x01" text="Port A Analog Comparator"/>
104 </reg>
105 <reg size="1" name="PRPB" offset="0x02" text="Power Reduction Port B">
106 <bitfield name="DAC" mask="0x04" text="Port B DAC"/>
107 <bitfield name="ADC" mask="0x02" text="Port B ADC"/>
108 <bitfield name="AC" mask="0x01" text="Port B Analog Comparator"/>
109 </reg>
110 <reg size="1" name="PRPC" offset="0x03" text="Power Reduction Port C">
111 <bitfield name="TWI" mask="0x40" text="Port C Two-wire Interface"/>
112 <bitfield name="USART1" mask="0x20" text="Port C USART1"/>
113 <bitfield name="USART0" mask="0x10" text="Port C USART0"/>
114 <bitfield name="SPI" mask="0x08" text="Port C SPI"/>
115 <bitfield name="HIRES" mask="0x04" text="Port C AWEX"/>
116 <bitfield name="TC1" mask="0x02" text="Port C Timer/Counter1"/>
117 <bitfield name="TC0" mask="0x01" text="Port C Timer/Counter0"/>
118 </reg>
119 <reg size="1" name="PRPD" offset="0x04" text="Power Reduction Port D">
120 <bitfield name="TWI" mask="0x40" text="Port D Two-wire Interface"/>
121 <bitfield name="USART1" mask="0x20" text="Port D USART1"/>
122 <bitfield name="USART0" mask="0x10" text="Port D USART0"/>
123 <bitfield name="SPI" mask="0x08" text="Port D SPI"/>
124 <bitfield name="HIRES" mask="0x04" text="Port D AWEX"/>
125 <bitfield name="TC1" mask="0x02" text="Port D Timer/Counter1"/>
126 <bitfield name="TC0" mask="0x01" text="Port D Timer/Counter0"/>
127 </reg>
128 <reg size="1" name="PRPE" offset="0x05" text="Power Reduction Port E">
129 <bitfield name="TWI" mask="0x40" text="Port E Two-wire Interface"/>
130 <bitfield name="USART1" mask="0x20" text="Port E USART1"/>
131 <bitfield name="USART0" mask="0x10" text="Port E USART0"/>
132 <bitfield name="SPI" mask="0x08" text="Port E SPI"/>
133 <bitfield name="HIRES" mask="0x04" text="Port E AWEX"/>
134 <bitfield name="TC1" mask="0x02" text="Port E Timer/Counter1"/>
135 <bitfield name="TC0" mask="0x01" text="Port E Timer/Counter0"/>
136 </reg>
137 <reg size="1" name="PRPF" offset="0x06" text="Power Reduction Port F">
138 <bitfield name="TWI" mask="0x40" text="Port F Two-wire Interface"/>
139 <bitfield name="USART1" mask="0x20" text="Port F USART1"/>
140 <bitfield name="USART0" mask="0x10" text="Port F USART0"/>
141 <bitfield name="SPI" mask="0x08" text="Port F SPI"/>
142 <bitfield name="HIRES" mask="0x04" text="Port F AWEX"/>
143 <bitfield name="TC1" mask="0x02" text="Port F Timer/Counter1"/>
144 <bitfield name="TC0" mask="0x01" text="Port F Timer/Counter0"/>
145 </reg>
146 </registers>
147 </module>
148 <module class="SLEEP">
149 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="SLEEP" text="Sleep Controller">
150 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
151 <bitfield name="SMODE" mask="0x0E" text="Sleep Mode" enum="SLEEP_SMODE"/>
152 <bitfield name="SEN" mask="0x01" text="Sleep Enable"/>
153 </reg>
154 </registers>
155 </module>
156 <module class="OSC">
157 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="OSC" text="Oscillator">
158 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
159 <bitfield name="PLLEN" mask="0x10" text="PLL Enable"/>
160 <bitfield name="XOSCEN" mask="0x08" text="External Oscillator Enable"/>
161 <bitfield name="RC32KEN" mask="0x04" text="Internal 32kHz RC Oscillator Enable"/>
162 <bitfield name="RC32MEN" mask="0x02" text="Internal 32MHz RC Oscillator Enable"/>
163 <bitfield name="RC2MEN" mask="0x01" text="Internal 2MHz RC Oscillator Enable"/>
164 </reg>
165 <reg size="1" name="STATUS" offset="0x01" text="Status Register">
166 <bitfield name="PLLRDY" mask="0x10" text="PLL Ready"/>
167 <bitfield name="XOSCRDY" mask="0x08" text="External Oscillator Ready"/>
168 <bitfield name="RC32KRDY" mask="0x04" text="Internal 32kHz RC Oscillator Ready"/>
169 <bitfield name="RC32MRDY" mask="0x02" text="Internal 32MHz RC Oscillator Ready"/>
170 <bitfield name="RC2MRDY" mask="0x01" text="Internal 2MHz RC Oscillator Ready"/>
171 </reg>
172 <reg size="1" name="XOSCCTRL" offset="0x02" text="External Oscillator Control Register">
173 <bitfield name="FRQRANGE" mask="0xC0" text="Frequency Range" enum="OSC_FRQRANGE"/>
174 <bitfield name="X32KLPM" mask="0x20" text="32kHz XTAL OSC Low-power Mode"/>
175 <bitfield name="XOSCSEL" mask="0x0F" text="External Oscillator Selection and Startup Time" enum="OSC_XOSCSEL"/>
176 </reg>
177 <reg size="1" name="XOSCFAIL" offset="0x03" text="External Oscillator Failure Detection Register">
178 <bitfield name="XOSCFDIF" mask="0x02" text="Failure Detection Interrupt Flag"/>
179 <bitfield name="XOSCFDEN" mask="0x01" text="Failure Detection Enable"/>
180 </reg>
181 <reg size="1" name="RC32KCAL" offset="0x04" text="32kHz Internal Oscillator Calibration Register"/>
182 <reg size="1" name="PLLCTRL" offset="0x05" text="PLL Control REgister">
183 <bitfield name="PLLSRC" mask="0xC0" text="Clock Source" enum="OSC_PLLSRC"/>
184 <bitfield name="PLLFAC" mask="0x1F" text="Multiplication Factor"/>
185 </reg>
186 <reg size="1" name="DFLLCTRL" offset="0x06" text="DFLL Control Register">
187 <bitfield name="RC32MCREF" mask="0x02" text="32MHz Calibration Reference"/>
188 <bitfield name="RC2MCREF" mask="0x01" text="2MHz Calibration Reference"/>
189 </reg>
190 </registers>
191 </module>
192 <module class="DFLL">
193 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="DFLL" text="DFLL">
194 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
195 <bitfield name="ENABLE" mask="0x01" text="DFLL Enable"/>
196 </reg>
197 <reg offset="0x01"/>
198 <reg size="1" name="CALA" offset="0x02" text="Calibration Register A">
199 <bitfield name="CALL" mask="0x7F" text="DFLL Calibration bits [6:0]"/>
200 </reg>
201 <reg size="1" name="CALB" offset="0x03" text="Calibration Register B">
202 <bitfield name="CALH" mask="0x3F" text="DFLL Calibration bits [12:7]"/>
203 </reg>
204 <reg size="1" name="OSCCNT0" offset="0x04" text="Oscillator Counter Register 0"/>
205 <reg size="1" name="OSCCNT1" offset="0x05" text="Oscillator Counter Register 1"/>
206 <reg size="1" name="OSCCNT2" mask="0x0F" offset="0x06" text="Oscillator Counter Register 2"/>
207 <reg offset="0x07"/>
208 </registers>
209 </module>
210 <module class="RST">
211 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="RST" text="Reset">
212 <reg size="1" name="STATUS" offset="0x00" text="Status Register">
213 <bitfield name="SDRF" mask="0x40" text="Spike Detection Reset Flag"/>
214 <bitfield name="SRF" mask="0x20" text="Software Reset Flag"/>
215 <bitfield name="PDIRF" mask="0x10" text="Programming and Debug Interface Interface Reset Flag"/>
216 <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag"/>
217 <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag"/>
218 <bitfield name="EXTRF" mask="0x02" text="External Reset Flag"/>
219 <bitfield name="PORF" mask="0x01" text="Power-on Reset Flag"/>
220 </reg>
221 <reg size="1" name="CTRL" offset="0x01" text="Control Register">
222 <bitfield name="SWRST" mask="0x01" text="Software Reset"/>
223 </reg>
224 </registers>
225 </module>
226 <module class="WDT">
227 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="WDT" text="Watch-Dog Timer">
228 <reg size="1" name="CTRL" offset="0x00" text="Control">
229 <bitfield name="PER" mask="0x3C" text="Period" enum="WDT_PER"/>
230 <bitfield name="ENABLE" mask="0x02" text="Enable"/>
231 <bitfield name="CEN" mask="0x01" text="Change Enable"/>
232 </reg>
233 <reg size="1" name="WINCTRL" offset="0x01" text="Windowed Mode Control">
234 <bitfield name="WPER" mask="0x3C" text="Windowed Mode Period" enum="WDT_WPER"/>
235 <bitfield name="WEN" mask="0x02" text="Windowed Mode Enable"/>
236 <bitfield name="WCEN" mask="0x01" text="Windowed Mode Change Enable"/>
237 </reg>
238 <reg size="1" name="STATUS" offset="0x02" text="Status">
239 <bitfield name="SYNCBUSY" mask="0x01" text="Syncronization busy"/>
240 </reg>
241 </registers>
242 </module>
243 <module class="MCU">
244 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="MCU" text="MCU Control">
245 <reg size="1" name="DEVID0" offset="0x00" text="Device ID byte 0"/>
246 <reg size="1" name="DEVID1" offset="0x01" text="Device ID byte 1"/>
247 <reg size="1" name="DEVID2" offset="0x02" text="Device ID byte 2"/>
248 <reg size="1" name="REVID" offset="0x03" text="Revision ID"/>
249 <reg size="1" name="JTAGUID" offset="0x04" text="JTAG User ID"/>
250 <reg offset="0x05"/>
251 <reg size="1" name="MCUCR" offset="0x06" text="MCU Control">
252 <bitfield name="JTAGD" mask="0x01" text="JTAG Disable"/>
253 </reg>
254 <reg offset="0x07"/>
255 <reg size="1" name="EVSYSLOCK" offset="0x08" text="Event System Lock">
256 <bitfield name="EVSYS1LOCK" mask="0x10" text="Event Channel 4-7 Lock"/>
257 <bitfield name="EVSYS0LOCK" mask="0x01" text="Event Channel 0-3 Lock"/>
258 </reg>
259 <reg size="1" name="AWEXLOCK" offset="0x09" text="AWEX Lock">
260 <bitfield name="AWEXELOCK" mask="0x04" text="AWeX on T/C E0 Lock"/>
261 <bitfield name="AWEXCLOCK" mask="0x01" text="AWeX on T/C C0 Lock"/>
262 </reg>
263 <reg offset="0x0A"/>
264 <reg offset="0x0B"/>
265 </registers>
266 </module>
267 <module class="PMIC">
268 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="PMIC" text="Programmable Multi-level Interrupt Controller">
269 <reg size="1" name="STATUS" offset="0x00" text="Status Register">
270 <bitfield name="NMIEX" mask="0x80" text="Non-maskable Interrupt Executing"/>
271 <bitfield name="HILVLEX" mask="0x04" text="High Level Interrupt Executing"/>
272 <bitfield name="MEDLVLEX" mask="0x02" text="Medium Level Interrupt Executing"/>
273 <bitfield name="LOLVLEX" mask="0x01" text="Low Level Interrupt Executing"/>
274 </reg>
275 <reg size="1" name="INTPRI" offset="0x01" text="Interrupt Priority"/>
276 <reg size="1" name="CTRL" offset="0x02" text="Control Register">
277 <bitfield name="RREN" mask="0x80" text="Round-Robin Priority Enable"/>
278 <bitfield name="IVSEL" mask="0x40" text="Interrupt Vector Select"/>
279 <bitfield name="HILVLEN" mask="0x04" text="High Level Enable"/>
280 <bitfield name="MEDLVLEN" mask="0x02" text="Medium Level Enable"/>
281 <bitfield name="LOLVLEN" mask="0x01" text="Low Level Enable"/>
282 </reg>
283 </registers>
284 </module>
285 <module class="DMA">
286 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" name="DMA_CH" text="DMA Channel">
287 <reg size="1" name="CTRLA" offset="0x00" text="Channel Control">
288 <bitfield name="ENABLE" mask="0x80" text="Channel Enable"/>
289 <bitfield name="RESET" mask="0x40" text="Channel Software Reset"/>
290 <bitfield name="REPEAT" mask="0x20" text="Channel Repeat Mode"/>
291 <bitfield name="TRFREQ" mask="0x10" text="Channel Transfer Request"/>
292 <bitfield name="SINGLE" mask="0x04" text="Channel Single Shot Data Transfer"/>
293 <bitfield name="BURSTLEN" mask="0x03" text="Channel Transfer Mode" enum="DMA_CH_BURSTLEN"/>
294 </reg>
295 <reg size="1" name="CTRLB" offset="0x01" text="Channel Control">
296 <bitfield name="CHBUSY" mask="0x80" text="Block Transfer Busy"/>
297 <bitfield name="CHPEND" mask="0x40" text="Block Transfer Pending"/>
298 <bitfield name="ERRIF" mask="0x20" text="Block Transfer Error Interrupt Flag"/>
299 <bitfield name="TRNIF" mask="0x10" text="Transaction Complete Interrup Flag"/>
300 <bitfield name="ERRINTLVL" mask="0x0C" text="Transfer Error Interrupt Level" enum="DMA_CH_ERRINTLVL"/>
301 <bitfield name="TRNINTLVL" mask="0x03" text="Transaction Complete Interrupt Level" enum="DMA_CH_TRNINTLVL"/>
302 </reg>
303 <reg size="1" name="ADDRCTRL" offset="0x02" text="Address Control">
304 <bitfield name="SRCRELOAD" mask="0xC0" text="Channel Source Address Reload" enum="DMA_CH_SRCRELOAD"/>
305 <bitfield name="SRCDIR" mask="0x30" text="Channel Source Address Mode" enum="DMA_CH_SRCDIR"/>
306 <bitfield name="DESTRELOAD" mask="0x0C" text="Channel Destination Address Reload" enum="DMA_CH_DESTRELOAD"/>
307 <bitfield name="DESTDIR" mask="0x03" text="Channel Destination Address Mode" enum="DMA_CH_DESTDIR"/>
308 </reg>
309 <reg size="1" name="TRIGSRC" offset="0x03" text="Channel Trigger Source">
310 <bitfield name="TRIGSRC" mask="0xFF" text="Channel Trigger Source" enum="DMA_CH_TRIGSRC"/>
311 </reg>
312 <reg size="2" name="TRFCNT" offset="0x04" text="Channel Block Transfer Count"/>
313 <reg size="1" name="REPCNT" offset="0x06" text="Channel Repeat Count"/>
314 <reg offset="0x07"/>
315 <reg size="1" name="SRCADDR0" offset="0x08" text="Channel Source Address 0"/>
316 <reg size="1" name="SRCADDR1" offset="0x09" text="Channel Source Address 1"/>
317 <reg size="1" name="SRCADDR2" offset="0x0A" text="Channel Source Address 2"/>
318 <reg offset="0x0B"/>
319 <reg size="1" name="DESTADDR0" offset="0x0C" text="Channel Destination Address 0"/>
320 <reg size="1" name="DESTADDR1" offset="0x0D" text="Channel Destination Address 1"/>
321 <reg size="1" name="DESTADDR2" offset="0x0E" text="Channel Destination Address 2"/>
322 <reg offset="0x0F"/>
323 </registers>
324 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="DMA" text="DMA Controller">
325 <reg size="1" name="CTRL" offset="0x00" text="Control">
326 <bitfield name="ENABLE" mask="0x80" text="Enable"/>
327 <bitfield name="RESET" mask="0x40" text="Software Reset"/>
328 <bitfield name="DBUFMODE" mask="0x0C" text="Double Buffering Mode" enum="DMA_DBUFMODE"/>
329 <bitfield name="PRIMODE" mask="0x03" text="Channel Priority Mode" enum="DMA_PRIMODE"/>
330 </reg>
331 <reg offset="0x01"/>
332 <reg offset="0x02"/>
333 <reg size="1" name="INTFLAGS" offset="0x03" text="Transfer Interrupt Status">
334 <bitfield name="CH3ERRIF" mask="0x80" text="Channel 3 Block Transfer Error Interrupt Flag"/>
335 <bitfield name="CH2ERRIF" mask="0x40" text="Channel 2 Block Transfer Error Interrupt Flag"/>
336 <bitfield name="CH1ERRIF" mask="0x20" text="Channel 1 Block Transfer Error Interrupt Flag"/>
337 <bitfield name="CH0ERRIF" mask="0x10" text="Channel 0 Block Transfer Error Interrupt Flag"/>
338 <bitfield name="CH3TRNIF" mask="0x08" text="Channel 3 Transaction Complete Interrupt Flag"/>
339 <bitfield name="CH2TRNIF" mask="0x04" text="Channel 2 Transaction Complete Interrupt Flag"/>
340 <bitfield name="CH1TRNIF" mask="0x02" text="Channel 1 Transaction Complete Interrupt Flag"/>
341 <bitfield name="CH0TRNIF" mask="0x01" text="Channel 0 Transaction Complete Interrupt Flag"/>
342 </reg>
343 <reg size="1" name="STATUS" offset="0x04" text="Status">
344 <bitfield name="CH3BUSY" mask="0x80" text="Channel 3 Block Transfer Busy"/>
345 <bitfield name="CH2BUSY" mask="0x40" text="Channel 2 Block Transfer Busy"/>
346 <bitfield name="CH1BUSY" mask="0x20" text="Channel 1 Block Transfer Busy"/>
347 <bitfield name="CH0BUSY" mask="0x10" text="Channel 0 Block Transfer Busy"/>
348 <bitfield name="CH3PEND" mask="0x08" text="Channel 3 Block Transfer Pending"/>
349 <bitfield name="CH2PEND" mask="0x04" text="Channel 2 Block Transfer Pending"/>
350 <bitfield name="CH1PEND" mask="0x02" text="Channel 1 Block Transfer Pending"/>
351 <bitfield name="CH0PEND" mask="0x01" text="Channel 0 Block Transfer Pending"/>
352 </reg>
353 <reg offset="0x05"/>
354 <reg size="2" name="TEMP" offset="0x06" text="Temporary Register For 16/24-bit Access"/>
355 <reg offset="0x08"/>
356 <reg offset="0x09"/>
357 <reg offset="0x0A"/>
358 <reg offset="0x0B"/>
359 <reg offset="0x0C"/>
360 <reg offset="0x0D"/>
361 <reg offset="0x0E"/>
362 <reg offset="0x0F"/>
363 <registers implements="DMA_CH" name="CH0" offset="0x10" text="DMA Channel 0"/>
364 <registers implements="DMA_CH" name="CH1" offset="0x20" text="DMA Channel 1"/>
365 <registers implements="DMA_CH" name="CH2" offset="0x30" text="DMA Channel 2"/>
366 <registers implements="DMA_CH" name="CH3" offset="0x40" text="DMA Channel 3"/>
367 </registers>
368 </module>
369 <module class="EVSYS">
370 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="EVSYS" text="Event System">
371 <reg size="1" name="CH0MUX" offset="0x00" text="Event Channel 0 Multiplexer">
372 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 0 Multiplexer" enum="EVSYS_CHMUX"/>
373 </reg>
374 <reg size="1" name="CH1MUX" offset="0x01" text="Event Channel 1 Multiplexer">
375 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 1 Multiplexer" enum="EVSYS_CHMUX"/>
376 </reg>
377 <reg size="1" name="CH2MUX" offset="0x02" text="Event Channel 2 Multiplexer">
378 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 2 Multiplexer" enum="EVSYS_CHMUX"/>
379 </reg>
380 <reg size="1" name="CH3MUX" offset="0x03" text="Event Channel 3 Multiplexer">
381 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 3 Multiplexer" enum="EVSYS_CHMUX"/>
382 </reg>
383 <reg size="1" name="CH4MUX" offset="0x04" text="Event Channel 4 Multiplexer">
384 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 4 Multiplexer" enum="EVSYS_CHMUX"/>
385 </reg>
386 <reg size="1" name="CH5MUX" offset="0x05" text="Event Channel 5 Multiplexer">
387 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 5 Multiplexer" enum="EVSYS_CHMUX"/>
388 </reg>
389 <reg size="1" name="CH6MUX" offset="0x06" text="Event Channel 6 Multiplexer">
390 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 6 Multiplexer" enum="EVSYS_CHMUX"/>
391 </reg>
392 <reg size="1" name="CH7MUX" offset="0x07" text="Event Channel 7 Multiplexer">
393 <bitfield name="CHMUX" mask="0xFF" text="Event Channel 7 Multiplexer" enum="EVSYS_CHMUX"/>
394 </reg>
395 <reg size="1" name="CH0CTRL" offset="0x08" text="Channel 0 Control Register">
396 <bitfield name="QDIRM" mask="0x60" text="Quadrature Decoder Index Recognition Mode"/>
397 <bitfield name="QDIEN" mask="0x10" text="Quadrature Decoder Index Enable"/>
398 <bitfield name="QDEN" mask="0x08" text="Quadrature Decoder Enable"/>
399 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
400 </reg>
401 <reg size="1" name="CH1CTRL" offset="0x09" text="Channel 1 Control Register">
402 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
403 </reg>
404 <reg size="1" name="CH2CTRL" offset="0x0A" text="Channel 2 Control Register">
405 <bitfield name="QDIRM" mask="0x60" text="Quadrature Decoder Index Recognition Mode" enum="EVSYS_QDIRM"/>
406 <bitfield name="QDIEN" mask="0x10" text="Quadrature Decoder Index Enable"/>
407 <bitfield name="QDEN" mask="0x08" text="Quadrature Decoder Enable"/>
408 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
409 </reg>
410 <reg size="1" name="CH3CTRL" offset="0x0B" text="Channel 3 Control Register">
411 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
412 </reg>
413 <reg size="1" name="CH4CTRL" offset="0x0C" text="Channel 4 Control Register">
414 <bitfield name="QDIRM" mask="0x60" text="Quadrature Decoder Index Recognition Mode" enum="EVSYS_QDIRM"/>
415 <bitfield name="QDIEN" mask="0x10" text="Quadrature Decoder Index Enable"/>
416 <bitfield name="QDEN" mask="0x08" text="Quadrature Decoder Enable"/>
417 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
418 </reg>
419 <reg size="1" name="CH5CTRL" offset="0x0D" text="Channel 5 Control Register">
420 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
421 </reg>
422 <reg size="1" name="CH6CTRL" offset="0x0E" text="Channel 6 Control Register">
423 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="EVSYS_DIGFILT"/>
424 </reg>
425 <reg size="1" name="CH7CTRL" offset="0x0F" text="Channel 7 Control Register">
426 <bitfield name="DIGFILT" mask="0x07" text="Digital Filter" enum="DIGFILT"/>
427 </reg>
428 <reg size="1" name="STROBE" offset="0x10" text="Event Strobe"/>
429 <reg size="1" name="DATA" offset="0x11" text="Event Data"/>
430 </registers>
431 </module>
432 <module class="NVM">
433 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="NVM" text="Non-volatile Memory Controller">
434 <reg size="1" name="ADDR0" offset="0x00" text="Address Register 0"/>
435 <reg size="1" name="ADDR1" offset="0x01" text="Address Register 1"/>
436 <reg size="1" name="ADDR2" offset="0x02" text="Address Register 2"/>
437 <reg offset="0x03"/>
438 <reg size="1" name="DATA0" offset="0x04" text="Data Register 0"/>
439 <reg size="1" name="DATA1" offset="0x05" text="Data Register 1"/>
440 <reg size="1" name="DATA2" offset="0x06" text="Data Register 2"/>
441 <reg offset="0x07"/>
442 <reg offset="0x08"/>
443 <reg offset="0x09"/>
444 <reg size="1" name="CMD" offset="0x0A" text="Command">
445 <bitfield name="CMD" mask="0xFF" text="Command" enum="NVM_CMD"/>
446 </reg>
447 <reg size="1" name="CTRLA" offset="0x0B" text="Control Register A">
448 <bitfield name="CMDEX" mask="0x01" text="Command Execute"/>
449 </reg>
450 <reg size="1" name="CTRLB" offset="0x0C" text="Control Register B">
451 <bitfield name="EEMAPEN" mask="0x08" text="EEPROM Mapping Enable"/>
452 <bitfield name="FPRM" mask="0x04" text="Flash Power Reduction Enable"/>
453 <bitfield name="EPRM" mask="0x02" text="EEPROM Power Reduction Enable"/>
454 <bitfield name="SPMLOCK" mask="0x01" text="SPM Lock"/>
455 </reg>
456 <reg size="1" name="INTCTRL" offset="0x0D" text="Interrupt Control">
457 <bitfield name="SPMLVL" mask="0x0C" text="SPM Interrupt Level" enum="NVM_SPMLVL"/>
458 <bitfield name="EELVL" mask="0x03" text="EEPROM Interrupt Level" enum="NVM_EELVL"/>
459 </reg>
460 <reg offset="0x0E"/>
461 <reg size="1" name="STATUS" offset="0x0F" text="Status">
462 <bitfield name="NVMBUSY" mask="0x80" text="Non-volatile Memory Busy"/>
463 <bitfield name="FBUSY" mask="0x40" text="Flash Memory Busy"/>
464 <bitfield name="EELOAD" mask="0x02" text="EEPROM Page Buffer Active Loading"/>
465 <bitfield name="FLOAD" mask="0x01" text="Flash Page Buffer Active Loading"/>
466 </reg>
467 <reg size="1" name="LOCKBITS" offset="0x10" text="Lock Bits">
468 <bitfield name="BLBB" mask="0xC0" text="Boot Lock Bits - Boot Section" enum="NVM_BLBB"/>
469 <bitfield name="BLBA" mask="0x30" text="Boot Lock Bits - Application Section" enum="NVM_BLBA"/>
470 <bitfield name="BLBAT" mask="0x0C" text="Boot Lock Bits - Application Table" enum="NVM_BLBAT"/>
471 <bitfield name="LB" mask="0x03" text="Lock Bits" enum="NVM_LB"/>
472 </reg>
473 </registers>
474 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="LOCKBIT" name="NVM_LOCKBITS" text="Lock Bits">
475 <reg size="1" name="LOCKBITS" offset="0x00" text="Lock Bits">
476 <bitfield name="BLBB" mask="0xC0" text="Boot Lock Bits - Boot Section" enum="NVM_BLBB"/>
477 <bitfield name="BLBA" mask="0x30" text="Boot Lock Bits - Application Section" enum="NVM_BLBA"/>
478 <bitfield name="BLBAT" mask="0x0C" text="Boot Lock Bits - Application Table" enum="NVM_BLBAT"/>
479 <bitfield name="LB" mask="0x03" text="Lock Bits" enum="NVM_LB"/>
480 </reg>
481 </registers>
482 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="FUSE" name="NVM_FUSES" text="Fuses">
483 <reg size="1" name="FUSEBYTE0" offset="0x00" text="JTAG User ID">
484 <bitfield name="JTAGUSERID" mask="0xFF" text="JTAG User ID"/>
485 </reg>
486 <reg size="1" name="FUSEBYTE1" offset="0x01" text="Watchdog Configuration">
487 <bitfield name="WDWP" mask="0xF0" text="Watchdog Window Timeout Period" enum="WD"/>
488 <bitfield name="WDP" mask="0x0F" text="Watchdog Timeout Period" enum="WD"/>
489 </reg>
490 <reg size="1" name="FUSEBYTE2" offset="0x02" text="Reset Configuration">
491 <bitfield name="DVSDON" mask="0x80" text="Spike Detector Enable"/>
492 <bitfield name="BOOTRST" mask="0x40" text="Boot Loader Section Reset Vector" enum="BOOTRST"/>
493 <bitfield name="BODACT" mask="0x0C" text="BOD Operation in Active Mode" enum="BOD"/>
494 <bitfield name="BODPD" mask="0x03" text="BOD Operation in Power-Down Mode" enum="BOD"/>
495 </reg>
496 <reg offset="0x03"/>
497 <reg size="1" name="FUSEBYTE4" offset="0x04" text="Start-up Configuration">
498 <bitfield name="SUT" mask="0x0C" text="Start-up Time" enum="SUT"/>
499 <bitfield name="WDLOCK" mask="0x02" text="Watchdog Timer Lock"/>
500 <bitfield name="JTAGEN" mask="0x01" text="JTAG Interface Enable"/>
501 </reg>
502 <reg size="1" name="FUSEBYTE5" offset="0x05" text="EESAVE and BOD Level">
503 <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM Through Chip Erase"/>
504 <bitfield name="BODLVL" mask="0x07" text="Brown Out Detection Voltage Level" enum="BODLVL"/>
505 </reg>
506 </registers>
507 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="SIGNATURES" name="NVM_PROD_SIGNATURES" text="Production Signatures">
508 <reg size="1" name="RCOSC2M" offset="0x00" text="RCOSC 2MHz Calibration Value"/>
509 <reg size="1" name="RCOSC32K" offset="0x02" text="RCOSC 32kHz Calibration Value"/>
510 <reg size="1" name="RCOSC32M" offset="0x03" text="RCOSC 32MHz Calibration Value"/>
511 <reg size="1" name="LOTNUM0" offset="0x08" text="Lot Number, Byte 0, ASCII"/>
512 <reg size="1" name="LOTNUM1" offset="0x09" text="Lot Number, Byte 1, ASCII"/>
513 <reg size="1" name="LOTNUM2" offset="0x0A" text="Lot Number, Byte 2, ASCII"/>
514 <reg size="1" name="LOTNUM3" offset="0x0B" text="Lot Number, Byte 3, ASCII"/>
515 <reg size="1" name="LOTNUM4" offset="0x0C" text="Lot Number, Byte 4, ASCII"/>
516 <reg size="1" name="LOTNUM5" offset="0x0D" text="Lot Number, Byte 5, ASCII"/>
517 <reg size="1" name="WAFNUM" offset="0x10" text="Wafer Number"/>
518 <reg size="2" name="COORDX" offset="0x12" text="Wafer Coordinate X"/>
519 <reg size="2" name="COORDY" offset="0x14" text="Wafer Coordinate Y"/>
520 <reg size="1" name="ADCACAL0" offset="0x20" text="ADCA Calibration Byte 0"/>
521 <reg size="1" name="ADCACAL1" offset="0x21" text="ADCA Calibration Byte 1"/>
522 <reg size="1" name="ADCACAL2" offset="0x22" text="ADCA Calibration Byte 2"/>
523 <reg size="1" name="ADCACAL3" offset="0x23" text="ADCA Calibration Byte 3"/>
524 <reg size="1" name="ADCBCAL0" offset="0x24" text="ADCB Calibration Byte 0"/>
525 <reg size="1" name="ADCBCAL1" offset="0x25" text="ADCB Calibration Byte 1"/>
526 <reg size="1" name="ADCBCAL2" offset="0x26" text="ADCB Calibration Byte 2"/>
527 <reg size="1" name="ADCBCAL3" offset="0x27" text="ADCB Calibration Byte 3"/>
528 <reg size="1" name="DACACAL0" offset="0x30" text="DACA Calibration Byte 0"/>
529 <reg size="1" name="DACACAL1" offset="0x31" text="DACA Calibration Byte 1"/>
530 <reg size="1" name="DACBCAL0" offset="0x32" text="DACB Calibration Byte 0"/>
531 <reg size="1" name="DACBCAL1" offset="0x33" text="DACB Calibration Byte 1"/>
532 </registers>
533 </module>
534 <module class="AC">
535 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="AC" text="Analog Comparator">
536 <reg size="1" name="AC0CTRL" offset="0x00" text="Comparator 0 Control">
537 <bitfield name="INTMODE" mask="0xC0" text="Interrupt Mode" enum="AC_INTMODE"/>
538 <bitfield name="INTLVL" mask="0x30" text="Interrupt Level" enum="AC_INTLVL"/>
539 <bitfield name="HSMODE" mask="0x08" text="High-speed Mode"/>
540 <bitfield name="HYSMODE" mask="0x06" text="Hysteresis Mode" enum="AC_HYSMODE"/>
541 <bitfield name="ENABLE" mask="0x01" text="Enable"/>
542 </reg>
543 <reg size="1" name="AC1CTRL" offset="0x01" text="Comparator 1 Control">
544 <bitfield name="INTMODE" mask="0xC0" text="Interrupt Mode" enum="AC_INTMODE"/>
545 <bitfield name="INTLVL" mask="0x30" text="Interrupt Level" enum="AC_INTLVL"/>
546 <bitfield name="HSMODE" mask="0x08" text="High-speed Mode"/>
547 <bitfield name="HYSMODE" mask="0x06" text="Hysteresis Mode" enum="AC_HYSMODE"/>
548 <bitfield name="ENABLE" mask="0x01" text="Enable"/>
549 </reg>
550 <reg size="1" name="AC0MUXCTRL" offset="0x02" text="Comparator 0 MUX Control">
551 <bitfield name="MUXPOS" mask="0x38" text="MUX Positive Input" enum="AC_MUXPOS"/>
552 <bitfield name="MUXNEG" mask="0x07" text="MUX Negative Input" enum="AC_MUXNEG"/>
553 </reg>
554 <reg size="1" name="AC1MUXCTRL" offset="0x03" text="Comparator 1 MUX Control">
555 <bitfield name="MUXPOS" mask="0x38" text="MUX Positive Input" enum="AC_MUXPOS"/>
556 <bitfield name="MUXNEG" mask="0x07" text="MUX Negative Input" enum="AC_MUXNEG"/>
557 </reg>
558 <reg size="1" name="CTRLA" offset="0x04" text="Control Register A">
559 <bitfield name="AC0OUT" mask="0x01" text="Comparator 0 Output Enable"/>
560 </reg>
561 <reg size="1" name="CTRLB" offset="0x05" text="Control Register B">
562 <bitfield name="SCALEFAC" mask="0x3F" text="VCC Voltage Scaler Factor"/>
563 </reg>
564 <reg size="1" name="WINCTRL" offset="0x06" text="Window Mode Control">
565 <bitfield name="WEN" mask="0x10" text="Window Mode Enable"/>
566 <bitfield name="WINTMODE" mask="0x0C" text="Window Interrupt Mode" enum="AC_WINTMODE"/>
567 <bitfield name="WINTLVL" mask="0x03" text="Window Interrupt Level" enum="AC_WINTLVL"/>
568 </reg>
569 <reg size="1" name="STATUS" offset="0x07" text="Status">
570 <bitfield name="WSTATE" mask="0xC0" text="Window Mode State" enum="AC_WSTATE"/>
571 <bitfield name="AC1STATE" mask="0x20" text="Comparator 1 State"/>
572 <bitfield name="AC0STATE" mask="0x10" text="Comparator 0 State"/>
573 <bitfield name="WIF" mask="0x04" text="Window Mode Interrupt Flag"/>
574 <bitfield name="AC1IF" mask="0x02" text="Comparator 1 Interrupt Flag"/>
575 <bitfield name="AC0IF" mask="0x01" text="Comparator 0 Interrupt Flag"/>
576 </reg>
577 </registers>
578 </module>
579 <module class="ADC">
580 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" name="ADC_CH" text="ADC Channel">
581 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
582 <bitfield name="START" mask="0x80" text="Channel Start Conversion"/>
583 <bitfield name="GAINFAC" mask="0x1C" text="Gain Factor" enum="ADC_CH_GAIN"/>
584 <bitfield name="INPUTMODE" mask="0x03" text="Input Mode Select" enum="ADC_CH_INPUTMODE"/>
585 </reg>
586 <reg size="1" name="MUXCTRL" offset="0x01" text="MUX Control">
587 <bitfield name="MUXPOS" mask="0x78" text="Positive Input Select" enum="ADC_CH_MUXPOS"/>
588 <bitfield name="MUXINT" mask="0x78" text="Internal Input Select" enum="ADC_CH_MUXINT" cond="INPUTMODE==INTERNAL"/>
589 <bitfield name="MUXNEG" mask="0x03" text="Negative Input Select" enum="ADC_CH_MUXNEG"/>
590 </reg>
591 <reg size="1" name="INTCTRL" offset="0x02" text="Channel Interrupt Control">
592 <bitfield name="INTMODE" mask="0x0C" text="Interrupt Mode" enum="ADC_CH_INTMODE"/>
593 <bitfield name="INTLVL" mask="0x03" text="Interrupt Level" enum="ADC_CH_INTLVL"/>
594 </reg>
595 <reg size="1" name="INTFLAGS" offset="0x03" text="Interrupt Flags">
596 <bitfield name="CHIF" mask="0x01" text="Channel Interrupt Flag"/>
597 </reg>
598 <reg size="2" name="RES" offset="0x04" text="Channel Result"/>
599 <reg offset="0x6"/>
600 <reg offset="0x7"/>
601 </registers>
602 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="ADC" text="Analog-to-Digital Converter">
603 <reg size="1" name="CTRLA" offset="0x00" text="Control Register A">
604 <bitfield name="DMASEL" mask="0xE0" text="DMA Selection" enum="ADC_DMASEL"/>
605 <bitfield name="CH3START" mask="0x20" text="Channel 3 Start Conversion"/>
606 <bitfield name="CH2START" mask="0x10" text="Channel 2 Start Conversion"/>
607 <bitfield name="CH1START" mask="0x08" text="Channel 1 Start Conversion"/>
608 <bitfield name="CH0START" mask="0x04" text="Channel 0 Start Conversion"/>
609 <bitfield name="FLUSH" mask="0x02" text="Flush Pipeline"/>
610 <bitfield name="ENABLE" mask="0x01" text="Enable ADC"/>
611 </reg>
612 <reg size="1" name="CTRLB" offset="0x01" text="Control Register B">
613 <bitfield name="CONMODE" mask="0x10" text="Conversion Mode"/>
614 <bitfield name="FREERUN" mask="0x08" text="Free Running Mode Enable"/>
615 <bitfield name="RESOLUTION" mask="0x06" text="Result Resolution" enum="ADC_RESOLUTION"/>
616 </reg>
617 <reg size="1" name="REFCTRL" offset="0x02" text="Reference Control">
618 <bitfield name="REFSEL" mask="0x30" text="Reference Selection" enum="ADC_REFSEL"/>
619 <bitfield name="BANDGAP" mask="0x02" text="Bandgap enable"/>
620 <bitfield name="TEMPREF" mask="0x01" text="Temperature Reference Enable"/>
621 </reg>
622 <reg size="1" name="EVCTRL" offset="0x03" text="Event Control">
623 <bitfield name="SWEEP" mask="0xC0" text="Channel Sweep Selection" enum="ADC_SWEEP"/>
624 <bitfield name="EVSEL" mask="0x38" text="Event Input Select" enum="ADC_EVSEL"/>
625 <bitfield name="EVACT" mask="0x07" text="Event Action Select" enum="ADC_EVACT"/>
626 </reg>
627 <reg size="1" name="PRESCALER" offset="0x04" text="Clock Prescaler">
628 <bitfield name="PRESCALER" mask="0x07" text="Clock Prescaler Selection" enum="ADC_PRESCALER"/>
629 </reg>
630 <reg size="1" name="CALCTRL" offset="0x05" text="Calibration Control Register">
631 <bitfield name="CAL" mask="0x01" text="ADC Calibration Start"/>
632 </reg>
633 <reg size="1" name="INTFLAGS" offset="0x06" text="Interrupt Flags">
634 <bitfield name="CH3IF" mask="0x08" text="Channel 3 Interrupt Flag"/>
635 <bitfield name="CH2IF" mask="0x04" text="Channel 2 Interrupt Flag"/>
636 <bitfield name="CH1IF" mask="0x02" text="Channel 1 Interrupt Flag"/>
637 <bitfield name="CH0IF" mask="0x01" text="Channel 0 Interrupt Flag"/>
638 </reg>
639 <reg offset="0x07"/>
640 <reg offset="0x08"/>
641 <reg offset="0x09"/>
642 <reg offset="0x0A"/>
643 <reg offset="0x0B"/>
644 <reg size="1" name="CALIB" offset="0x0C" text="Calibration Value"/>
645 <reg offset="0x0D"/>
646 <reg offset="0x0E"/>
647 <reg offset="0x0F"/>
648 <reg size="2" name="CH0RES" offset="0x10" text="Channel 0 Result"/>
649 <reg size="2" name="CH1RES" offset="0x12" text="Channel 1 Result"/>
650 <reg size="2" name="CH2RES" offset="0x14" text="Channel 2 Result"/>
651 <reg size="2" name="CH3RES" offset="0x16" text="Channel 3 Result"/>
652 <reg size="2" name="CMP" offset="0x18" text="Compare Value"/>
653 <reg offset="0x1A"/>
654 <reg offset="0x1B"/>
655 <reg offset="0x1C"/>
656 <reg offset="0x1D"/>
657 <reg offset="0x1E"/>
658 <reg offset="0x1F"/>
659 <registers implements="ADC_CH" name="CH0" offset="0x20" text="ADC Channel 0"/>
660 <registers implements="ADC_CH" name="CH1" offset="0x28" text="ADC Channel 1"/>
661 <registers implements="ADC_CH" name="CH2" offset="0x30" text="ADC Channel 2"/>
662 <registers implements="ADC_CH" name="CH3" offset="0x38" text="ADC Channel 3"/>
663 </registers>
664 </module>
665 <module class="DAC">
666 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="DAC" text="Digital-to-Analog Converter">
667 <reg size="1" name="CTRLA" offset="0x00" text="Control Register A">
668 <bitfield name="IDOEN" mask="0x10" text="Internal Output Enable"/>
669 <bitfield name="CH1EN" mask="0x08" text="Channel 1 Output Enable"/>
670 <bitfield name="CH0EN" mask="0x04" text="Channel 0 Output Enable"/>
671 <bitfield name="LPMODE" mask="0x02" text="Low Power Mode"/>
672 <bitfield name="ENABLE" mask="0x01" text="Enable"/>
673 </reg>
674 <reg size="1" name="CTRLB" offset="0x01" text="Control Register B">
675 <bitfield name="CHSEL" mask="0x60" text="Channel Select" enum="DAC_CHSEL"/>
676 <bitfield name="CH1TRIG" mask="0x02" text="Channel 1 Event Trig Enable"/>
677 <bitfield name="CH0TRIG" mask="0x01" text="Channel 0 Event Trig Enable"/>
678 </reg>
679 <reg size="1" name="CTRLC" offset="0x02" text="Control Register C">
680 <bitfield name="REFSEL" mask="0x18" text="Reference Select" enum="DAC_REFSEL"/>
681 <bitfield name="LEFTADJ" mask="0x01" text="Left-adjust Result"/>
682 </reg>
683 <reg size="1" name="EVCTRL" offset="0x03" text="Event Input Control">
684 <bitfield name="EVSEL" mask="0x07" text="Event Input Selection" enum="DAC_EVSEL"/>
685 </reg>
686 <reg size="1" name="TIMCTRL" offset="0x04" text="Timing Control">
687 <bitfield name="CONINTVAL" mask="0x70" text="Conversion Intercal" enum="DAC_CONINTVAL"/>
688 <bitfield name="REFRESH" mask="0x0F" text="Refresh Timing Control" enum="DAC_REFRESH"/>
689 </reg>
690 <reg size="1" name="STATUS" offset="0x05" text="Status">
691 <bitfield name="CH1DRE" mask="0x02" text="Channel 1 Data Register Empty"/>
692 <bitfield name="CH0DRE" mask="0x01" text="Channel 0 Data Register Empty"/>
693 </reg>
694 <reg offset="0x06"/>
695 <reg offset="0x07"/>
696 <reg size="1" name="GAINCAL" offset="0x08" text="Gain Calibration"/>
697 <reg size="1" name="OFFSETCAL" offset="0x09" text="Offset Calibration"/>
698 <reg offset="0x0A"/>
699 <reg offset="0x0B"/>
700 <reg offset="0x0C"/>
701 <reg offset="0x0D"/>
702 <reg offset="0x0E"/>
703 <reg offset="0x0F"/>
704 <reg offset="0x10"/>
705 <reg offset="0x11"/>
706 <reg offset="0x12"/>
707 <reg offset="0x13"/>
708 <reg offset="0x14"/>
709 <reg offset="0x15"/>
710 <reg offset="0x16"/>
711 <reg offset="0x17"/>
712 <reg size="2" name="CH0DATA" offset="0x18" text="Channel 0 Data"/>
713 <reg size="2" name="CH1DATA" offset="0x1A" text="Channel 1 Data"/>
714 </registers>
715 </module>
716 <module class="RTC">
717 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="RTC" text="Real-Time Clock">
718 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
719 <bitfield name="PRESCALER" mask="0x07" text="Prescaling Factor" enum="RTC_PRESCALER"/>
720 </reg>
721 <reg size="1" name="STATUS" offset="0x01" text="Status Register">
722 <bitfield name="SYNCBUSY" mask="0x01" text="Synchronization Busy Flag"/>
723 </reg>
724 <reg size="1" name="INTCTRL" offset="0x02" text="Interrupt Control Register">
725 <bitfield name="COMPINTLVL" mask="0x0C" text="Compare Match Interrupt Level" enum="RTC_COMPINTLVL"/>
726 <bitfield name="OVFINTLVL" mask="0x03" text="Overflow Interrupt Level" enum="RTC_OVFINTLVL"/>
727 </reg>
728 <reg size="1" name="INTFLAGS" offset="0x03" text="Interrupt Flags">
729 <bitfield name="COMPIF" mask="0x02" text="Compare Match Interrupt Flag"/>
730 <bitfield name="OVFIF" mask="0x01" text="Overflow Interrupt Flag"/>
731 </reg>
732 <reg size="1" name="TEMP" offset="0x04" text="Temporary register"/>
733 <reg offset="0x05"/>
734 <reg offset="0x06"/>
735 <reg offset="0x07"/>
736 <reg size="2" name="CNT" offset="0x08" text="Count Register"/>
737 <reg size="2" name="PER" offset="0x0A" text="Period Register"/>
738 <reg size="2" name="COMP" offset="0x0C" text="Compare Register"/>
739 </registers>
740 </module>
741 <module class="EBI">
742 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" name="EBI_CS" text="EBI Chip Select Module">
743 <reg size="1" name="CTRLA" offset="0x00" text="Chip Select Control Register A">
744 <bitfield name="ASPACE" mask="0x7C" text="Address Space" enum="EBI_CS_ASPACE"/>
745 <bitfield name="MODE" mask="0x03" text="Memory Mode" enum="EBI_CS_MODE"/>
746 </reg>
747 <reg size="1" name="CTRLB" offset="0x01" text="Chip Select Control Register B">
748 <bitfield name="SRWS" mask="0x07" text="SRAM Wait State Cycles" cond="CTRLA.MODE != SDRAM"/>
749 <bitfield name="SDINITDONE" mask="0x80" text="SDRAM Initialization Done" cond="CTRLA.MODE == SDRAM"/>
750 <bitfield name="SDSREN" mask="0x04" text="SDRAM Self-refresh Enable" cond="CTRLA.MODE == SDRAM"/>
751 <bitfield name="SDMODE" mask="0x03" text="SDRAM Mode" enum="EBI_CS_SDMODE" cond="CTRLA.MODE == SDRAM"/>
752 </reg>
753 <reg size="2" name="BASEADDR" offset="0x02" text="Chip Select Base Address"/>
754 </registers>
755 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="EBI" text="External Bus Interface">
756 <reg size="1" name="CTRL" offset="0x00" text="Control">
757 <bitfield name="SDDATAW" mask="0xC0" text="SDRAM Data Width Setting" enum="EBI_SDDATAW"/>
758 <bitfield name="LPCMODE" mask="0x30" text="SRAM LPC Mode" enum="EBI_LPCMODE"/>
759 <bitfield name="SRMODE" mask="0x0C" text="SRAM Mode" enum="EBI_SRMODE"/>
760 <bitfield name="IFMODE" mask="0x03" text="Interface Mode" enum="EBI_IFMODE"/>
761 </reg>
762 <reg size="1" name="SDRAMCTRLA" offset="0x01" text="SDRAM Control Register A">
763 <bitfield name="SDCAS" mask="0x08" text="SDRAM CAS Latency Setting"/>
764 <bitfield name="SDROW" mask="0x04" text="SDRAM ROW Bits Setting"/>
765 <bitfield name="SDCOL" mask="0x03" text="SDRAM Column Bits Setting" enum="EBI_SDCOL"/>
766 </reg>
767 <reg offset="0x02"/>
768 <reg offset="0x03"/>
769 <reg size="2" name="REFRESH" offset="0x04" text="SDRAM Refresh Period"/>
770 <reg size="2" name="INITDLY" offset="0x06" text="SDRAM Initialization Delay"/>
771 <reg size="1" name="SDRAMCTRLB" offset="0x08" text="SDRAM Control Register B">
772 <bitfield name="MRDLY" mask="0xC0" text="SDRAM Mode Register Delay" enum="EBI_MRDLY"/>
773 <bitfield name="ROWCYCDLY" mask="0x38" text="SDRAM Row Cycle Delay" enum="EBI_ROWCYCDLY"/>
774 <bitfield name="RPDLY" mask="0x07" text="SDRAM Row-to-Precharge Delay" enum="EBI_RPDLY"/>
775 </reg>
776 <reg size="1" name="SDRAMCTRLC" offset="0x09" text="SDRAM Control Register C">
777 <bitfield name="WRDLY" mask="0xC0" text="SDRAM Write Recovery Delay" enum="EBI_WRDLY"/>
778 <bitfield name="ESRDLY" mask="0x38" text="SDRAM Exit-Self-refresh-to-Active Delay" enum="EBI_ESRDLY"/>
779 <bitfield name="ROWCOLDLY" mask="0x07" text="SDRAM Row-to-Column Delay" enum="EBI_ROWCOLDLY"/>
780 </reg>
781 <reg offset="0x0A"/>
782 <reg offset="0x0B"/>
783 <reg offset="0x0C"/>
784 <reg offset="0x0D"/>
785 <reg offset="0x0E"/>
786 <reg offset="0x0F"/>
787 <registers implements="EBI_CS" offset="0x10" name="CS0" text="Chip Select 0"/>
788 <registers implements="EBI_CS" offset="0x14" name="CS1" text="Chip Select 1"/>
789 <registers implements="EBI_CS" offset="0x18" name="CS2" text="Chip Select 2"/>
790 <registers implements="EBI_CS" offset="0x1C" name="CS3" text="Chip Select 3"/>
791 </registers>
792 </module>
793 <module class="TWI">
794 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" name="TWI_MASTER">
795 <reg size="1" name="CTRLA" offset="0x01" text="Control Register A">
796 <bitfield name="INTLVL" mask="0xC0" text="Interrupt Level" enum="TWI_MASTER_INTLVL"/>
797 <bitfield name="RIEN" mask="0x20" text="Read Interrupt Enable"/>
798 <bitfield name="WIEN" mask="0x10" text="Write Interrupt Enable"/>
799 <bitfield name="ENABLE" mask="0x08" text="Enable TWI Master"/>
800 </reg>
801 <reg size="1" name="CTRLB" offset="0x02" text="Control Register B">
802 <bitfield name="TIMEOUT" mask="0x0C" text="Inactive Bus Timeout" enum="TWI_MASTER_TIMEOUT"/>
803 <bitfield name="QCEN" mask="0x02" text="Quick Command Enable"/>
804 <bitfield name="SMEN" mask="0x01" text="Smart Mode Enable"/>
805 </reg>
806 <reg size="1" name="CTRLC" offset="0x03" text="Control Register C">
807 <bitfield name="ACKACT" mask="0x04" text="Acknowledge Action"/>
808 <bitfield name="CMD" mask="0x03" text="Command" enum="TWI_MASTER_CMD"/>
809 </reg>
810 <reg size="1" name="STATUS" offset="0x04" text="Status Register">
811 <bitfield name="RIF" mask="0x80" text="Read Interrupt Flag"/>
812 <bitfield name="WIF" mask="0x40" text="Write Interrupt Flag"/>
813 <bitfield name="CLKHOLD" mask="0x20" text="Clock Hold"/>
814 <bitfield name="RXACK" mask="0x10" text="Received Acknowledge"/>
815 <bitfield name="ARBLOST" mask="0x08" text="Arbitration Lost"/>
816 <bitfield name="BUSERR" mask="0x04" text="Bus Error"/>
817 <bitfield name="BUSSTATE" mask="0x03" text="Bus State" enum="TWI_MASTER_BUSSTATE"/>
818 </reg>
819 <reg size="1" name="BAUD" offset="0x05" text="Baurd Rate Control Register"/>
820 <reg size="1" name="ADDR" offset="0x06" text="Address Register"/>
821 <reg size="1" name="DATA" offset="0x07" text="Data Register"/>
822 </registers>
823 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" name="TWI_SLAVE">
824 <reg size="1" name="CTRLA" offset="0x00" text="Control Register A">
825 <bitfield name="INTLVL" mask="0xC0" text="Interrupt Level" enum="TWI_SLAVE_INTLVL"/>
826 <bitfield name="DIEN" mask="0x20" text="Data Interrupt Enable"/>
827 <bitfield name="APIEN" mask="0x10" text="Address/Stop Interrupt Enable"/>
828 <bitfield name="ENABLE" mask="0x08" text="Enable TWI Slave"/>
829 <bitfield name="PIEN" mask="0x04" text="Stop Interrupt Enable"/>
830 <bitfield name="PMEN" mask="0x02" text="Promiscuous Mode Enable"/>
831 <bitfield name="SMEN" mask="0x01" text="Smart Mode Enable"/>
832 </reg>
833 <reg size="1" name="CTRLB" offset="0x01" text="Control Register B">
834 <bitfield name="ACKACT" mask="0x04" text="Acknowledge Action"/>
835 <bitfield name="CMD" mask="0x03" text="Command" enum="TWI_SLAVE_CMD"/>
836 </reg>
837 <reg size="1" name="STATUS" offset="0x02" text="Status Register">
838 <bitfield name="DIF" mask="0x80" text="Data Interrupt Flag"/>
839 <bitfield name="APIF" mask="0x40" text="Address/Stop Interrupt Flag"/>
840 <bitfield name="CLKHOLD" mask="0x20" text="Clock Hold"/>
841 <bitfield name="RXACK" mask="0x10" text="Received Acknowledge"/>
842 <bitfield name="COLL" mask="0x08" text="Collision"/>
843 <bitfield name="BUSERR" mask="0x04" text="Bus Error"/>
844 <bitfield name="DIR" mask="0x02" text="Read/Write Direction"/>
845 <bitfield name="AP" mask="0x01" text="Slave Address or Stop"/>
846 </reg>
847 <reg size="1" name="ADDR" offset="0x03" text="Address Register"/>
848 <reg size="1" name="DATA" offset="0x04" text="Data Register"/>
849 </registers>
850 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="TWI" text="Two-Wire Interface">
851 <reg size="1" name="CTRL" offset="0x00" text="TWI Common Control Register">
852 <bitfield name="SDAHOLD" mask="0x02" text="SDA Hold Time Enable"/>
853 <bitfield name="EDIEN" mask="0x01" text="External Driver Interface Enable"/>
854 </reg>
855 <registers implements="TWI_MASTER" offset="0x0000" name="MASTER" text="TWI master module"/>
856 <registers implements="TWI_SLAVE" offset="0x0008" name="SLAVE" text="TWI slave module"/>
857 </registers>
858 </module>
859 <module class="PORT">
860 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="PORTCFG" text="I/O port Configuration">
861 <reg size="1" name="MPCMASK" offset="0x00" text="Multi-pin Configuration Mask"/>
862 <reg offset="0x01"/>
863 <reg size="1" name="VPCTRLA" offset="0x02" text="Virtual Port Control Register A">
864 <bitfield name="VP1MAP" mask="0xF0" text="Virtual Port 1 Mapping" enum="PORTCFG_VP1MAP"/>
865 <bitfield name="VP0MAP" mask="0x0F" text="Virtual Port 0 Mapping" enum="PORTCFG_VP0MAP"/>
866 </reg>
867 <reg size="1" name="VPCTRLB" offset="0x03" text="Virtual Port Control Register B">
868 <bitfield name="VP3MAP" mask="0xF0" text="Virtual Port 3 Mapping" enum="PORTCFG_VP3MAP"/>
869 <bitfield name="VP2MAP" mask="0x0F" text="Virtual Port 2 Mapping" enum="PORTCFG_VP2MAP"/>
870 </reg>
871 <reg size="1" name="CLKEVOUT" offset="0x04" text="Clock and Event Out Register">
872 <bitfield name="CLKOUT" mask="0x30" text="Clock Output Port" enum="PORTCFG_CLKOUT"/>
873 <bitfield name="EVOUT" mask="0x03" text="Event Output Port" enum="PORTCFG_EVOUT"/>
874 </reg>
875 </registers>
876 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="VPORT" text="Virtual Port">
877 <reg size="1" name="DIR" offset="0x00" text="I/O Port Data Direction"/>
878 <reg size="1" name="OUT" offset="0x01" text="I/O Port Output"/>
879 <reg size="1" name="IN" offset="0x02" text="I/O Port Input"/>
880 <reg size="1" name="INTFLAGS" offset="0x03" text="Interrupt Flag Register">
881 <bitfield name="INT1IF" mask="0x02" text="Port Interrupt 1 Flag"/>
882 <bitfield name="INT0IF" mask="0x01" text="Port Interrupt 0 Flag"/>
883 </reg>
884 </registers>
885 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="PORT" text="I/O Ports">
886 <reg size="1" name="DIR" offset="0x00" text="I/O Port Data Direction"/>
887 <reg size="1" name="DIRSET" offset="0x01" text="I/O Port Data Direction Set"/>
888 <reg size="1" name="DIRCLR" offset="0x02" text="I/O Port Data Direction Clear"/>
889 <reg size="1" name="DIRTGL" offset="0x03" text="I/O Port Data Direction Toggle"/>
890 <reg size="1" name="OUT" offset="0x04" text="I/O Port Output"/>
891 <reg size="1" name="OUTSET" offset="0x05" text="I/O Port Output Set"/>
892 <reg size="1" name="OUTCLR" offset="0x06" text="I/O Port Output Clear"/>
893 <reg size="1" name="OUTTGL" offset="0x07" text="I/O Port Output Toggle"/>
894 <reg size="1" name="IN" offset="0x08" text="I/O port Input"/>
895 <reg size="1" name="INTCTRL" offset="0x09" text="Interrupt Control Register">
896 <bitfield name="INT1LVL" mask="0x0C" text="Port Interrupt 1 Level" enum="PORT_INT1LVL"/>
897 <bitfield name="INT0LVL" mask="0x03" text="Port Interrupt 0 Level" enum="PORT_INT0LVL"/>
898 </reg>
899 <reg size="1" name="INT0MASK" offset="0x0A" text="Port Interrupt 0 Mask"/>
900 <reg size="1" name="INT1MASK" offset="0x0B" text="Port Interrupt 1 Mask"/>
901 <reg size="1" name="INTFLAGS" offset="0x0C" text="Interrupt Flag Register">
902 <bitfield name="INT1IF" mask="0x02" text="Port Interrupt 1 Flag"/>
903 <bitfield name="INT0IF" mask="0x01" text="Port Interrupt 0 Flag"/>
904 </reg>
905 <reg offset="0x0D"/>
906 <reg offset="0x0E"/>
907 <reg offset="0x0F"/>
908 <reg size="1" name="PIN0CTRL" offset="0x10" text="Pin 0 Control Register">
909 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
910 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
911 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
912 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
913 </reg>
914 <reg size="1" name="PIN1CTRL" offset="0x11" text="Pin 1 Control Register">
915 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
916 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
917 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
918 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
919 </reg>
920 <reg size="1" name="PIN2CTRL" offset="0x12" text="Pin 2 Control Register">
921 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
922 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
923 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
924 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
925 </reg>
926 <reg size="1" name="PIN3CTRL" offset="0x13" text="Pin 3 Control Register">
927 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
928 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
929 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
930 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
931 </reg>
932 <reg size="1" name="PIN4CTRL" offset="0x14" text="Pin 4 Control Register">
933 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
934 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
935 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
936 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
937 </reg>
938 <reg size="1" name="PIN5CTRL" offset="0x15" text="Pin 5 Control Register">
939 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
940 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
941 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
942 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
943 </reg>
944 <reg size="1" name="PIN6CTRL" offset="0x16" text="Pin 6 Control Register">
945 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
946 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
947 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
948 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
949 </reg>
950 <reg size="1" name="PIN7CTRL" offset="0x17" text="Pin 7 Control Register">
951 <bitfield name="SRLEN" mask="0x80" text="Slew Rate Enable"/>
952 <bitfield name="INVEN" mask="0x40" text="Inverted I/O Enable"/>
953 <bitfield name="OPC" mask="0x38" text="Output/Pull Configuration" enum="PORT_OPC"/>
954 <bitfield name="ISC" mask="0x07" text="Input/Sense Configuration" enum="PORT_ISC"/>
955 </reg>
956 </registers>
957 </module>
958 <module class="TC">
959 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="TC0" text="16-bit Timer/Counter 0">
960 <reg size="1" name="CTRLA" offset="0x00" text="Control Register A">
961 <bitfield name="CLKSEL" mask="0x0F" text="Clock Selection" enum="TC_CLKSEL"/>
962 </reg>
963 <reg size="1" name="CTRLB" offset="0x01" text="Control Register B">
964 <bitfield name="CCDEN" mask="0x80" text="Compare or Capture D Enable"/>
965 <bitfield name="CCCEN" mask="0x40" text="Compare or Capture C Enable"/>
966 <bitfield name="CCBEN" mask="0x20" text="Compare or Capture B Enable"/>
967 <bitfield name="CCAEN" mask="0x10" text="Compare or Capture A Enable"/>
968 <bitfield name="WGMODE" mask="0x07" text="Waveform generation mode" enum="TC_WGMODE"/>
969 </reg>
970 <reg size="1" name="CTRLC" offset="0x02" text="Control register C">
971 <bitfield name="CMPD" mask="0x08" text="Compare D Output Value"/>
972 <bitfield name="CMPC" mask="0x04" text="Compare C Output Value"/>
973 <bitfield name="CMPB" mask="0x02" text="Compare B Output Value"/>
974 <bitfield name="CMPA" mask="0x01" text="Compare A Output Value"/>
975 </reg>
976 <reg size="1" name="CTRLD" offset="0x03" text="Control Register D">
977 <bitfield name="EVACT" mask="0xE0" text="Event Action" enum="TC_EVACT"/>
978 <bitfield name="EVDLY" mask="0x10" text="Event Delay"/>
979 <bitfield name="EVSEL" mask="0x0F" text="Event Source Select" enum="TC_EVSEL"/>
980 </reg>
981 <reg size="1" name="CTRLE" offset="0x04" text="Control Register E">
982 <bitfield name="DTHM" mask="0x02" text="Dead Time Hold Mode"/>
983 <bitfield name="BYTEM" mask="0x01" text="Byte Mode"/>
984 </reg>
985 <reg offset="0x05"/>
986 <reg size="1" name="INTCTRLA" offset="0x06" text="Interrupt Control Register A">
987 <bitfield name="ERRINTLVL" mask="0x0C" text="Error Interrupt Level" enum="TC_ERRINTLVL"/>
988 <bitfield name="OVFINTLVL" mask="0x03" text="Overflow interrupt level" enum="TC_OVFINTLVL"/>
989 </reg>
990 <reg size="1" name="INTCTRLB" offset="0x07" text="Interrupt Control Register B">
991 <bitfield name="CCDINTLVL" mask="0xC0" text="Compare or Capture D Interrupt Level" enum="TC_CCDINTLVL"/>
992 <bitfield name="CCCINTLVL" mask="0x30" text="Compare or Capture C Interrupt Level" enum="TC_CCCINTLVL"/>
993 <bitfield name="CCBINTLVL" mask="0x0C" text="Compare or Capture B Interrupt Level" enum="TC_CCBINTLVL"/>
994 <bitfield name="CCAINTLVL" mask="0x03" text="Compare or Capture A Interrupt Level" enum="TC_CCAINTLVL"/>
995 </reg>
996 <reg size="1" name="CTRLFCLR" offset="0x08" text="Control Register F Clear">
997 <bitfield name="CMD" mask="0x0C" text="Command"/>
998 <bitfield name="LUPD" mask="0x02" text="Lock Update"/>
999 <bitfield name="DIR" mask="0x01" text="Direction"/>
1000 </reg>
1001 <reg size="1" name="CTRLFSET" offset="0x09" text="Control Register F Set">
1002 <bitfield name="CMD" mask="0x0C" text="Command" enum="TC_CMD"/>
1003 <bitfield name="LUPD" mask="0x02" text="Lock Update"/>
1004 <bitfield name="DIR" mask="0x01" text="Direction"/>
1005 </reg>
1006 <reg size="1" name="CTRLGCLR" offset="0x0A" text="Control Register G Clear">
1007 <bitfield name="CCDBV" mask="0x10" text="Compare or Capture D Buffer Valid"/>
1008 <bitfield name="CCCBV" mask="0x08" text="Compare or Capture C Buffer Valid"/>
1009 <bitfield name="CCBBV" mask="0x04" text="Compare or Capture B Buffer Valid"/>
1010 <bitfield name="CCABV" mask="0x02" text="Compare or Capture A Buffer Valid"/>
1011 <bitfield name="PERBV" mask="0x01" text="Period Buffer Valid"/>
1012 </reg>
1013 <reg size="1" name="CTRLGSET" offset="0x0B" text="Control Register G Set">
1014 <bitfield name="CCDBV" mask="0x10" text="Compare or Capture D Buffer Valid"/>
1015 <bitfield name="CCCBV" mask="0x08" text="Compare or Capture C Buffer Valid"/>
1016 <bitfield name="CCBBV" mask="0x04" text="Compare or Capture B Buffer Valid"/>
1017 <bitfield name="CCABV" mask="0x02" text="Compare or Capture A Buffer Valid"/>
1018 <bitfield name="PERBV" mask="0x01" text="Period Buffer Valid"/>
1019 </reg>
1020 <reg size="1" name="INTFLAGS" offset="0x0C" text="Interrupt Flag Register">
1021 <bitfield name="CCDIF" mask="0x80" text="Compare or Capture D Interrupt Flag"/>
1022 <bitfield name="CCCIF" mask="0x40" text="Compare or Capture C Interrupt Flag"/>
1023 <bitfield name="CCBIF" mask="0x20" text="Compare or Capture B Interrupt Flag"/>
1024 <bitfield name="CCAIF" mask="0x10" text="Compare or Capture A Interrupt Flag"/>
1025 <bitfield name="ERRIF" mask="0x02" text="Error Interrupt Flag"/>
1026 <bitfield name="OVFIF" mask="0x01" text="Overflow Interrupt Flag"/>
1027 </reg>
1028 <reg offset="0x0D"/>
1029 <reg offset="0x0E"/>
1030 <reg size="1" name="TEMP" offset="0x0F" text="Temporary Register For 16-bit Access"/>
1031 <reg offset="0x10"/>
1032 <reg offset="0x11"/>
1033 <reg offset="0x12"/>
1034 <reg offset="0x13"/>
1035 <reg offset="0x14"/>
1036 <reg offset="0x15"/>
1037 <reg offset="0x16"/>
1038 <reg offset="0x17"/>
1039 <reg offset="0x18"/>
1040 <reg offset="0x19"/>
1041 <reg offset="0x1A"/>
1042 <reg offset="0x1B"/>
1043 <reg offset="0x1C"/>
1044 <reg offset="0x1D"/>
1045 <reg offset="0x1E"/>
1046 <reg offset="0x1F"/>
1047 <reg size="2" name="CNT" offset="0x20" text="Count"/>
1048 <reg offset="0x22"/>
1049 <reg offset="0x23"/>
1050 <reg offset="0x24"/>
1051 <reg offset="0x25"/>
1052 <reg size="2" name="PER" offset="0x26" text="Period"/>
1053 <reg size="2" name="CCA" offset="0x28" text="Compare or Capture A"/>
1054 <reg size="2" name="CCB" offset="0x2A" text="Compare or Capture B"/>
1055 <reg size="2" name="CCC" offset="0x2C" text="Compare or Capture C"/>
1056 <reg size="2" name="CCD" offset="0x2E" text="Compare or Capture D"/>
1057 <reg offset="0x30"/>
1058 <reg offset="0x31"/>
1059 <reg offset="0x32"/>
1060 <reg offset="0x33"/>
1061 <reg offset="0x34"/>
1062 <reg offset="0x35"/>
1063 <reg size="2" name="PERBUF" offset="0x36" text="Period Buffer"/>
1064 <reg size="2" name="CCABUF" offset="0x38" text="Compare Or Capture A Buffer"/>
1065 <reg size="2" name="CCBBUF" offset="0x3A" text="Compare Or Capture B Buffer"/>
1066 <reg size="2" name="CCCBUF" offset="0x3C" text="Compare Or Capture C Buffer"/>
1067 <reg size="2" name="CCDBUF" offset="0x3E" text="Compare Or Capture D Buffer"/>
1068 </registers>
1069 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="TC1" text="16-bit Timer/Counter 1">
1070 <reg size="1" name="CTRLA" offset="0x00" text="Control Register A">
1071 <bitfield name="CLKSEL" mask="0x0F" text="Clock Selection" enum="TC_CLKSEL"/>
1072 </reg>
1073 <reg size="1" name="CTRLB" offset="0x01" text="Control Register B">
1074 <bitfield name="CCBEN" mask="0x20" text="Compare or Capture B Enable"/>
1075 <bitfield name="CCAEN" mask="0x10" text="Compare or Capture A Enable"/>
1076 <bitfield name="WGMODE" mask="0x07" text="Waveform generation mode" enum="TC_WGMODE"/>
1077 </reg>
1078 <reg size="1" name="CTRLC" offset="0x02" text="Control register C">
1079 <bitfield name="CMPB" mask="0x02" text="Compare B Output Value"/>
1080 <bitfield name="CMPA" mask="0x01" text="Compare A Output Value"/>
1081 </reg>
1082 <reg size="1" name="CTRLD" offset="0x03" text="Control Register D">
1083 <bitfield name="EVACT" mask="0xE0" text="Event Action" enum="TC_EVACT"/>
1084 <bitfield name="EVDLY" mask="0x10" text="Event Delay"/>
1085 <bitfield name="EVSEL" mask="0x0F" text="Event Source Select" enum="TC_EVSEL"/>
1086 </reg>
1087 <reg size="1" name="CTRLE" offset="0x04" text="Control Register E">
1088 <bitfield name="DTHM" mask="0x02" text="Dead Time Hold Mode"/>
1089 <bitfield name="BYTEM" mask="0x01" text="Byte Mode"/>
1090 </reg>
1091 <reg offset="0x05"/>
1092 <reg size="1" name="INTCTRLA" offset="0x06" text="Interrupt Control Register A">
1093 <bitfield name="ERRINTLVL" mask="0x0C" text="Error Interrupt Level" enum="TC_ERRINTLVL"/>
1094 <bitfield name="OVFINTLVL" mask="0x03" text="Overflow interrupt level" enum="TC_OVFINTLVL"/>
1095 </reg>
1096 <reg size="1" name="INTCTRLB" offset="0x07" text="Interrupt Control Register B">
1097 <bitfield name="CCBINTLVL" mask="0x0C" text="Compare or Capture B Interrupt Level" enum="TC_CCBINTLVL"/>
1098 <bitfield name="CCAINTLVL" mask="0x03" text="Compare or Capture A Interrupt Level" enum="TC_CCAINTLVL"/>
1099 </reg>
1100 <reg size="1" name="CTRLFCLR" offset="0x08" text="Control Register F Clear">
1101 <bitfield name="CMD" mask="0x0C" text="Command"/>
1102 <bitfield name="LUPD" mask="0x02" text="Lock Update"/>
1103 <bitfield name="DIR" mask="0x01" text="Direction"/>
1104 </reg>
1105 <reg size="1" name="CTRLFSET" offset="0x09" text="Control Register F Set">
1106 <bitfield name="CMD" mask="0x0C" text="Command" enum="TC_CMD"/>
1107 <bitfield name="LUPD" mask="0x02" text="Lock Update"/>
1108 <bitfield name="DIR" mask="0x01" text="Direction"/>
1109 </reg>
1110 <reg size="1" name="CTRLGCLR" offset="0x0A" text="Control Register G Clear">
1111 <bitfield name="CCBBV" mask="0x04" text="Compare or Capture B Buffer Valid"/>
1112 <bitfield name="CCABV" mask="0x02" text="Compare or Capture A Buffer Valid"/>
1113 <bitfield name="PERBV" mask="0x01" text="Period Buffer Valid"/>
1114 </reg>
1115 <reg size="1" name="CTRLGSET" offset="0x0B" text="Control Register G Set">
1116 <bitfield name="CCBBV" mask="0x04" text="Compare or Capture B Buffer Valid"/>
1117 <bitfield name="CCABV" mask="0x02" text="Compare or Capture A Buffer Valid"/>
1118 <bitfield name="PERBV" mask="0x01" text="Period Buffer Valid"/>
1119 </reg>
1120 <reg size="1" name="INTFLAGS" offset="0x0C" text="Interrupt Flag Register">
1121 <bitfield name="CCBIF" mask="0x20" text="Compare or Capture B Interrupt Flag"/>
1122 <bitfield name="CCAIF" mask="0x10" text="Compare or Capture A Interrupt Flag"/>
1123 <bitfield name="ERRIF" mask="0x02" text="Error Interrupt Flag"/>
1124 <bitfield name="OVFIF" mask="0x01" text="Overflow Interrupt Flag"/>
1125 </reg>
1126 <reg offset="0x0D"/>
1127 <reg offset="0x0E"/>
1128 <reg size="1" name="TEMP" offset="0x0F" text="Temporary Register For 16-bit Access"/>
1129 <reg offset="0x10"/>
1130 <reg offset="0x11"/>
1131 <reg offset="0x12"/>
1132 <reg offset="0x13"/>
1133 <reg offset="0x14"/>
1134 <reg offset="0x15"/>
1135 <reg offset="0x16"/>
1136 <reg offset="0x17"/>
1137 <reg offset="0x18"/>
1138 <reg offset="0x19"/>
1139 <reg offset="0x1A"/>
1140 <reg offset="0x1B"/>
1141 <reg offset="0x1C"/>
1142 <reg offset="0x1D"/>
1143 <reg offset="0x1E"/>
1144 <reg offset="0x1F"/>
1145 <reg size="2" name="CNT" offset="0x20" text="Count"/>
1146 <reg offset="0x22"/>
1147 <reg offset="0x23"/>
1148 <reg offset="0x24"/>
1149 <reg offset="0x25"/>
1150 <reg size="2" name="PER" offset="0x26" text="Period"/>
1151 <reg size="2" name="CCA" offset="0x28" text="Compare or Capture A"/>
1152 <reg size="2" name="CCB" offset="0x2A" text="Compare or Capture B"/>
1153 <reg offset="0x2C"/>
1154 <reg offset="0x2D"/>
1155 <reg offset="0x2E"/>
1156 <reg offset="0x2F"/>
1157 <reg offset="0x30"/>
1158 <reg offset="0x31"/>
1159 <reg offset="0x32"/>
1160 <reg offset="0x33"/>
1161 <reg offset="0x34"/>
1162 <reg offset="0x35"/>
1163 <reg size="2" name="PERBUF" offset="0x36" text="Period Buffer"/>
1164 <reg size="2" name="CCABUF" offset="0x38" text="Compare Or Capture A Buffer"/>
1165 <reg size="2" name="CCBBUF" offset="0x3A" text="Compare Or Capture B Buffer"/>
1166 </registers>
1167 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="AWEX" text="Advanced Waveform Extension">
1168 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
1169 <bitfield name="PGM" mask="0x20" text="Pattern Generation Mode"/>
1170 <bitfield name="CWCM" mask="0x10" text="Common Waveform Channel Mode"/>
1171 <bitfield name="DTICCDEN" mask="0x08" text="Dead Time Insertion Compare Channel D Enable"/>
1172 <bitfield name="DTICCCEN" mask="0x04" text="Dead Time Insertion Compare Channel C Enable"/>
1173 <bitfield name="DTICCBEN" mask="0x02" text="Dead Time Insertion Compare Channel B Enable"/>
1174 <bitfield name="DTICCAEN" mask="0x01" text="Dead Time Insertion Compare Channel A Enable"/>
1175 </reg>
1176 <reg offset="0x01"/>
1177 <reg size="1" name="FDEVMASK" offset="0x02" text="Fault Detection Event Mask"/>
1178 <reg size="1" name="FDCTRL" offset="0x03" text="Fault Detection Control Register">
1179 <bitfield name="FDDBD" mask="0x10" text="Fault Detect on Disable Break Disable"/>
1180 <bitfield name="FDMODE" mask="0x04" text="Fault Detect Mode"/>
1181 <bitfield name="FDACT" mask="0x03" text="Fault Detect Action" enum="AWEX_FDACT"/>
1182 </reg>
1183 <reg size="1" name="STATUS" offset="0x04" text="Status Register">
1184 <bitfield name="FDF" mask="0x04" text="Fault Detect Flag"/>
1185 <bitfield name="DTHSBUFV" mask="0x02" text="Dead Time High Side Buffer Valid"/>
1186 <bitfield name="DTLSBUFV" mask="0x01" text="Dead Time Low Side Buffer Valid"/>
1187 </reg>
1188 <reg offset="0x05"/>
1189 <reg size="1" name="DTBOTH" offset="0x06" text="Dead Time Both Sides"/>
1190 <reg size="1" name="DTBOTHBUF" offset="0x07" text="Dead Time Both Sides Buffer"/>
1191 <reg size="1" name="DTLS" offset="0x08" text="Dead Time Low Side"/>
1192 <reg size="1" name="DTHS" offset="0x09" text="Dead Time High Side"/>
1193 <reg size="1" name="DTLSBUF" offset="0x0A" text="Dead Time Low Side Buffer"/>
1194 <reg size="1" name="DTHSBUF" offset="0x0B" text="Dead Time High Side Buffer"/>
1195 <reg size="1" name="OUTOVEN" offset="0x0C" text="Output Override Enable"/>
1196 </registers>
1197 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="HIRES" text="High-Resolution Extension">
1198 <reg size="1" name="CTRL" offset="0x00" text="Control Register">
1199 <bitfield name="HREN" mask="0x03" text="High Resolution Enable" enum="HIRES_HREN"/>
1200 </reg>
1201 </registers>
1202 </module>
1203 <module class="USART">
1204 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="USART" text="Universal Synchronous/Asynchronous Receiver/Transmitter">
1205 <reg size="1" name="DATA" offset="0x00" text="Data Register"/>
1206 <reg size="1" name="STATUS" offset="0x01" text="Status Register">
1207 <bitfield name="RXCIF" mask="0x80" text="Receive Interrupt Flag"/>
1208 <bitfield name="TXCIF" mask="0x40" text="Transmit Interrupt Flag"/>
1209 <bitfield name="DREIF" mask="0x20" text="Data Register Empty Flag"/>
1210 <bitfield name="FERR" mask="0x10" text="Frame Error"/>
1211 <bitfield name="BUFOVF" mask="0x08" text="Buffer Overflow"/>
1212 <bitfield name="PERR" mask="0x04" text="Parity Error"/>
1213 <bitfield name="RXB8" mask="0x01" text="Receive Bit 8"/>
1214 </reg>
1215 <reg offset="0x02"/>
1216 <reg size="1" name="CTRLA" offset="0x03" text="Control Register A">
1217 <bitfield name="RXCINTLVL" mask="0x30" text="Receive Interrupt Level" enum="USART_RXCINTLVL"/>
1218 <bitfield name="TXCINTLVL" mask="0x0C" text="Transmit Interrupt Level" enum="USART_TXCINTLVL"/>
1219 <bitfield name="DREINTLVL" mask="0x03" text="Data Register Empty Interrupt Level" enum="USART_DREINTLVL"/>
1220 </reg>
1221 <reg size="1" name="CTRLB" offset="0x04" text="Control Register B">
1222 <bitfield name="RXEN" mask="0x10" text="Receiver Enable"/>
1223 <bitfield name="TXEN" mask="0x08" text="Transmitter Enable"/>
1224 <bitfield name="CLK2X" mask="0x04" text="Double transmission speed"/>
1225 <bitfield name="MPCM" mask="0x02" text="Multi-processor Communication Mode"/>
1226 <bitfield name="TXB8" mask="0x01" text="Transmit bit 8"/>
1227 </reg>
1228 <reg size="1" name="CTRLC" offset="0x05" text="Control Register C">
1229 <bitfield name="CMODE" mask="0xC0" text="Communication Mode" enum="USART_CMODE"/>
1230 <bitfield name="PMODE" mask="0x30" text="Parity Mode" enum="USART_PMODE"/>
1231 <bitfield name="SBMODE" mask="0x08" text="Stop Bit Mode"/>
1232 <bitfield name="CHSIZE" mask="0x07" text="Character Size" enum="USART_CHSIZE"/>
1233 </reg>
1234 <reg size="1" name="BAUDCTRLA" offset="0x06" text="Baud Rate Control Register A">
1235 <bitfield name="BSEL" mask="0xFF" text="Baud Rate Selection Bits [7:0]"/>
1236 </reg>
1237 <reg size="1" name="BAUDCTRLB" offset="0x07" text="Baud Rate Control Register B">
1238 <bitfield name="BSCALE" mask="0xF0" text="Baud Rate Scale"/>
1239 <bitfield name="BSEL" mask="0x0F" text="Baud Rate Selection bits[11:8]"/>
1240 </reg>
1241 </registers>
1242 </module>
1243 <module class="SPI">
1244 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="SPI" text="Serial Peripheral Interface">
1245 <reg size="1" name="CTRL" offset="0x0" text="Control Register">
1246 <bitfield name="CLK2X" mask="0x80" text="Enable Double Speed"/>
1247 <bitfield name="ENABLE" mask="0x40" text="Enable Module"/>
1248 <bitfield name="DORD" mask="0x20" text="Data Order Setting"/>
1249 <bitfield name="MASTER" mask="0x10" text="Master Operation Enable"/>
1250 <bitfield name="MODE" mask="0x0C" text="SPI Mode" enum="SPI_MODE"/>
1251 <bitfield name="PRESCALER" mask="0x03" text="Prescaler" enum="SPI_PRESCALER"/>
1252 </reg>
1253 <reg size="1" name="INTCTRL" offset="0x01" text="Interrupt Control Register">
1254 <bitfield name="INTLVL" mask="0x03" text="Interrupt level" enum="SPI_INTLVL"/>
1255 </reg>
1256 <reg size="1" name="STATUS" offset="0x02" text="Status Register">
1257 <bitfield name="IF" mask="0x80" text="Interrupt Flag"/>
1258 <bitfield name="WRCOL" mask="0x40" text="Write Collision"/>
1259 </reg>
1260 <reg size="1" name="DATA" offset="0x03" text="Data Register"/>
1261 </registers>
1262 </module>
1263 <module class="IRCOM">
1264 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="IRCOM" text="IR Communication Module">
1265 <reg size="1" name="TXPLCTRL" offset="0x00" text="IrDA Transmitter Pulse Length Control Register"/>
1266 <reg size="1" name="RXPLCTRL" offset="0x01" text="IrDA Receiver Pulse Length Control Register"/>
1267 <reg size="1" name="CTRL" offset="0x02" text="Control Register">
1268 <bitfield name="EVSEL" mask="0x0F" text="Event Channel Select" enum="IRDA_EVSEL"/>
1269 </reg>
1270 </registers>
1271 </module>
1272 <module class="AES">
1273 <registers xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xi="http://www.w3.org/2001/XInclude" memspace="IO" name="AES" text="AES MOdule">
1274 <reg size="1" name="CTRL" offset="0x00" text="AES Control Register">
1275 <bitfield name="START" mask="0x80" text="Start/Run"/>
1276 <bitfield name="AUTO" mask="0x40" text="Auto Start Trigger"/>
1277 <bitfield name="RESET" mask="0x20" text="AES Software Reset"/>
1278 <bitfield name="DECRYPT" mask="0x10" text="Decryption / Direction"/>
1279 <bitfield name="XOR" mask="0x04" text="State XOR Load Enable"/>
1280 </reg>
1281 <reg size="1" name="STATUS" offset="0x01" text="AES Status Register">
1282 <bitfield name="ERROR" mask="0x80" text="AES Error"/>
1283 <bitfield name="SRIF" mask="0x01" text="State Ready Interrupt Flag"/>
1284 </reg>
1285 <reg size="1" name="STATE" offset="0x02" text="AES State Register"/>
1286 <reg size="1" name="KEY" offset="0x03" text="AES Key Register"/>
1287 <reg size="1" name="INTCTRL" offset="0x04" text="AES Interrupt Control Register">
1288 <bitfield name="INTLVL" mask="0x03" text="Interrupt level" enum="AES_INTLVL"/>
1289 </reg>
1290 </registers>
1291 </module>
1292 </hardware>
1293 </device>
Atmel AVR simulator