devices/attiny26

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="12">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$002" name="I/O_PINS">External Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$003" name="TIMER1,CMPA">Timer/Counter1 Compare Match 1A</interrupt>
   9     <interrupt vector="5" address="$004" name="TIMER1,CMPB">Timer/Counter1 Compare Match 1B</interrupt>
  10     <interrupt vector="6" address="$005" name="TIMER1,OVF1">Timer/Counter1 Overflow</interrupt>
  11     <interrupt vector="7" address="$006" name="TIMER0,OVF0">Timer/Counter0 Overflow</interrupt>
  12     <interrupt vector="8" address="$007" name="USI_STRT">USI Start</interrupt>
  13     <interrupt vector="9" address="$008" name="USI_OVF">USI Overflow</interrupt>
  14     <interrupt vector="10" address="$009" name="EE_RDY">EEPROM Ready</interrupt>
  15     <interrupt vector="11" address="$00A" name="ANA_COMP">Analog Comparator</interrupt>
  16     <interrupt vector="12" address="$00B" name="ADC">ADC Conversion Complete</interrupt>
  17   </interrupts>
  18   <memory>
  19     <flash size="2048"/>
  20     <iospace start="$20" stop="$5F"/>
  21     <sram size="128"/>
  22     <eram size="0"/>
  23   </memory>
  24   <ioregisters>
  25     <ioreg name="ADCL" address="$04"/>
  26     <ioreg name="ADCH" address="$05"/>
  27     <ioreg name="ADCSR" address="$06"/>
  28     <ioreg name="ADMUX" address="$07"/>
  29     <ioreg name="ACSR" address="$08"/>
  30     <ioreg name="USICR" address="$0D"/>
  31     <ioreg name="USISR" address="$0E"/>
  32     <ioreg name="USIDR" address="$0F"/>
  33     <ioreg name="PINB" address="$16"/>
  34     <ioreg name="DDRB" address="$17"/>
  35     <ioreg name="PORTB" address="$18"/>
  36     <ioreg name="PINA" address="$19"/>
  37     <ioreg name="DDRA" address="$1A"/>
  38     <ioreg name="PORTA" address="$1B"/>
  39     <ioreg name="EECR" address="$1C"/>
  40     <ioreg name="EEDR" address="$1D"/>
  41     <ioreg name="EEAR" address="$1E"/>
  42     <ioreg name="WDTCR" address="$21"/>
  43     <ioreg name="PLLCSR" address="$29"/>
  44     <ioreg name="OCR1C" address="$2B"/>
  45     <ioreg name="OCR1B" address="$2C"/>
  46     <ioreg name="OCR1A" address="$2D"/>
  47     <ioreg name="TCNT1" address="$2E"/>
  48     <ioreg name="TCCR1B" address="$2F"/>
  49     <ioreg name="TCCR1A" address="$30"/>
  50     <ioreg name="OSCCAL" address="$31"/>
  51     <ioreg name="TCNT0" address="$32"/>
  52     <ioreg name="TCCR0" address="$33"/>
  53     <ioreg name="MCUSR" address="$34"/>
  54     <ioreg name="MCUCR" address="$35"/>
  55     <ioreg name="TIFR" address="$38"/>
  56     <ioreg name="TIMSK" address="$39"/>
  57     <ioreg name="GIFR" address="$3A"/>
  58     <ioreg name="GIMSK" address="$3B"/>
  59     <ioreg name="SP" address="$3D"/>
  60     <ioreg name="SREG" address="$3F"/>
  61   </ioregisters>
  62   <packages>
  63     <package name="PDIP" pins="20">
  64       <pin id="1" name="[MOSI:DI:SDA:'OC1A:PCINT0:PB0]">DI: Data input in USI 3-wire mode. USI 3-wire mode does not override normal port functions., so pin must be configure as an input. SDA: Serial data in USI 2-wire mode. Serial data pin is bi-directional and uses open-col-lector output. The SDA pin is enabled by setting the pin as an output. The pin is pulled low when the PORTB0 or USI shiftregister is zero when DDB0 is set (one). Pull-up is disabled in USI 2-wire mode. OC1A: Inverted Timer/Counter1 PWM Output A: The PB0 pin can serve as an Inverted output for the PWM mode if not used in programming or USI. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function. For further reading on PCINT0 please refer to the manual</pin>
  65       <pin id="2" name="[MISO:DO:OC1A:PCINT0:PB1]">DO: Data output in USI 3-wire mode. Data output (DO) overrides PORTB1 value and it is driven to the port when the data direction bit DDB1 is set (one). However the PORTB1 bit still controls the pullup, enabling pullup if direction is input and PORTB1 is set(one). OC1A: Output compare match output: The PB1 pin can serve as an output for the Timer/Counter1 compare match A. The PB1 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function if not used in programming or USI. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the output compare match out-put OC1A and data output DO in USI 3-wire mode. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function</pin>
  66       <pin id="3" name="[SCK:SCL:'OC1B:PCINT0:PB2]">SCK: Clock input or output in USI 3-wire mode. When the SPI is enabled this pin is con-figured</pin>
  67       <pin id="4" name="[OC1B:PCINT0:PB3]">OC1B: Output compare match output: The PB3 pin can serve as an output for the Timer/Counter1 compare match B. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode. PCINT0: Pin Change Interrupt 0 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate function is the output compare match output OC1B. Digital input is enabled on pin PB3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function</pin>
  68       <pin id="5" name="[VCC]"/>
  69       <pin id="6" name="[GND]"/>
  70       <pin id="7" name="[ADC7:XTAL1:PCINT1:PB4]">ADC7: ADC input channel 7. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL1: Chip clock oscillator pin 1. Used for all chip clock sources except internal cali-brateble RC oscillator and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator or PLL clock as chip clock sources, PB4 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL1 inputs. Digital input is enabled on pin PB4 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functions</pin>
  71       <pin id="8" name="[ADC8:XTAL2:PCINT1:PB5]">ADC8: ADC input channel 8. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the ana-log to digital converter. XTAL2: Chip clock oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC oscillator, external clock and PLL clock. When used as a clock pin, the pin can not be used as an I/O pin. When using internal calibratable RC oscillator, external clock or PLL clock as chip clock sources, PB5 serves as an ordinary I/O pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the XTAL2 outputs. Digital input is enabled on pin PB5 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function</pin>
  72       <pin id="9" name="[ADC9:INT0:T0:PCINT1:PB6]">ADC9: ADC input channel 9. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. INT0: External Interrupt source 0: The PB6 pin can serve as an external interrupt source enabled by setting (one) the bit INT0 in the general input mask register (GIMSK). T0: Timer/Counter0 External Counter Clock Input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 control register (TCCR0). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate functions do not mask the interrupt. The masking alternate functions are the external low level Interrupt source 0 (INT0) and the Timer/Counter0 external counter clock input (T0). Digital input is enabled on pin PB6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio</pin>
  73       <pin id="10" name="[ADC10:'RESET:PCINT1:PB7]">ADC10: ADC input channel 10. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter. RESET: External Reset Input is active low and enabled by unprogramming (“1”) the RSTDISBL fuse. Pullup is activated and output driver and digital input are deactivated when the pin is used as the RESET pin. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as RESET. Digital input is enabled on pin PB7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functi</pin>
  74       <pin id="11" name="[ADC6:AIN1:PA7]">AIN1: Analog Comparator Negative Input and ADC6: ADC input channel 6. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA7 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio</pin>
  75       <pin id="12" name="[ADC5:AIN0:PA6]">AIN0: Analog Comparator Positive Input and ADC5: ADC input channel 5. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator or analog to digital converter. PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the analog comparator.Digital input is enabled on pin PA6 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate functio</pin>
  76       <pin id="13" name="[ADC4:PA5]">ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.</pin>
  77       <pin id="14" name="[ADC3:PA4]">ADC4/ADC3: ADC input channel 4 and 3. Configure the port pins as inputs with the internal pull-ups switched off to avoid the digital port function from interfering with the function of the analog to digital converter.</pin>
  78       <pin id="15" name="[AVCC]"/>
  79       <pin id="16" name="[AGND]"/>
  80       <pin id="17" name="[AREF:PA3]">AREF: External reference for ADC. Pullup and output driver are disabled on PA3 when the pin is used as an external reference or Internal Voltage Reference (2.56V) with external capacitor at the AREF pin by setting (one) the bit REFS0 in the ADC Multiplexer Selection Register (ADMUX). PCINT1: Pin Change Interrupt 1 pin. Pin change interrupt is enabled on pin when global interrupt is enabled, pin change interrupt is enabled and the alternate function do not mask the interrupt. The masking alternate function is the pin usage as an analog refer-ence for the ADC. Digital input is enabled on pin PA3 also in SLEEP modes, if the pin change interrupt is enabled and not masked by the alternate function. Please refer to the manual for further details</pin>
  81       <pin id="18" name="[ADC2:PA2]"/>
  82       <pin id="19" name="[ADC1:PA1]"/>
  83       <pin id="20" name="[ADC0:PA0]"/>
  84     </package>
  85   </packages>
  86   <hardware>
  87 <!--Everything after this needs editing!!!-->
  88     <module class="FUSE">
  89       <registers name="FUSE" memspace="FUSE">
  90           <reg size="1" name="HIGH" offset="0x01">
  91             <bitfield name="RSTDISBL" mask="0x10" text="Reset Disabled (Enable PB7 as i/o pin)" icon=""/>
  92             <bitfield name="SPIEN" mask="0x08" text="Serial program downloading (SPI) enabled" icon=""/>
  93             <bitfield name="EESAVE" mask="0x04" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
  94             <bitfield name="BODLEVEL" mask="0x02" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
  95             <bitfield name="BODEN" mask="0x01" text="Brown-out detection enabled" icon=""/>
  96           </reg>
  97           <reg size="1" name="LOW" offset="0x00">
  98             <bitfield name="CKOPT" mask="0x40" text="CKOPT fuse (operation dependent of CKSEL fuses)" icon=""/>
  99             <bitfield name="PLLCK_SUT_CKSEL" mask="0xBF" text="Select Clock Source" icon="" enum="ENUM_PLLCK_SUT_CKSEL"/>
 100           </reg>
 101         </registers>
 102     </module>
 103     <module class="LOCKBIT">
 104       <registers name="LOCKBIT" memspace="LOCKBIT">
 105           <reg size="1" name="LOCKBIT" offset="0x00">
 106             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 107           </reg>
 108         </registers>
 109     </module>
 110     <module class="AD_CONVERTER">
 111       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 112           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 113             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF"/>
 114             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 115             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 116           </reg>
 117           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 118             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 119             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 120             <bitfield name="ADFR" mask="0x20" text="ADC  Free Running Select" icon=""/>
 121             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 122             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 123             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 124           </reg>
 125           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 126         </registers>
 127     </module>
 128     <module class="ANALOG_COMPARATOR">
 129       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 130           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 131             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 132             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 133             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 134             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 135             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 136             <bitfield name="ACME" mask="0x04" text="Analog Comparator Multiplexer Enable" icon=""/>
 137             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 138           </reg>
 139         </registers>
 140     </module>
 141     <module class="USI">
 142       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 143           <reg size="1" name="USIDR" offset="0x2F" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 144           <reg size="1" name="USISR" offset="0x2E" text="USI Status Register" icon="io_flag.bmp">
 145             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 146             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 147             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 148             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 149             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 150           </reg>
 151           <reg size="1" name="USICR" offset="0x2D" text="USI Control Register" icon="io_flag.bmp">
 152             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 153             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 154             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 155             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 156             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 157             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 158           </reg>
 159         </registers>
 160     </module>
 161     <module class="PORTA">
 162       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 163           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 164           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 165           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 166         </registers>
 167     </module>
 168     <module class="PORTB">
 169       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 170           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 171           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 172           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 173         </registers>
 174     </module>
 175     <module class="EEPROM">
 176       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 177           <reg size="1" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x7F"/>
 178           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 179           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 180             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 181             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 182             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 183             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 184           </reg>
 185         </registers>
 186     </module>
 187     <module class="WATCHDOG">
 188       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 189           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 190             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 191             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 192             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 193           </reg>
 194         </registers>
 195     </module>
 196     <module class="CPU">
 197       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.com">
 198           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 199             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 200             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 201             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 202             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 203             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 204             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 205             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 206             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 207           </reg>
 208           <reg size="1" name="SP" offset="0x5D" text="Stack Pointer" icon="io_sreg.bmp" mask="0xFF"/>
 209           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 210             <bitfield name="PUD" mask="0x40" text="Pull-up Disable" icon=""/>
 211             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 212             <bitfield name="SM" mask="0x18" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE"/>
 213             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 214           </reg>
 215           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status register" icon="io_cpu.bmp">
 216             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 217             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 218             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 219             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 220           </reg>
 221           <reg size="1" name="OSCCAL" offset="0x51" text="Status Register" icon="io_sreg.bmp" mask="0xFF"/>
 222         </registers>
 223     </module>
 224     <module class="TIMER_COUNTER_0">
 225       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 226           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 227             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 228           </reg>
 229           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 230             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 231           </reg>
 232           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 233             <bitfield name="PSR0" mask="0x08" text="Prescaler Reset Timer/Counter0" icon=""/>
 234             <bitfield name="CS0" mask="0x07" text="Clock Select0 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 235           </reg>
 236           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 237         </registers>
 238     </module>
 239     <module class="TIMER_COUNTER_1">
 240       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 241           <reg size="1" name="TCCR1A" offset="0x50" text="Timer/Counter Control Register A" icon="io_flag.bmp">
 242             <bitfield name="COM1A" mask="0xC0" text="Comparator A Output Mode Bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 243             <bitfield name="COM1B" mask="0x30" text="Comparator B Output Mode Bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 244             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare Match 1A" icon=""/>
 245             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare Match 1B" icon=""/>
 246             <bitfield name="PWM1A" mask="0x02" text="Pulse Width Modulator A Enable" icon=""/>
 247             <bitfield name="PWM1B" mask="0x01" text="Pulse Width Modulator B Enable" icon=""/>
 248           </reg>
 249           <reg size="1" name="TCCR1B" offset="0x4F" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 250             <bitfield name="CTC1" mask="0x80" text="Clear Timer/Counter on Compare Match" icon=""/>
 251             <bitfield name="PSR1" mask="0x40" text="Prescaler Reset Timer/Counter1" icon=""/>
 252             <bitfield name="CS1" mask="0x0F" text="Clock Select Bits" icon="" enum="CLK_SEL_4BIT"/>
 253           </reg>
 254           <reg size="1" name="TCNT1" offset="0x4E" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 255           <reg size="1" name="OCR1A" offset="0x4D" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 256           <reg size="1" name="OCR1B" offset="0x4C" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 257           <reg size="1" name="OCR1C" offset="0x4B" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 258           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 259             <bitfield name="OCIE1A" mask="0x40" text="Timer/Counter1 Output Compare Interrupt Enable" icon=""/>
 260             <bitfield name="OCIE1B" mask="0x20" text="Timer/Counter1 Output Compare Interrupt Enable" icon=""/>
 261             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 262           </reg>
 263           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 264             <bitfield name="OCF1A" mask="0x40" text="Timer/Counter1 Output Compare Flag 1A" icon=""/>
 265             <bitfield name="OCF1B" mask="0x20" text="Timer/Counter1 Output Compare Flag 1B" icon=""/>
 266             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 267           </reg>
 268           <reg size="1" name="PLLCSR" offset="0x49" text="PLL Control and Status Register" icon="io_sreg.bmp">
 269             <bitfield name="PCKE" mask="0x04" text="PCK Enable" icon=""/>
 270             <bitfield name="PLLE" mask="0x02" text="PLL Enable" icon=""/>
 271             <bitfield name="PLOCK" mask="0x01" text="PLL Lock Detector" icon=""/>
 272           </reg>
 273         </registers>
 274     </module>
 275     <module class="EXTERNAL_INTERRUPT">
 276       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 277           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 278             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
 279             <bitfield name="PCIE" mask="0x30" text="Pin Change Interrupt Enables" icon=""/>
 280           </reg>
 281           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 282             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
 283             <bitfield name="PCIF" mask="0x20" text="Pin Change Interrupt Flag" icon=""/>
 284           </reg>
 285         </registers>
 286     </module>
 287   </hardware>
 288 </device>