devices/attiny24

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <packages>
   5     <package name="MLF" pins="20">
   6       <pin id="1" name="[PA4:ADC4:USCK:SCL:T1:PCINT4]"/>
   7       <pin id="2" name="[PA3:ADC3:T0:PCINT3]"/>
   8       <pin id="3" name="[PA2:ADC2:AIN1:PCINT2]"/>
   9       <pin id="4" name="[PA1:ADC1:AIN0:PCINT1]"/>
  10       <pin id="5" name="[PA0:ADC0:AREF:PCINT0]"/>
  11       <pin id="6" name="NC"/>
  12       <pin id="7" name="NC"/>
  13       <pin id="8" name="[GND]"/>
  14       <pin id="9" name="[VCC]"/>
  15       <pin id="10" name="NC"/>
  16       <pin id="11" name="[PB0:PCINT8:XTAL1]"/>
  17       <pin id="12" name="[PB1:PCINT9:XTAL2]"/>
  18       <pin id="13" name="[PB3:PCINT11:'RESET:dW]"/>
  19       <pin id="14" name="[PB2:PCINT10:INT0:OC0A:CKOUT]"/>
  20       <pin id="15" name="[PA7:PCINT7:ICP1:OC0B:ADC7]"/>
  21       <pin id="16" name="[PA6:PCINT6:OC1A:DI:SDA:MOSI:ADC6]"/>
  22       <pin id="17" name="NC"/>
  23       <pin id="18" name="NC"/>
  24       <pin id="19" name="NC"/>
  25       <pin id="20" name="[PA5:ADC5:DO:MISO:OC1B:PCINT5]"/>
  26     </package>
  27   </packages>
  28   <interrupts num="17">
  29     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset</interrupt>
  30     <interrupt vector="2" address="$001" name="EXT_INT0">External Interrupt Request 0</interrupt>
  31     <interrupt vector="3" address="$002" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
  32     <interrupt vector="4" address="$003" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
  33     <interrupt vector="5" address="$004" name="WATCHDOG">Watchdog Time-out</interrupt>
  34     <interrupt vector="6" address="$005" name="TIM1 CAPT">Timer/Counter1 Capture Event</interrupt>
  35     <interrupt vector="7" address="$006" name="TIM1_COMPA">Timer/Counter1 Compare Match A</interrupt>
  36     <interrupt vector="8" address="$007" name="TIM1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  37     <interrupt vector="9" address="$008" name="TIM1_OVF">Timer/Counter1 Overflow</interrupt>
  38     <interrupt vector="10" address="$009" name="TIM0_COMPA">Timer/Counter0 Compare Match A</interrupt>
  39     <interrupt vector="11" address="$00A" name="TIM0_COMPB">Timer/Counter0 Compare Match B</interrupt>
  40     <interrupt vector="12" address="$00B" name="TIM0_OVF">Timer/Counter0 Overflow</interrupt>
  41     <interrupt vector="13" address="$00C" name="ANA_COMP">Analog Comparator</interrupt>
  42     <interrupt vector="14" address="$00D" name="ADC">ADC Conversion Complete</interrupt>
  43     <interrupt vector="15" address="$00E" name="EE_RDY">EEPROM Ready</interrupt>
  44     <interrupt vector="16" address="$00F" name="USI_STR">USI START</interrupt>
  45     <interrupt vector="17" address="$010" name="USI_OVF">USI Overflow</interrupt>
  46   </interrupts>
  47   <memory>
  48     <flash size="2048"/>
  49     <iospace start="$20" stop="$5F"/>
  50     <sram size="128"/>
  51     <eram size="0"/>
  52   </memory>
  53   <ioregisters>
  54     <ioreg name="PRR" address="$00"/>
  55     <ioreg name="DIDR0" address="$01"/>
  56     <ioreg name="ADCSRB" address="$03"/>
  57     <ioreg name="ADCL" address="$04"/>
  58     <ioreg name="ADCH" address="$05"/>
  59     <ioreg name="ADCSRA" address="$06"/>
  60     <ioreg name="ADMUX" address="$07"/>
  61     <ioreg name="ACSR" address="$08"/>
  62     <ioreg name="TIFR1" address="$0B"/>
  63     <ioreg name="TIMSK1" address="$0C"/>
  64     <ioreg name="USICR" address="$0D"/>
  65     <ioreg name="USISR" address="$0E"/>
  66     <ioreg name="USIDR" address="$0F"/>
  67     <ioreg name="USIBR" address="$10"/>
  68     <ioreg name="PCMSK0" address="$12"/>
  69     <ioreg name="GPIOR0" address="$13"/>
  70     <ioreg name="GPIOR1" address="$14"/>
  71     <ioreg name="GPIOR2" address="$15"/>
  72     <ioreg name="PINB" address="$16"/>
  73     <ioreg name="DDRB" address="$17"/>
  74     <ioreg name="PORTB" address="$18"/>
  75     <ioreg name="PINA" address="$19"/>
  76     <ioreg name="DDRA" address="$1A"/>
  77     <ioreg name="PORTA" address="$1B"/>
  78     <ioreg name="EECR" address="$1C"/>
  79     <ioreg name="EEDR" address="$1D"/>
  80     <ioreg name="EEARL" address="$1E"/>
  81     <ioreg name="EEARH" address="$1F"/>
  82     <ioreg name="PCMSK1" address="$20"/>
  83     <ioreg name="WDTCSR" address="$21"/>
  84     <ioreg name="TCCR1C" address="$22"/>
  85     <ioreg name="GTCCR" address="$23"/>
  86     <ioreg name="ICR1L" address="$24"/>
  87     <ioreg name="ICR1H" address="$25"/>
  88     <ioreg name="CLKPR" address="$26"/>
  89     <ioreg name="DWDR" address="$27"/>
  90     <ioreg name="OCR1BL" address="$28"/>
  91     <ioreg name="OCR1BH" address="$29"/>
  92     <ioreg name="OCR1AL" address="$2A"/>
  93     <ioreg name="OCR1AH" address="$2B"/>
  94     <ioreg name="TCNT1L" address="$2C"/>
  95     <ioreg name="TCNT1H" address="$2D"/>
  96     <ioreg name="TCCR1B" address="$2E"/>
  97     <ioreg name="TCCR1A" address="$2F"/>
  98     <ioreg name="TCCR0A" address="$30"/>
  99     <ioreg name="OSCCAL" address="$31"/>
 100     <ioreg name="TCNT0" address="$32"/>
 101     <ioreg name="TCCR0B" address="$33"/>
 102     <ioreg name="MCUSR" address="$34"/>
 103     <ioreg name="MCUCR" address="$35"/>
 104     <ioreg name="OCR0A" address="$36"/>
 105     <ioreg name="SPMCSR" address="$37"/>
 106     <ioreg name="TIFR0" address="$38"/>
 107     <ioreg name="TIMSK0" address="$39"/>
 108     <ioreg name="GIFR" address="$3A"/>
 109     <ioreg name="GIMSK" address="$3B"/>
 110     <ioreg name="OCR0B" address="$3C"/>
 111     <ioreg name="SPL" address="$3D"/>
 112     <ioreg name="SREG" address="$3F"/>
 113   </ioregisters>
 114   <hardware>
 115 <!--Everything after this needs editing!!!-->
 116     <module class="FUSE">
 117       <registers name="FUSE" memspace="FUSE">
 118           <reg size="1" name="EXTENDED" offset="0x02">
 119             <bitfield name="SELFPRGEN" mask="0x01" text="Self Programming enable" icon=""/>
 120           </reg>
 121           <reg size="1" name="HIGH" offset="0x01">
 122             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PB3 as i/o pin)" icon=""/>
 123             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 124             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 125             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
 126             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 127             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 128           </reg>
 129           <reg size="1" name="LOW" offset="0x00">
 130             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 131             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB2" icon=""/>
 132             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock source" icon="" enum="ENUM_SUT_CKSEL"/>
 133           </reg>
 134         </registers>
 135     </module>
 136     <module class="LOCKBIT">
 137       <registers name="LOCKBIT" memspace="LOCKBIT">
 138           <reg size="1" name="LOCKBIT" offset="0x00">
 139             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 140           </reg>
 141         </registers>
 142     </module>
 143     <module class="PORTA">
 144       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 145           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 146           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 147           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 148         </registers>
 149     </module>
 150     <module class="PORTB">
 151       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 152           <reg size="1" name="PORTB" offset="0x38" text="Data Register, Port B" icon="io_port.bmp" mask="0x0F"/>
 153           <reg size="1" name="DDRB" offset="0x37" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x0F"/>
 154           <reg size="1" name="PINB" offset="0x36" text="Input Pins, Port B" icon="io_port.bmp" mask="0x0F"/>
 155         </registers>
 156     </module>
 157     <module class="ANALOG_COMPARATOR">
 158       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 159           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_flag.bmp">
 160             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 161           </reg>
 162           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 163             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 164             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 165             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 166             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 167             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 168             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 169             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 170           </reg>
 171           <reg size="1" name="DIDR0" offset="0x21" text="" icon="">
 172             <bitfield name="ADC1D" mask="0x02" text="ADC 1 Digital input buffer disable" icon=""/>
 173             <bitfield name="ADC0D" mask="0x01" text="ADC 0 Digital input buffer disable" icon=""/>
 174           </reg>
 175         </registers>
 176     </module>
 177     <module class="AD_CONVERTER">
 178       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 179           <reg size="1" name="ADMUX" offset="0x27" text="ADC Multiplexer Selection Register" icon="io_analo.bmp" mask="0xFF"/>
 180           <reg size="1" name="ADCSRA" offset="0x26" text="ADC Control and Status Register A" icon="io_flag.bmp">
 181             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 182             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 183             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 184             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 185             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 186             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 187           </reg>
 188           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 189           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_analo.bmp">
 190             <bitfield name="BIN" mask="0x80" text="Bipolar Input Mode" icon=""/>
 191             <bitfield name="ADLAR" mask="0x10" text="ADC Left Adjust Result" icon=""/>
 192             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Source bits" icon="" enum="ANALIG_ADC_AUTO_TRIGGER"/>
 193           </reg>
 194           <reg size="1" name="DIDR0" offset="0x21" text="Digital Input Disable Register 0" icon="io_analo.bmp" mask="0xFF"/>
 195         </registers>
 196     </module>
 197     <module class="USI">
 198       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 199           <reg size="1" name="USIBR" offset="0x30" text="USI Buffer Register" icon="io_com.bmp" mask="0xFF"/>
 200           <reg size="1" name="USIDR" offset="0x2F" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 201           <reg size="1" name="USISR" offset="0x2E" text="USI Status Register" icon="io_flag.bmp">
 202             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 203             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 204             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 205             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 206             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 207           </reg>
 208           <reg size="1" name="USICR" offset="0x2D" text="USI Control Register" icon="io_flag.bmp">
 209             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 210             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 211             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 212             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 213             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 214             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 215           </reg>
 216         </registers>
 217     </module>
 218     <module class="EXTERNAL_INTERRUPT">
 219       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 220           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 221             <bitfield name="ISC01" mask="0x02" text="Interrupt Sense Control 0 Bit 1" icon=""/>
 222             <bitfield name="ISC00" mask="0x01" text="Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 223           </reg>
 224           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 225             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
 226             <bitfield name="PCIE" mask="0x30" text="Pin Change Interrupt Enables" icon=""/>
 227           </reg>
 228           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 229             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
 230             <bitfield name="PCIF" mask="0x30" text="Pin Change Interrupt Flags" icon=""/>
 231           </reg>
 232           <reg size="1" name="PCMSK1" offset="0x40" text="Pin Change Enable Mask 1" icon="io_flag.bmp" mask="0x0F"/>
 233           <reg size="1" name="PCMSK0" offset="0x32" text="Pin Change Enable Mask 0" icon="io_flag.bmp" mask="0xFF"/>
 234         </registers>
 235     </module>
 236     <module class="EEPROM">
 237       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 238           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 239           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 240           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 241             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 242             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 243             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 244             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 245             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 246           </reg>
 247         </registers>
 248     </module>
 249     <module class="WATCHDOG">
 250       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 251           <reg size="1" name="WDTCSR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 252             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 253             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 254             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 255             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 256             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 257           </reg>
 258         </registers>
 259     </module>
 260     <module class="TIMER_COUNTER_0">
 261       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 262           <reg size="1" name="TIMSK0" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 263             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 264             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 265             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 266           </reg>
 267           <reg size="1" name="TIFR0" offset="0x58" text="Timer/Counter0 Interrupt Flag Register" icon="io_flag.bmp">
 268             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag B" icon=""/>
 269             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag A" icon=""/>
 270             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 271           </reg>
 272           <reg size="1" name="TCCR0A" offset="0x50" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 273             <bitfield name="COM0A" mask="0xC0" text="Compare Match Output A Mode bits" icon=""/>
 274             <bitfield name="COM0B" mask="0x30" text="Compare Match Output B Mode bits" icon=""/>
 275             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode bits" icon=""/>
 276           </reg>
 277           <reg size="1" name="TCCR0B" offset="0x53" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 278             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 279             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 280             <bitfield name="WGM02" mask="0x08" text="Waveform Generation Mode bit 2" icon=""/>
 281             <bitfield name="CS0" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 282           </reg>
 283           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 284           <reg size="1" name="OCR0A" offset="0x56" text="Timer/Counter0 Output Compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 285           <reg size="1" name="OCR0B" offset="0x5C" text="Timer/Counter0 Output Compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 286           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 287             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 288             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/CounterN" icon=""/>
 289           </reg>
 290         </registers>
 291     </module>
 292     <module class="TIMER_COUNTER_1">
 293       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 294           <reg size="1" name="TIMSK1" offset="0x2C" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 295             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 296             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 297             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 298             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 299           </reg>
 300           <reg size="1" name="TIFR1" offset="0x2B" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 301             <bitfield name="ICF1" mask="0x20" text="Timer/Counter1 Input Capture Flag" icon=""/>
 302             <bitfield name="OCF1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Flag" icon=""/>
 303             <bitfield name="OCF1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Flag" icon=""/>
 304             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 305           </reg>
 306           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 307             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 308             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 309             <bitfield name="WGM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon=""/>
 310           </reg>
 311           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 312             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 313             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 314             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode Bits" icon="" lsb="2"/>
 315             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 316           </reg>
 317           <reg size="1" name="TCCR1C" offset="0x42" text="Timer/Counter1 Control Register C" icon="io_flag.bmp">
 318             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare for Channel A" icon=""/>
 319             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare for Channel B" icon=""/>
 320           </reg>
 321           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 322           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Output Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 323           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 324           <reg size="2" name="ICR1" offset="0x44" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 325         </registers>
 326     </module>
 327     <module class="CPU">
 328       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 329           <reg size="1" name="PRR" offset="0x20" text="Power Reduction Register" icon="io_cpu.bmp">
 330             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 331             <bitfield name="PRTIM0" mask="0x04" text="Power Reduction Timer/Counter0" icon=""/>
 332             <bitfield name="PRUSI" mask="0x02" text="Power Reduction USI" icon=""/>
 333             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 334           </reg>
 335           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 336           <reg size="1" name="CLKPR" offset="0x46" text="Clock Prescale Register" icon="io_flag.bmp">
 337             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 338             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 339           </reg>
 340           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 341             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 342             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 343             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 344             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 345             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 346             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 347             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 348             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 349           </reg>
 350           <reg size="1" name="SPL" offset="0x5D" text="Stack Pointer Low" icon="io_sph.bmp" mask="0xFF"/>
 351           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 352             <bitfield name="PUD" mask="0x40" text="" icon=""/>
 353             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 354             <bitfield name="SM" mask="0x18" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE"/>
 355           </reg>
 356           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 357             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 358             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 359             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 360             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 361           </reg>
 362           <reg size="1" name="GPIOR2" offset="0x35" text="General Purpose I/O Register 2" icon="io_flag.bmp" mask="0xFF"/>
 363           <reg size="1" name="GPIOR1" offset="0x34" text="General Purpose I/O Register 1" icon="io_flag.bmp" mask="0xFF"/>
 364           <reg size="1" name="GPIOR0" offset="0x33" text="General Purpose I/O Register 0" icon="io_flag.bmp" mask="0xFF"/>
 365         </registers>
 366     </module>
 367     <module class="BOOT_LOAD">
 368       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 369           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 370             <bitfield name="CTPB" mask="0x10" text="Clear temporary page buffer" icon=""/>
 371             <bitfield name="RFLB" mask="0x08" text="Read fuse and lock bits" icon=""/>
 372             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 373             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 374             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 375           </reg>
 376         </registers>
 377     </module>
 378   </hardware>
 379 </device>