devices/attiny15

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="9">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$002" name="I/O_PINS">External Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$003" name="TIMER1_COMP">Timer/Counter1 Compare Match</interrupt>
   9     <interrupt vector="5" address="$004" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  10     <interrupt vector="6" address="$005" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  11     <interrupt vector="7" address="$006" name="EE_RDY">EEPROM Ready</interrupt>
  12     <interrupt vector="8" address="$007" name="ANA_COMP">Analog Comparator</interrupt>
  13     <interrupt vector="9" address="$008" name="ADC">ADC Conversion Ready</interrupt>
  14   </interrupts>
  15   <memory>
  16     <flash size="1024"/>
  17     <iospace start="$20" stop="$5F"/>
  18     <sram size="0"/>
  19     <eram size="0"/>
  20   </memory>
  21   <ioregisters>
  22     <ioreg name="SREG" address="$3F"/>
  23     <ioreg name="GIMSK" address="$3B"/>
  24     <ioreg name="GIFR" address="$3A"/>
  25     <ioreg name="TIMSK" address="$39"/>
  26     <ioreg name="TIFR" address="$38"/>
  27     <ioreg name="MCUCR" address="$35"/>
  28     <ioreg name="MCUSR" address="$34"/>
  29     <ioreg name="TCCR0" address="$33"/>
  30     <ioreg name="TCNT0" address="$32"/>
  31     <ioreg name="OSCCAL" address="$31"/>
  32     <ioreg name="TCCR1" address="$30"/>
  33     <ioreg name="TCNT1" address="$2F"/>
  34     <ioreg name="OCR1A" address="$2E"/>
  35     <ioreg name="OCR1B" address="$2D"/>
  36     <ioreg name="SFIOR" address="$2C"/>
  37     <ioreg name="WDTCR" address="$21"/>
  38     <ioreg name="EEAR" address="$1E"/>
  39     <ioreg name="EEDR" address="$1D"/>
  40     <ioreg name="EECR" address="$1C"/>
  41     <ioreg name="PORTB" address="$18"/>
  42     <ioreg name="DDRB" address="$17"/>
  43     <ioreg name="PINB" address="$16"/>
  44     <ioreg name="ACSR" address="$08"/>
  45     <ioreg name="ADMUX" address="$07"/>
  46     <ioreg name="ADCSR" address="$06"/>
  47     <ioreg name="ADCH" address="$05"/>
  48     <ioreg name="ADCL" address="$04"/>
  49   </ioregisters>
  50   <packages/>
  51   <hardware>
  52 <!--Everything after this needs editing!!!-->
  53     <module class="FUSE">
  54       <registers name="FUSE" memspace="FUSE">
  55           <reg size="1" name="LOW" offset="0x00">
  56             <bitfield name="BODLEVEL" mask="0x80" text="Brown-out Detection Level" icon="" enum="ENUM1"/>
  57             <bitfield name="BODEN" mask="0x40" text="Brown-out Detection Enabled" icon=""/>
  58             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
  59             <bitfield name="RSTDISBL" mask="0x10" text="External reset function of PB5 disabled" icon=""/>
  60             <bitfield name="CKSEL" mask="0x03" text="Clock Select" icon="" enum="ENUM2"/>
  61           </reg>
  62         </registers>
  63     </module>
  64     <module class="LOCKBIT">
  65       <registers name="LOCKBIT" memspace="LOCKBIT">
  66           <reg size="1" name="LOCKBIT" offset="0x00">
  67             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
  68           </reg>
  69         </registers>
  70     </module>
  71     <module class="AD_CONVERTER">
  72       <registers name="AD_CONVERTER" memspace="IOMEM" text="" icon="io_analo.bmp">
  73           <reg size="1" name="ADMUX" offset="0x07" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
  74             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF"/>
  75             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
  76             <bitfield name="MUX" mask="0x07" text="Analog Channel and Gain Selection Bits" icon=""/>
  77           </reg>
  78           <reg size="1" name="ADCSR" offset="0x06" text="The ADC Control and Status register" icon="io_flag.bmp">
  79             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
  80             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
  81             <bitfield name="ADFR" mask="0x20" text="ADC  Free Running Select" icon=""/>
  82             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
  83             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
  84             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
  85           </reg>
  86           <reg size="2" name="ADC" offset="0x04" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
  87         </registers>
  88     </module>
  89     <module class="ANALOG_COMPARATOR">
  90       <registers name="ANALOG_COMPARATOR" memspace="IOMEM" text="" icon="io_analo.bmp">
  91           <reg size="1" name="ACSR" offset="0x08" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
  92             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
  93             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
  94             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
  95             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
  96             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
  97             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
  98           </reg>
  99         </registers>
 100     </module>
 101     <module class="EEPROM">
 102       <registers name="EEPROM" memspace="IOMEM" text="" icon="io_cpu.bmp">
 103           <reg size="1" name="EEAR" offset="0x1E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x3F"/>
 104           <reg size="1" name="EEDR" offset="0x1D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 105           <reg size="1" name="EECR" offset="0x1C" text="EEPROM Control Register" icon="io_flag.bmp">
 106             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 107             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 108             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 109             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 110           </reg>
 111         </registers>
 112     </module>
 113     <module class="PORTB">
 114       <registers name="PORTB" memspace="IOMEM" text="" icon="io_port.bmp">
 115           <reg size="1" name="PORTB" offset="0x18" text="Data Register, Port B" icon="io_port.bmp" mask="0x1F"/>
 116           <reg size="1" name="DDRB" offset="0x17" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x3F"/>
 117           <reg size="1" name="PINB" offset="0x16" text="Input Pins, Port B" icon="io_port.bmp" mask="0x3F"/>
 118         </registers>
 119     </module>
 120     <module class="TIMER_COUNTER_0">
 121       <registers name="TIMER_COUNTER_0" memspace="IOMEM" text="" icon="io_timer.bmp">
 122           <reg size="1" name="TIMSK" offset="0x39" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 123             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 124           </reg>
 125           <reg size="1" name="TIFR" offset="0x38" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 126             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 127           </reg>
 128           <reg size="1" name="TCCR0" offset="0x33" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 129             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon="" enum="CLK_SEL_3BIT_EXT"/>
 130             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 131             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
 132           </reg>
 133           <reg size="1" name="TCNT0" offset="0x32" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 134         </registers>
 135     </module>
 136     <module class="WATCHDOG">
 137       <registers name="WATCHDOG" memspace="IOMEM" text="" icon="io_watch.bmp">
 138           <reg size="1" name="WDTCR" offset="0x21" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 139             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 140             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 141             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 142           </reg>
 143         </registers>
 144     </module>
 145     <module class="CPU">
 146       <registers name="CPU" memspace="IOMEM" text="" icon="io_cpu.com">
 147           <reg size="1" name="SREG" offset="0x3F" text="Status Register" icon="io_sreg.bmp">
 148             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 149             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 150             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 151             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 152             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 153             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 154             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 155             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 156           </reg>
 157           <reg size="1" name="MCUCR" offset="0x35" text="MCU Control Register" icon="io_cpu.bmp">
 158             <bitfield name="PUD" mask="0x40" text="Pull-up Disable" icon=""/>
 159             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 160             <bitfield name="SM" mask="0x18" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE2"/>
 161             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 162           </reg>
 163           <reg size="1" name="MCUSR" offset="0x34" text="MCU Status register" icon="io_cpu.bmp">
 164             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 165             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 166             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 167             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 168           </reg>
 169           <reg size="1" name="OSCCAL" offset="0x31" text="Status Register" icon="io_sreg.bmp" mask="0xFF"/>
 170         </registers>
 171     </module>
 172     <module class="EXTERNAL_INTERRUPT">
 173       <registers name="EXTERNAL_INTERRUPT" memspace="IOMEM" text="" icon="io_ext.bmp">
 174           <reg size="1" name="GIMSK" offset="0x3B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 175             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
 176             <bitfield name="PCIE" mask="0x20" text="Pin Change Interrupt Enable" icon=""/>
 177           </reg>
 178           <reg size="1" name="GIFR" offset="0x3A" text="General Interrupt Flag register" icon="io_flag.bmp">
 179             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
 180             <bitfield name="PCIF" mask="0x20" text="Pin Change Interrupt Flag" icon=""/>
 181           </reg>
 182         </registers>
 183     </module>
 184     <module class="TIMER_COUNTER_1">
 185       <registers name="TIMER_COUNTER_1" memspace="IOMEM" text="" icon="io_timer.bmp">
 186           <reg size="1" name="TCCR1" offset="0x30" text="Timer/Counter Control Register" icon="io_flag.bmp">
 187             <bitfield name="CTC1" mask="0x80" text="Clear Timer/Counter on Compare Match" icon=""/>
 188             <bitfield name="PWM1" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 189             <bitfield name="COM1A" mask="0x30" text="Compare Output Mode, Bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 190             <bitfield name="CS1" mask="0x0F" text="Clock Select Bits" icon="" enum="CLK_SEL_4BIT_FAST"/>
 191           </reg>
 192           <reg size="1" name="TCNT1" offset="0x2F" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 193           <reg size="1" name="OCR1A" offset="0x2E" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 194           <reg size="1" name="OCR1B" offset="0x2D" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 195           <reg size="1" name="TIMSK" offset="0x39" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 196             <bitfield name="OCIE1A" mask="0x40" text="OCIE1A: Timer/Counter1 Output Compare Interrupt Enable" icon=""/>
 197             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 198           </reg>
 199           <reg size="1" name="TIFR" offset="0x38" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 200             <bitfield name="OCF1A" mask="0x40" text="Timer/Counter1 Output Compare Flag 1A" icon=""/>
 201             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 202           </reg>
 203           <reg size="1" name="SFIOR" offset="0x2C" text="Special Function IO Register" icon="io_flag.bmp">
 204             <bitfield name="FOC1A" mask="0x04" text="Force Output Compare 1A" icon=""/>
 205             <bitfield name="PSR1" mask="0x02" text="Prescaler Reset Timer/Counter1" icon=""/>
 206             <bitfield name="PSR0" mask="0x01" text="Prescaler Reset Timer/Counter0" icon=""/>
 207           </reg>
 208         </registers>
 209     </module>
 210   </hardware>
 211 </device>