devices/atmega8

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="8192"/>
   6     <iospace start="$20" stop="$5F"/>
   7     <sram size="1024"/>
   8     <eram size="0"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="TWBR" address="0x00"/>
  12     <ioreg name="TWSR" address="0x01"/>
  13     <ioreg name="TWAR" address="0x02"/>
  14     <ioreg name="TWDR" address="0x03"/>
  15     <ioreg name="ADCL" address="0x04"/>
  16     <ioreg name="ADCH" address="0x05"/>
  17     <ioreg name="ADCSRA" address="0x06"/>
  18     <ioreg name="ADMUX" address="0x07"/>
  19     <ioreg name="ACSR" address="0x08"/>
  20     <ioreg name="UBRRL" address="0x09"/>
  21     <ioreg name="UCSRB" address="0x0A"/>
  22     <ioreg name="UCSRA" address="0x0B"/>
  23     <ioreg name="UDR" address="0x0C"/>
  24     <ioreg name="SPCR" address="0x0D"/>
  25     <ioreg name="SPSR" address="0x0E"/>
  26     <ioreg name="SPDR" address="0x0F"/>
  27     <ioreg name="PIND" address="0x10"/>
  28     <ioreg name="DDRD" address="0x11"/>
  29     <ioreg name="PORTD" address="0x12"/>
  30     <ioreg name="PINC" address="0x13"/>
  31     <ioreg name="DDRC" address="0x14"/>
  32     <ioreg name="PORTC" address="0x15"/>
  33     <ioreg name="PINB" address="0x16"/>
  34     <ioreg name="DDRB" address="0x17"/>
  35     <ioreg name="PORTB" address="0x18"/>
  36     <ioreg name="EECR" address="0x1C"/>
  37     <ioreg name="EEDR" address="0x1D"/>
  38     <ioreg name="EEARL" address="0x1E"/>
  39     <ioreg name="EEARH" address="0x1F"/>
  40     <ioreg name="UBRRH/UCSRC" address="0x20"/>
  41     <ioreg name="WDTCR" address="0x21"/>
  42     <ioreg name="ASSR" address="0x22"/>
  43     <ioreg name="OCR2" address="0x23"/>
  44     <ioreg name="TCNT2" address="0x24"/>
  45     <ioreg name="TCCR2" address="0x25"/>
  46     <ioreg name="ICR1L" address="0x26"/>
  47     <ioreg name="ICR1H" address="0x27"/>
  48     <ioreg name="OCR1BL" address="0x28"/>
  49     <ioreg name="OCR1BH" address="0x29"/>
  50     <ioreg name="OCR1AL" address="0x2A"/>
  51     <ioreg name="OCR1AH" address="0x2B"/>
  52     <ioreg name="TCNT1L" address="0x2C"/>
  53     <ioreg name="TCNT1H" address="0x2D"/>
  54     <ioreg name="TCCR1B" address="0x2E"/>
  55     <ioreg name="TCCR1A" address="0x2F"/>
  56     <ioreg name="SFIOR" address="0x30"/>
  57     <ioreg name="OSCCAL" address="0x31"/>
  58     <ioreg name="TCNT0" address="0x32"/>
  59     <ioreg name="TCCR0" address="0x33"/>
  60     <ioreg name="MCUCSR" address="0x34"/>
  61     <ioreg name="MCUCR" address="0x35"/>
  62     <ioreg name="TWCR" address="0x36"/>
  63     <ioreg name="SPMCR" address="0x37"/>
  64     <ioreg name="TIFR" address="0x38"/>
  65     <ioreg name="TIMSK" address="0x39"/>
  66     <ioreg name="GIFR" address="0x3A"/>
  67     <ioreg name="GICR" address="0x3B"/>
  68     <ioreg name="SPL" address="0x3D"/>
  69     <ioreg name="SPH" address="0x3E"/>
  70     <ioreg name="SREG" address="0x3F"/>
  71   </ioregisters>
  72
  73   <interrupts num="19">
  74     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset</interrupt>
  75     <interrupt vector="2" address="$001" name="INT0">External Interrupt Request 0</interrupt>
  76     <interrupt vector="3" address="$002" name="INT1">External Interrupt Request 1</interrupt>
  77     <interrupt vector="4" address="$003" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
  78     <interrupt vector="5" address="$004" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  79     <interrupt vector="6" address="$005" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  80     <interrupt vector="7" address="$006" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  81     <interrupt vector="8" address="$007" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
  82     <interrupt vector="9" address="$008" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  83     <interrupt vector="10" address="$009" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  84     <interrupt vector="11" address="$00A" name="SPI, STC">Serial Transfer Complete</interrupt>
  85     <interrupt vector="12" address="$00B" name="USART, RXC">USART, Rx Complete</interrupt>
  86     <interrupt vector="13" address="$00C" name="USART, UDRE">USART Data Register Empty</interrupt>
  87     <interrupt vector="14" address="$00D" name="USART, TXC">USART, Tx Complete</interrupt>
  88     <interrupt vector="15" address="$00E" name="ADC">ADC Conversion Complete</interrupt>
  89     <interrupt vector="16" address="$00F" name="EE_RDY">EEPROM Ready</interrupt>
  90     <interrupt vector="17" address="$010" name="ANA_COMP">Analog Comparator</interrupt>
  91     <interrupt vector="18" address="$011" name="TWI">2-wire Serial Interface</interrupt>
  92     <interrupt vector="19" address="$012" name="SPM_RDY">Store Program Memory Ready</interrupt>
  93   </interrupts>
  94
  95   <packages>
  96     <package name="TQFP" pins="32">
  97       <pin id="1" name="[PD3:IN1]">INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.</pin>
  98       <pin id="2" name="[PD4:XCK:T0]">XCK, USART external clock. T0,Timer/Counter0 counter source.</pin>
  99       <pin id="3" name="[GND]"/>
 100       <pin id="4" name="[VCC]"/>
 101       <pin id="5" name="[GND]"/>
 102       <pin id="6" name="[VCC]"/>
 103       <pin id="7" name="[PB6:XTAL1:TOSC1]">XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all read</pin>
 104       <pin id="8" name="[PB7:XTAL2:TOSC2]">XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read </pin>
 105       <pin id="9" name="[PD5:T1]">T1,Timer/Counter1 counter source.</pin>
 106       <pin id="10" name="[PD6:AIN0]">AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
 107       <pin id="11" name="[PD7:AIN1]">AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
 108       <pin id="12" name="[PB0:ICP]">ICP -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1.</pin>
 109       <pin id="13" name="[PB1:OC1A]">OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 110       <pin id="14" name="[PB2:'SS:OC1B]">SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer func</pin>
 111       <pin id="15" name="[PB3:MOSI:OC2]">MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.</pin>
 112       <pin id="16" name="[PB4:MISO]">MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.</pin>
 113       <pin id="17" name="[PB5:SCK]">SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.</pin>
 114       <pin id="18" name="[AVCC]"/>
 115       <pin id="19" name="[ADC6]"/>
 116       <pin id="20" name="[AREF]"/>
 117       <pin id="21" name="[AGND]"/>
 118       <pin id="22" name="[ADC7]"/>
 119       <pin id="23" name="[PC0:ADC0]">PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.</pin>
 120       <pin id="24" name="[PC1:ADC1]">PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.</pin>
 121       <pin id="25" name="[PC2:ADC2]">PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.</pin>
 122       <pin id="26" name="[PC3:ADC3]">PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.</pin>
 123       <pin id="27" name="[PC4:ADC4:SDA]">SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.</pin>
 124       <pin id="28" name="[PC5:ADC5:SCL]">SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.</pin>
 125       <pin id="29" name="[PC6:'RESET]">RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.</pin>
 126       <pin id="30" name="[PD0:RXD]">RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.</pin>
 127       <pin id="31" name="[PD1:TXD]">TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.</pin>
 128       <pin id="32" name="[PD2:INT0]">INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.</pin>
 129     </package>
 130   </packages>
 131
 132   <hardware>
 133         <module class="eeprom">
 134                 <params>
 135                         <param name="size" value="512"/>
 136                         <param name="rdyVec" value="16"/>
 137                 </params>
 138                 <registers>
 139                         <reg name="eearl" bind="EEARL"/>
 140                         <reg name="eearh" bind="EEARH"/>
 141                         <reg name="eecr" bind="EECR"/>
 142                         <reg name="eedr" bind="EEDR"/>
 143                 </registers>
 144         </module>
 145
 146         <module class="hwport">
 147                 <params>
 148                         <param name="name" value="portb"/>
 149                 </params>
 150                 <registers>
 151                         <reg name="port" bind="PORTB"/>
 152                         <reg name="pin" bind="PINB"/>
 153                         <reg name="ddr" bind="DDRB"/>
 154                 </registers>
 155         </module>
 156
 157         <module class="hwport">
 158                 <params>
 159                         <param name="name" value="portc"/>
 160                 </params>
 161                 <registers>
 162                         <reg name="port" bind="PORTC"/>
 163                         <reg name="pin" bind="PINC"/>
 164                         <reg name="ddr" bind="DDRC"/>
 165                 </registers>
 166         </module>
 167
 168         <module class="hwport">
 169                 <params>
 170                         <param name="name" value="portd"/>
 171                 </params>
 172                 <registers>
 173                         <reg name="port" bind="PORTD"/>
 174                         <reg name="pin" bind="PIND"/>
 175                         <reg name="ddr" bind="DDRD"/>
 176                 </registers>
 177         </module>
 178
 179         <module class="timerirq">
 180                 <params>
 181                         <param name="bit0Vec" value="10"/>
 182                         <param name="bit1Vec" value="0"/>
 183                         <param name="bit2Vec" value="9"/>
 184                         <param name="bit3Vec" value="8"/>
 185                         <param name="bit4Vec" value="7"/>
 186                         <param name="bit5Vec" value="6"/>
 187                         <param name="bit6Vec" value="5"/>
 188                         <param name="bit7Vec" value="4"/>
 189                 </params>
 190                 <registers>
 191                         <reg name="tifr" bind="TIFR"/>
 192                         <reg name="timsk" bind="TIMSK"/>
 193                 </registers>
 194         </module>
 195
 196         <module class="timer8">
 197                 <params>
 198                         <param name="name" value="Timer/Counter0"/>
 199                         <param name="tov" value="0x02"/>
 200                         <param name="ocf" value="0x04"/>
 201                 </params>
 202                 <registers>
 203                         <reg name="tccr" bind="TCCR0"/>
 204                         <reg name="tcnt" bind="TCNT0"/>
 205                         <reg name="tifr" bind="TIFR"/>
 206                 </registers>
 207         </module>
 208
 209         <module class="usart">
 210                 <params>
 211                         <param name="name" value="usart"/>
 212                         <param name="rxVec" value="12"/>
 213                         <param name="txVec" value="14"/>
 214                         <param name="udreVec" value="13"/>
 215                 </params>
 216                 <registers>
 217                         <reg name="udr" bind="UDR"/>
 218                         <reg name="ucsra" bind="UCSRA"/>
 219                         <reg name="ucsrb" bind="UCSRB"/>
 220                         <reg name="ubrrh" bind="UBRRH/UCSRC"/>
 221                         <reg name="ubrrl" bind="UBRRL"/>
 222                 </registers>
 223         </module>
 224
 225         <module class="spi">
 226                 <params>
 227                         <param name="stcVec" value="11"/>
 228                 </params>
 229                 <registers>
 230                         <reg name="spsr" bind="SPSR"/>
 231                         <reg name="spcr" bind="SPCR"/>
 232                         <reg name="spdr" bind="SPDR"/>
 233                 </registers>
 234         </module>
 235
 236         <module class="adc">
 237                 <params>
 238                         <param name="ccVec" value="15"/>
 239                 </params>
 240                 <registers>
 241                         <reg name="admux" bind="ADMUX"/>
 242                         <reg name="adcsr" bind="ADCSRA"/>
 243                         <reg name="adch" bind="ADCH"/>
 244                         <reg name="adcl" bind="ADCL"/>
 245                 </registers>
 246         </module>
 247
 248 <!--
 249     <module class="ANALOG_COMPARATOR">
 250       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 251           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_flag.bmp">
 252             <bitfield name="ACME" mask="0x08" text="Analog Comparator Multiplexer Enable" icon=""/>
 253           </reg>
 254           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 255             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 256             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 257             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 258             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 259             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 260             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 261             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 262           </reg>
 263         </registers>
 264     </module>
 265    <module class="EXTERNAL_INTERRUPT">
 266       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 267           <reg size="1" name="GICR" offset="0x5B" text="General Interrupt Control Register" icon="io_flag.bmp">
 268             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 269             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 270             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 271           </reg>
 272           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_flag.bmp">
 273             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 274           </reg>
 275           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 276             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 277             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 278           </reg>
 279         </registers>
 280     </module>
 281     <module class="TIMER_COUNTER_0">
 282       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 283           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 284             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 285           </reg>
 286           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 287             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 288           </reg>
 289           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 290             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon=""/>
 291             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 292             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon="" enum="CLK_SEL_3BIT_EXT"/>
 293           </reg>
 294           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 295         </registers>
 296     </module>
 297     <module class="TIMER_COUNTER_1">
 298       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 299           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 300             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 301             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 302             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 303             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 304           </reg>
 305           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 306             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 307             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 308             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 309             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 310           </reg>
 311           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 312             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 313             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 314             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
 315             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
 316             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 317           </reg>
 318           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 319             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 320             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 321             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 322             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 323           </reg>
 324           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 325           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 326           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 327           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 328         </registers>
 329     </module>
 330     <module class="TIMER_COUNTER_2">
 331       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 332           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 333             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 334             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 335           </reg>
 336           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 337             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 338             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 339           </reg>
 340           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 341             <bitfield name="FOC2" mask="0x80" text="Force Output Compare" icon=""/>
 342             <bitfield name="WGM20" mask="0x40" text="Waveform Genration Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 343             <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon=""/>
 344             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 345             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 346           </reg>
 347           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 348           <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 349           <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
 350             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer/counter2" icon=""/>
 351             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 352             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 353             <bitfield name="TCR2UB" mask="0x01" text="Timer/counter Control Register2 Update Busy" icon=""/>
 354           </reg>
 355           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 356             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 357           </reg>
 358         </registers>
 359     </module>
 360    <module class="TWI">
 361       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 362           <reg size="1" name="TWBR" offset="0x20" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 363           <reg size="1" name="TWCR" offset="0x56" text="TWI Control Register" icon="io_flag.bmp">
 364             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 365             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 366             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 367             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 368             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 369             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 370             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 371           </reg>
 372           <reg size="1" name="TWSR" offset="0x21" text="TWI Status Register" icon="io_flag.bmp">
 373             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 374             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 375           </reg>
 376           <reg size="1" name="TWDR" offset="0x23" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 377           <reg size="1" name="TWAR" offset="0x22" text="TWI (Slave) Address register" icon="io_com.bmp">
 378             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 379             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 380           </reg>
 381         </registers>
 382     </module>
 383     <module class="WATCHDOG">
 384       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 385           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 386             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 387             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 388             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 389           </reg>
 390         </registers>
 391     </module>
 392     <module class="CPU">
 393       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 394           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 395             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 396             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 397             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 398             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 399             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 400             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 401             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 402             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 403           </reg>
 404           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x07FF"/>
 405           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 406             <bitfield name="SE" mask="0x80" text="Sleep Enable" icon=""/>
 407             <bitfield name="SM" mask="0x70" text="Sleep Mode Select" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 408             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 409             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 410           </reg>
 411           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 412             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 413             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 414             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 415             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 416           </reg>
 417           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 418           <reg size="1" name="SPMCR" offset="0x57" text="Store Program Memory Control Register" icon="io_cpu.bmp">
 419             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 420             <bitfield name="RWWSB" mask="0x40" text="Read-While-Write Section Busy" icon=""/>
 421             <bitfield name="RWWSRE" mask="0x10" text="Read-While-Write Section Read Enable" icon=""/>
 422             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 423             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 424             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 425             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 426           </reg>
 427           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 428             <bitfield name="ADHSM" mask="0x10" text="ADC High Speed Mode" icon=""/>
 429             <bitfield name="PUD" mask="0x04" text="Pull-up Disable" icon=""/>
 430             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 431           </reg>
 432         </registers>
 433     </module>
 434
 435         -->
 436   </hardware>
 437 </device>