devices/atmega6490

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="65536"/>
   6     <iospace start="$20" stop="$FF"/>
   7     <sram size="4096"/>
   8     <eram size="0"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="PINA" address="$00"/>
  12     <ioreg name="DDRA" address="$01"/>
  13     <ioreg name="PORTA" address="$02"/>
  14     <ioreg name="PINB" address="$03"/>
  15     <ioreg name="DDRB" address="$04"/>
  16     <ioreg name="PORTB" address="$05"/>
  17     <ioreg name="PINC" address="$06"/>
  18     <ioreg name="DDRC" address="$07"/>
  19     <ioreg name="PORTC" address="$08"/>
  20     <ioreg name="PIND" address="$09"/>
  21     <ioreg name="DDRD" address="$0A"/>
  22     <ioreg name="PORTD" address="$0B"/>
  23     <ioreg name="PINE" address="$0C"/>
  24     <ioreg name="DDRE" address="$0D"/>
  25     <ioreg name="PORTE" address="$0E"/>
  26     <ioreg name="PINF" address="$0F"/>
  27     <ioreg name="DDRF" address="$10"/>
  28     <ioreg name="PORTF" address="$11"/>
  29     <ioreg name="PING" address="$12"/>
  30     <ioreg name="DDRG" address="$13"/>
  31     <ioreg name="PORTG" address="$14"/>
  32     <ioreg name="TIFR0" address="$15"/>
  33     <ioreg name="TIFR1" address="$16"/>
  34     <ioreg name="TIFR2" address="$17"/>
  35     <ioreg name="EIFR" address="$1C"/>
  36     <ioreg name="EIMSK" address="$1D"/>
  37     <ioreg name="GPIOR0" address="$1E"/>
  38     <ioreg name="EECR" address="$1F"/>
  39     <ioreg name="EEDR" address="$20"/>
  40     <ioreg name="EEARL" address="$21"/>
  41     <ioreg name="EEARH" address="$22"/>
  42     <ioreg name="GTCCR" address="$23"/>
  43     <ioreg name="TCCR0A" address="$24"/>
  44     <ioreg name="TCNT0" address="$26"/>
  45     <ioreg name="OCR0A" address="$27"/>
  46     <ioreg name="GPIOR1" address="$2A"/>
  47     <ioreg name="GPIOR2" address="$2B"/>
  48     <ioreg name="SPCR" address="$2C"/>
  49     <ioreg name="SPSR" address="$2D"/>
  50     <ioreg name="SPDR" address="$2E"/>
  51     <ioreg name="ACSR" address="$30"/>
  52     <ioreg name="OCDR" address="$31"/>
  53     <ioreg name="SMCR" address="$33"/>
  54     <ioreg name="MCUSR" address="$34"/>
  55     <ioreg name="MCUCR" address="$35"/>
  56     <ioreg name="SPMCSR" address="$37"/>
  57     <ioreg name="SPL" address="$3D"/>
  58     <ioreg name="SPH" address="$3E"/>
  59     <ioreg name="SREG" address="$3F"/>
  60     <ioreg name="WDTCR" address="$60"/>
  61     <ioreg name="CLKPR" address="$61"/>
  62     <ioreg name="PRR" address="$64"/>
  63     <ioreg name="OSCCAL" address="$66"/>
  64     <ioreg name="EICRA" address="$69"/>
  65     <ioreg name="PCMSK0" address="$6B"/>
  66     <ioreg name="PCMSK1" address="$6C"/>
  67     <ioreg name="PCMSK2" address="$6D"/>
  68     <ioreg name="TIMSK0" address="$6E"/>
  69     <ioreg name="TIMSK1" address="$6F"/>
  70     <ioreg name="TIMSK2" address="$70"/>
  71     <ioreg name="PCMSK3" address="$73"/>
  72     <ioreg name="ADCL" address="$78"/>
  73     <ioreg name="ADCH" address="$79"/>
  74     <ioreg name="ADCSRA" address="$7A"/>
  75     <ioreg name="ADCSRB" address="$7B"/>
  76     <ioreg name="ADMUX" address="$7C"/>
  77     <ioreg name="DIDR0" address="$7E"/>
  78     <ioreg name="DIDR1" address="$7F"/>
  79     <ioreg name="TCCR1A" address="$80"/>
  80     <ioreg name="TCCR1B" address="$81"/>
  81     <ioreg name="TCCR1C" address="$82"/>
  82     <ioreg name="TCNT1L" address="$84"/>
  83     <ioreg name="TCNT1H" address="$85"/>
  84     <ioreg name="ICR1L" address="$86"/>
  85     <ioreg name="ICR1H" address="$87"/>
  86     <ioreg name="OCR1AL" address="$88"/>
  87     <ioreg name="OCR1AH" address="$89"/>
  88     <ioreg name="OCR1BL" address="$8A"/>
  89     <ioreg name="OCR1BH" address="$8B"/>
  90     <ioreg name="TCCR2A" address="$B0"/>
  91     <ioreg name="TCNT2" address="$B2"/>
  92     <ioreg name="OCR2A" address="$B3"/>
  93     <ioreg name="ASSR" address="$B6"/>
  94     <ioreg name="USICR" address="$B8"/>
  95     <ioreg name="USISR" address="$B9"/>
  96     <ioreg name="USIDR" address="$BA"/>
  97     <ioreg name="UCSR0A" address="$C0"/>
  98     <ioreg name="UCSR0B" address="$C1"/>
  99     <ioreg name="UCSR0C" address="$C2"/>
 100     <ioreg name="UBRR0L" address="$C4"/>
 101     <ioreg name="UBRR0H" address="$C5"/>
 102     <ioreg name="UDR0" address="$C6"/>
 103     <ioreg name="PINH" address="$D8"/>
 104     <ioreg name="DDRH" address="$D9"/>
 105     <ioreg name="PORTH" address="$DA"/>
 106     <ioreg name="PINJ" address="$DB"/>
 107     <ioreg name="DDRJ" address="$DC"/>
 108     <ioreg name="PORTJ" address="$DD"/>
 109     <ioreg name="LCDCRA" address="$E4"/>
 110     <ioreg name="LCDCRB" address="$E5"/>
 111     <ioreg name="LCDFRR" address="$E6"/>
 112     <ioreg name="LCDCCR" address="$E7"/>
 113     <ioreg name="LCDDR0" address="$EC"/>
 114     <ioreg name="LCDDR1" address="$ED"/>
 115     <ioreg name="LCDDR2" address="$EE"/>
 116     <ioreg name="LCDDR3" address="$EF"/>
 117     <ioreg name="LCDDR4" address="$F0"/>
 118     <ioreg name="LCDDR5" address="$F1"/>
 119     <ioreg name="LCDDR6" address="$F2"/>
 120     <ioreg name="LCDDR7" address="$F3"/>
 121     <ioreg name="LCDDR8" address="$F4"/>
 122     <ioreg name="LCDDR9" address="$F5"/>
 123     <ioreg name="LCDDR10" address="$F6"/>
 124     <ioreg name="LCDDR11" address="$F7"/>
 125     <ioreg name="LCDDR12" address="$F8"/>
 126     <ioreg name="LCDDR13" address="$F9"/>
 127     <ioreg name="LCDDR14" address="$FA"/>
 128     <ioreg name="LCDDR15" address="$FB"/>
 129     <ioreg name="LCDDR16" address="$FC"/>
 130     <ioreg name="LCDDR17" address="$FD"/>
 131     <ioreg name="LCDDR18" address="$FE"/>
 132     <ioreg name="LCDDR19" address="$FF"/>
 133   </ioregisters>
 134   <packages>
 135     <package name="TQFP" pins="100">
 136       <pin id="1" name=""/>
 137       <pin id="2" name=""/>
 138       <pin id="3" name=""/>
 139       <pin id="4" name=""/>
 140       <pin id="5" name=""/>
 141       <pin id="6" name=""/>
 142       <pin id="7" name=""/>
 143       <pin id="8" name=""/>
 144       <pin id="9" name=""/>
 145       <pin id="10" name=""/>
 146       <pin id="11" name=""/>
 147       <pin id="12" name=""/>
 148       <pin id="13" name=""/>
 149       <pin id="14" name=""/>
 150       <pin id="15" name=""/>
 151       <pin id="16" name=""/>
 152       <pin id="17" name=""/>
 153       <pin id="18" name=""/>
 154       <pin id="19" name=""/>
 155       <pin id="20" name=""/>
 156       <pin id="21" name=""/>
 157       <pin id="22" name=""/>
 158       <pin id="23" name=""/>
 159       <pin id="24" name=""/>
 160       <pin id="25" name=""/>
 161       <pin id="26" name=""/>
 162       <pin id="27" name=""/>
 163       <pin id="28" name=""/>
 164       <pin id="29" name=""/>
 165       <pin id="30" name=""/>
 166       <pin id="31" name=""/>
 167       <pin id="32" name=""/>
 168       <pin id="33" name=""/>
 169       <pin id="34" name=""/>
 170       <pin id="35" name=""/>
 171       <pin id="36" name=""/>
 172       <pin id="37" name=""/>
 173       <pin id="38" name=""/>
 174       <pin id="39" name=""/>
 175       <pin id="40" name=""/>
 176       <pin id="41" name=""/>
 177       <pin id="42" name=""/>
 178       <pin id="43" name=""/>
 179       <pin id="44" name=""/>
 180       <pin id="45" name=""/>
 181       <pin id="46" name=""/>
 182       <pin id="47" name=""/>
 183       <pin id="48" name=""/>
 184       <pin id="49" name=""/>
 185       <pin id="50" name=""/>
 186       <pin id="51" name=""/>
 187       <pin id="52" name=""/>
 188       <pin id="53" name=""/>
 189       <pin id="54" name=""/>
 190       <pin id="55" name=""/>
 191       <pin id="56" name=""/>
 192       <pin id="57" name=""/>
 193       <pin id="58" name=""/>
 194       <pin id="59" name=""/>
 195       <pin id="60" name=""/>
 196       <pin id="61" name=""/>
 197       <pin id="62" name=""/>
 198       <pin id="63" name=""/>
 199       <pin id="64" name=""/>
 200       <pin id="65" name=""/>
 201       <pin id="66" name=""/>
 202       <pin id="67" name=""/>
 203       <pin id="68" name=""/>
 204       <pin id="69" name=""/>
 205       <pin id="70" name=""/>
 206       <pin id="71" name=""/>
 207       <pin id="72" name=""/>
 208       <pin id="73" name=""/>
 209       <pin id="74" name=""/>
 210       <pin id="75" name=""/>
 211       <pin id="76" name=""/>
 212       <pin id="77" name=""/>
 213       <pin id="78" name=""/>
 214       <pin id="79" name=""/>
 215       <pin id="80" name=""/>
 216       <pin id="81" name=""/>
 217       <pin id="82" name=""/>
 218       <pin id="83" name=""/>
 219       <pin id="84" name=""/>
 220       <pin id="85" name=""/>
 221       <pin id="86" name=""/>
 222       <pin id="87" name=""/>
 223       <pin id="88" name=""/>
 224       <pin id="89" name=""/>
 225       <pin id="90" name=""/>
 226       <pin id="91" name=""/>
 227       <pin id="92" name=""/>
 228       <pin id="93" name=""/>
 229       <pin id="94" name=""/>
 230       <pin id="95" name=""/>
 231       <pin id="96" name=""/>
 232       <pin id="97" name=""/>
 233       <pin id="98" name=""/>
 234       <pin id="99" name=""/>
 235       <pin id="100" name=""/>
 236     </package>
 237   </packages>
 238   <interrupts num="25">
 239     <interrupt vector="1" address="$000" name="RESET">External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.     </interrupt>
 240     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
 241     <interrupt vector="3" address="$004" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
 242     <interrupt vector="4" address="$006" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
 243     <interrupt vector="5" address="$008" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
 244     <interrupt vector="6" address="$00A" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
 245     <interrupt vector="7" address="$00C" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
 246     <interrupt vector="8" address="$00E" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
 247     <interrupt vector="9" address="$010" name="TIMER1 COMPB">Timer/Counter Compare Match B</interrupt>
 248     <interrupt vector="10" address="$012" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
 249     <interrupt vector="11" address="$014" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
 250     <interrupt vector="12" address="$016" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
 251     <interrupt vector="13" address="$018" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
 252     <interrupt vector="14" address="$01A" name="USART, RX">USART, Rx Complete</interrupt>
 253     <interrupt vector="15" address="$01C" name="USART, UDRE">USART Data register Empty</interrupt>
 254     <interrupt vector="16" address="$01E" name="USART0, TX">USART0, Tx Complete</interrupt>
 255     <interrupt vector="17" address="$020" name="USI START">USI Start Condition</interrupt>
 256     <interrupt vector="18" address="$022" name="USI OVERFLOW">USI Overflow</interrupt>
 257     <interrupt vector="19" address="$024" name="ANALOG COMP">Analog Comparator</interrupt>
 258     <interrupt vector="20" address="$026" name="ADC">ADC Conversion Complete</interrupt>
 259     <interrupt vector="21" address="$028" name="EE_READY">EEPROM Ready</interrupt>
 260     <interrupt vector="22" address="$02A" name="SPM_READY">Store Program Memory Read</interrupt>
 261     <interrupt vector="23" address="$02C" name="LCD">LCD Start of Frame</interrupt>
 262     <interrupt vector="24" address="$02E" name="PCINT2">Pin Change Interrupt Request 2</interrupt>
 263     <interrupt vector="25" address="$030" name="PCINT3">Pin Change Interrupt Request 3</interrupt>
 264   </interrupts>
 265   <hardware>
 266 <!--Everything after this needs editing!!!-->
 267     <module class="FUSE">
 268       <registers name="FUSE" memspace="FUSE">
 269           <reg size="1" name="EXTENDED" offset="0x02">
 270             <bitfield name="BODLEVEL" mask="0x06" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 271             <bitfield name="RSTDISBL" mask="0x01" text="External Reset Disable" icon=""/>
 272           </reg>
 273           <reg size="1" name="HIGH" offset="0x01">
 274             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 275             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 276             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enable" icon=""/>
 277             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 278             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 279             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 280             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 281           </reg>
 282           <reg size="1" name="LOW" offset="0x00">
 283             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 284             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTE7" icon=""/>
 285             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 286           </reg>
 287         </registers>
 288     </module>
 289     <module class="LOCKBIT">
 290       <registers name="LOCKBIT" memspace="LOCKBIT">
 291           <reg size="1" name="LOCKBIT" offset="0x00">
 292             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 293             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 294             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 295           </reg>
 296         </registers>
 297     </module>
 298     <module class="AD_CONVERTER">
 299       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 300           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 301             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF3"/>
 302             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 303             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 304           </reg>
 305           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 306             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 307             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 308             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 309             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 310             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 311             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 312           </reg>
 313           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 314           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp">
 315             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon=""/>
 316           </reg>
 317           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp">
 318             <bitfield name="ADC7D" mask="0x80" text="ADC7 Digital input Disable" icon=""/>
 319             <bitfield name="ADC6D" mask="0x40" text="ADC6 Digital input Disable" icon=""/>
 320             <bitfield name="ADC5D" mask="0x20" text="ADC5 Digital input Disable" icon=""/>
 321             <bitfield name="ADC4D" mask="0x10" text="ADC4 Digital input Disable" icon=""/>
 322             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 323             <bitfield name="ADC2D" mask="0x04" text="ADC2 Digital input Disable" icon=""/>
 324             <bitfield name="ADC1D" mask="0x02" text="ADC1 Digital input Disable" icon=""/>
 325             <bitfield name="ADC0D" mask="0x01" text="ADC0 Digital input Disable" icon=""/>
 326           </reg>
 327         </registers>
 328     </module>
 329     <module class="ANALOG_COMPARATOR">
 330       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 331           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_flag.bmp">
 332             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 333           </reg>
 334           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 335             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 336             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 337             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 338             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 339             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 340             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 341             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 342           </reg>
 343           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 344             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 345             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 346           </reg>
 347         </registers>
 348     </module>
 349     <module class="SPI">
 350       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 351           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 352             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 353             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 354             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 355             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 356             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 357             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 358             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 359           </reg>
 360           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 361             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 362             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 363             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 364           </reg>
 365           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 366         </registers>
 367     </module>
 368     <module class="USI">
 369       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 370           <reg size="1" name="USIDR" offset="0xBA" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 371           <reg size="1" name="USISR" offset="0xB9" text="USI Status Register" icon="io_flag.bmp">
 372             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 373             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 374             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 375             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 376             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 377           </reg>
 378           <reg size="1" name="USICR" offset="0xB8" text="USI Control Register" icon="io_flag.bmp">
 379             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 380             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 381             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 382             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 383             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 384             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 385           </reg>
 386         </registers>
 387     </module>
 388     <module class="USART0">
 389       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 390           <reg size="1" name="UDR0" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 391           <reg size="1" name="UCSR0A" offset="0xC0" text="USART Control and Status Register A" icon="io_flag.bmp">
 392             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 393             <bitfield name="TXC0" mask="0x40" text="USART Transmit Complete" icon=""/>
 394             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 395             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 396             <bitfield name="DOR0" mask="0x08" text="Data OverRun" icon=""/>
 397             <bitfield name="UPE0" mask="0x04" text="USART Parity Error" icon=""/>
 398             <bitfield name="U2X0" mask="0x02" text="Double the USART Transmission Speed" icon=""/>
 399             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 400           </reg>
 401           <reg size="1" name="UCSR0B" offset="0xC1" text="USART Control and Status Register B" icon="io_flag.bmp">
 402             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 403             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 404             <bitfield name="UDRIE0" mask="0x20" text="USART Data Register Empty Interrupt Enable" icon=""/>
 405             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 406             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 407             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 408             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 409             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 410           </reg>
 411           <reg size="1" name="UCSR0C" offset="0xC2" text="USART Control and Status Register C" icon="io_flag.bmp">
 412             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 413             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 414             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 415             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 416             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 417           </reg>
 418           <reg size="2" name="UBRR0" offset="0xC4" text="USART Baud Rate Register  Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 419         </registers>
 420     </module>
 421     <module class="CPU">
 422       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 423           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 424             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 425             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 426             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 427             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 428             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 429             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 430             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 431             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 432           </reg>
 433           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 434           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 435             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 436             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 437             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 438           </reg>
 439           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 440             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 441             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 442             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 443             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 444             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 445           </reg>
 446           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 447           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_cpu.bmp">
 448             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 449             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 450           </reg>
 451           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 452             <bitfield name="PRLCD" mask="0x10" text="Power Reduction LCD" icon=""/>
 453             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 454             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 455             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 456             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 457           </reg>
 458           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 459             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 460             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 461           </reg>
 462           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp" mask="0xFF"/>
 463           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp" mask="0xFF"/>
 464           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp" mask="0xFF"/>
 465         </registers>
 466     </module>
 467     <module class="JTAG">
 468       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 469           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp" mask="0xFF"/>
 470           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 471             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 472           </reg>
 473           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 474             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 475           </reg>
 476         </registers>
 477     </module>
 478     <module class="EEPROM">
 479       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 480           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x07FF"/>
 481           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 482           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 483             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 484             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 485             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 486             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 487           </reg>
 488         </registers>
 489     </module>
 490     <module class="PORTA">
 491       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 492           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 493           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 494           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 495         </registers>
 496     </module>
 497     <module class="PORTB">
 498       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 499           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 500           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 501           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 502         </registers>
 503     </module>
 504     <module class="PORTC">
 505       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 506           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 507           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 508           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 509         </registers>
 510     </module>
 511     <module class="PORTD">
 512       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 513           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 514           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 515           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 516         </registers>
 517     </module>
 518     <module class="PORTE">
 519       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 520           <reg size="1" name="PORTE" offset="0x2E" text="Data Register, Port E" icon="io_port.bmp" mask="0xFF"/>
 521           <reg size="1" name="DDRE" offset="0x2D" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0xFF"/>
 522           <reg size="1" name="PINE" offset="0x2C" text="Input Pins, Port E" icon="io_port.bmp" mask="0xFF"/>
 523         </registers>
 524     </module>
 525     <module class="PORTF">
 526       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 527           <reg size="1" name="PORTF" offset="0x31" text="Data Register, Port F" icon="io_port.bmp" mask="0xFF"/>
 528           <reg size="1" name="DDRF" offset="0x30" text="Data Direction Register, Port F" icon="io_flag.bmp" mask="0xFF"/>
 529           <reg size="1" name="PINF" offset="0x2F" text="Input Pins, Port F" icon="io_port.bmp" mask="0xFF"/>
 530         </registers>
 531     </module>
 532     <module class="PORTG">
 533       <registers name="PORTG" memspace="DATAMEM" text="" icon="io_port.bmp">
 534           <reg size="1" name="PORTG" offset="0x34" text="Port G Data Register" icon="io_port.bmp" mask="0x1F"/>
 535           <reg size="1" name="DDRG" offset="0x33" text="Port G Data Direction Register" icon="io_flag.bmp" mask="0x1F"/>
 536           <reg size="1" name="PING" offset="0x32" text="Port G Input Pins" icon="io_port.bmp" mask="0x3F"/>
 537         </registers>
 538     </module>
 539     <module class="TIMER_COUNTER_0">
 540       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 541           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 542             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare" icon=""/>
 543             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 544             <bitfield name="COM0A" mask="0x30" text="Compare Match Output Modes" icon=""/>
 545             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 546             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 547           </reg>
 548           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 549           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 550           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 551             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt Enable" icon=""/>
 552             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 553           </reg>
 554           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 555             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0" icon=""/>
 556             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 557           </reg>
 558           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Control Register" icon="io_cpu.bmp">
 559             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 560             <bitfield name="PSR310" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 561           </reg>
 562         </registers>
 563     </module>
 564     <module class="TIMER_COUNTER_1">
 565       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 566           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 567             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 568             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 569             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 570           </reg>
 571           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 572             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 573             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 574             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 575             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 576           </reg>
 577           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter 1 Control Register C" icon="io_flag.bmp">
 578             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare 1A" icon=""/>
 579             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare 1B" icon=""/>
 580           </reg>
 581           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 582           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Outbut Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 583           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 584           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 585           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 586             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 587             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 588             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 589             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 590           </reg>
 591           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter1 Interrupt Flag register" icon="io_flag.bmp">
 592             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 593             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 594             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 595             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 596           </reg>
 597         </registers>
 598     </module>
 599     <module class="TIMER_COUNTER_2">
 600       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 601           <reg size="1" name="TCCR2A" offset="0xB0" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 602             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare A" icon=""/>
 603             <bitfield name="WGM20" mask="0x40" text="Waveform Generation Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 604             <bitfield name="COM2A" mask="0x30" text="Compare Output Mode bits" icon=""/>
 605             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 606             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 607           </reg>
 608           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 609           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 610           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter2 Interrupt Mask register" icon="io_flag.bmp">
 611             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 612             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 613           </reg>
 614           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter2 Interrupt Flag Register" icon="io_flag.bmp">
 615             <bitfield name="OCF2A" mask="0x02" text="Timer/Counter2 Output Compare Flag 2" icon=""/>
 616             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 617           </reg>
 618           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_cpu.bmp">
 619             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 620           </reg>
 621           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.bmp">
 622             <bitfield name="EXCLK" mask="0x10" text="Enable External Clock Interrupt" icon=""/>
 623             <bitfield name="AS2" mask="0x08" text="AS2: Asynchronous Timer/Counter2" icon=""/>
 624             <bitfield name="TCN2UB" mask="0x04" text="TCN2UB: Timer/Counter2 Update Busy" icon=""/>
 625             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 626             <bitfield name="TCR2UB" mask="0x01" text="TCR2UB: Timer/Counter Control Register2 Update Busy" icon=""/>
 627           </reg>
 628         </registers>
 629     </module>
 630     <module class="WATCHDOG">
 631       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 632           <reg size="1" name="WDTCR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 633             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 634             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 635             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 636           </reg>
 637         </registers>
 638     </module>
 639     <module class="BOOT_LOAD">
 640       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 641           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 642             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 643             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 644             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 645             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 646             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 647             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 648             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 649           </reg>
 650         </registers>
 651     </module>
 652     <module class="PORTH">
 653       <registers name="PORTH" memspace="DATAMEM" text="" icon="io_port.bmp">
 654           <reg size="1" name="PORTH" offset="0xDA" text="PORT H Data Register" icon="io_port.bmp" mask="0xFF"/>
 655           <reg size="1" name="DDRH" offset="0xD9" text="PORT H Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 656           <reg size="1" name="PINH" offset="0xD8" text="PORT H Input Pins" icon="io_port.bmp" mask="0xFF"/>
 657         </registers>
 658     </module>
 659     <module class="PORTJ">
 660       <registers name="PORTJ" memspace="DATAMEM" text="" icon="io_port.bmp">
 661           <reg size="1" name="PORTJ" offset="0xDD" text="PORT J Data Register" icon="io_port.bmp" mask="0x7F"/>
 662           <reg size="1" name="DDRJ" offset="0xDC" text="PORT J Data Direction Register" icon="io_flag.bmp" mask="0x7F"/>
 663           <reg size="1" name="PINJ" offset="0xDB" text="PORT J Input Pins" icon="io_port.bmp" mask="0x7F"/>
 664         </registers>
 665     </module>
 666     <module class="LCD">
 667       <registers name="LCD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 668           <reg size="1" name="LCDDR19" offset="0xFF" text="LCD Data Register 19" icon="io_flag.bmp" mask="0xFF"/>
 669           <reg size="1" name="LCDDR18" offset="0xFE" text="LCD Data Register 18" icon="io_flag.bmp" mask="0xFF"/>
 670           <reg size="1" name="LCDDR17" offset="0xFD" text="LCD Data Register 17" icon="io_flag.bmp" mask="0xFF"/>
 671           <reg size="1" name="LCDDR16" offset="0xFC" text="LCD Data Register 16" icon="io_flag.bmp" mask="0xFF"/>
 672           <reg size="1" name="LCDDR15" offset="0xFB" text="LCD Data Register 15" icon="io_flag.bmp" mask="0xFF"/>
 673           <reg size="1" name="LCDDR14" offset="0xFA" text="LCD Data Register 14" icon="io_flag.bmp" mask="0xFF"/>
 674           <reg size="1" name="LCDDR13" offset="0xF9" text="LCD Data Register 13" icon="io_flag.bmp" mask="0xFF"/>
 675           <reg size="1" name="LCDDR12" offset="0xF8" text="LCD Data Register 12" icon="io_flag.bmp" mask="0xFF"/>
 676           <reg size="1" name="LCDDR11" offset="0xF7" text="LCD Data Register 11" icon="io_flag.bmp" mask="0xFF"/>
 677           <reg size="1" name="LCDDR10" offset="0xF6" text="LCD Data Register 10" icon="io_flag.bmp" mask="0xFF"/>
 678           <reg size="1" name="LCDDR9" offset="0xF5" text="LCD Data Register 9" icon="io_flag.bmp" mask="0xFF"/>
 679           <reg size="1" name="LCDDR8" offset="0xF4" text="LCD Data Register 8" icon="io_flag.bmp" mask="0xFF"/>
 680           <reg size="1" name="LCDDR7" offset="0xF3" text="LCD Data Register 7" icon="io_flag.bmp" mask="0xFF"/>
 681           <reg size="1" name="LCDDR6" offset="0xF2" text="LCD Data Register 6" icon="io_flag.bmp" mask="0xFF"/>
 682           <reg size="1" name="LCDDR5" offset="0xF1" text="LCD Data Register 5" icon="io_flag.bmp" mask="0xFF"/>
 683           <reg size="1" name="LCDDR4" offset="0xF0" text="LCD Data Register 4" icon="io_flag.bmp" mask="0xFF"/>
 684           <reg size="1" name="LCDDR3" offset="0xEF" text="LCD Data Register 3" icon="io_flag.bmp" mask="0xFF"/>
 685           <reg size="1" name="LCDDR2" offset="0xEE" text="LCD Data Register 2" icon="io_flag.bmp" mask="0xFF"/>
 686           <reg size="1" name="LCDDR1" offset="0xED" text="LCD Data Register 1" icon="io_flag.bmp" mask="0xFF"/>
 687           <reg size="1" name="LCDDR0" offset="0xEC" text="LCD Data Register 0" icon="io_flag.bmp" mask="0xFF"/>
 688           <reg size="1" name="LCDCCR" offset="0xE7" text="LCD Contrast Control Register" icon="io_flag.bmp" mask="0xEF"/>
 689           <reg size="1" name="LCDFRR" offset="0xE6" text="LCD Frame Rate Register" icon="io_flag.bmp">
 690             <bitfield name="LCDPS" mask="0x70" text="LCD Prescaler Selects" icon="" enum="LCD_PRESCALE"/>
 691             <bitfield name="LCDCD" mask="0x07" text="LCD Clock Dividers" icon="" enum="MISC_3BIT_COUNT"/>
 692           </reg>
 693           <reg size="1" name="LCDCRB" offset="0xE5" text="LCD Control and Status Register B" icon="io_flag.bmp">
 694             <bitfield name="LCDCS" mask="0x80" text="LCD CLock Select" icon=""/>
 695             <bitfield name="LCD2B" mask="0x40" text="LCD 1/2 Bias Select" icon=""/>
 696             <bitfield name="LCDMUX" mask="0x30" text="LCD Mux Selects" icon=""/>
 697             <bitfield name="LCDPM" mask="0x0F" text="LCD Port Masks" icon="" enum="LCD_PORT_MASK_4BIT"/>
 698           </reg>
 699           <reg size="1" name="LCDCRA" offset="0xE4" text="LCD Control and Status Register A" icon="io_flag.bmp">
 700             <bitfield name="LCDEN" mask="0x80" text="LCD Enable" icon=""/>
 701             <bitfield name="LCDAB" mask="0x40" text="LCD A or B waveform" icon=""/>
 702             <bitfield name="LCDIF" mask="0x10" text="LCD Interrupt Flag" icon=""/>
 703             <bitfield name="LCDIE" mask="0x08" text="LCD Interrupt Enable" icon=""/>
 704             <bitfield name="LCDBL" mask="0x01" text="LCD Blanking" icon=""/>
 705           </reg>
 706         </registers>
 707     </module>
 708     <module class="EXTERNAL_INTERRUPT">
 709       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 710           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 711             <bitfield name="ISC01" mask="0x02" text="External Interrupt Sense Control 0 Bit 1" icon=""/>
 712             <bitfield name="ISC00" mask="0x01" text="External Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 713           </reg>
 714           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 715             <bitfield name="PCIE" mask="0xF0" text="Pin Change Interrupt Enables" icon=""/>
 716             <bitfield name="INT0" mask="0x01" text="External Interrupt Request 0 Enable" icon=""/>
 717           </reg>
 718           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 719             <bitfield name="PCIF" mask="0xF0" text="Pin Change Interrupt Flags" icon=""/>
 720             <bitfield name="INTF0" mask="0x01" text="External Interrupt Flag 0" icon=""/>
 721           </reg>
 722           <reg size="1" name="PCMSK3" offset="0x73" text="Pin Change Mask Register 3" icon="io_flag.bmp" mask="0x7F"/>
 723           <reg size="1" name="PCMSK2" offset="0x6D" text="Pin Change Mask Register 2" icon="io_flag.bmp" mask="0xFF"/>
 724           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp" mask="0xFF"/>
 725           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp" mask="0xFF"/>
 726         </registers>
 727     </module>
 728   </hardware>
 729 </device>