devices/atmega649

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="23">
   5     <interrupt vector="1" address="$000" name="RESET">External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.     </interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$004" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$006" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1 COMPB">Timer/Counter Compare Match B</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
  18     <interrupt vector="14" address="$01A" name="USART0, RX">USART0, Rx Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="USART0, UDRE">USART0 Data register Empty</interrupt>
  20     <interrupt vector="16" address="$01E" name="USART0, TX">USART0, Tx Complete</interrupt>
  21     <interrupt vector="17" address="$020" name="USI START">USI Start Condition</interrupt>
  22     <interrupt vector="18" address="$022" name="USI OVERFLOW">USI Overflow</interrupt>
  23     <interrupt vector="19" address="$024" name="ANALOG COMP">Analog Comparator</interrupt>
  24     <interrupt vector="20" address="$026" name="ADC">ADC Conversion Complete</interrupt>
  25     <interrupt vector="21" address="$028" name="EE_READY">EEPROM Ready</interrupt>
  26     <interrupt vector="22" address="$02A" name="SPM_READY">Store Program Memory Read</interrupt>
  27     <interrupt vector="23" address="$02C" name="LCD">LCD Start of Frame</interrupt>
  28   </interrupts>
  29   <packages>
  30     <package name="TQFP" pins="64">
  31       <pin id="1" name=""/>
  32       <pin id="2" name=""/>
  33       <pin id="3" name=""/>
  34       <pin id="4" name=""/>
  35       <pin id="5" name=""/>
  36       <pin id="6" name=""/>
  37       <pin id="7" name=""/>
  38       <pin id="8" name=""/>
  39       <pin id="9" name=""/>
  40       <pin id="10" name=""/>
  41       <pin id="11" name=""/>
  42       <pin id="12" name=""/>
  43       <pin id="13" name=""/>
  44       <pin id="14" name=""/>
  45       <pin id="15" name=""/>
  46       <pin id="16" name=""/>
  47       <pin id="17" name=""/>
  48       <pin id="18" name=""/>
  49       <pin id="19" name=""/>
  50       <pin id="20" name=""/>
  51       <pin id="21" name=""/>
  52       <pin id="22" name=""/>
  53       <pin id="23" name=""/>
  54       <pin id="24" name=""/>
  55       <pin id="25" name=""/>
  56       <pin id="26" name=""/>
  57       <pin id="27" name=""/>
  58       <pin id="28" name=""/>
  59       <pin id="29" name=""/>
  60       <pin id="30" name=""/>
  61       <pin id="31" name=""/>
  62       <pin id="32" name=""/>
  63       <pin id="33" name=""/>
  64       <pin id="34" name=""/>
  65       <pin id="35" name=""/>
  66       <pin id="36" name=""/>
  67       <pin id="37" name=""/>
  68       <pin id="38" name=""/>
  69       <pin id="39" name=""/>
  70       <pin id="40" name=""/>
  71       <pin id="41" name=""/>
  72       <pin id="42" name=""/>
  73       <pin id="43" name=""/>
  74       <pin id="44" name=""/>
  75       <pin id="45" name=""/>
  76       <pin id="46" name=""/>
  77       <pin id="47" name=""/>
  78       <pin id="48" name=""/>
  79       <pin id="49" name=""/>
  80       <pin id="50" name=""/>
  81       <pin id="51" name=""/>
  82       <pin id="52" name=""/>
  83       <pin id="53" name=""/>
  84       <pin id="54" name=""/>
  85       <pin id="55" name=""/>
  86       <pin id="56" name=""/>
  87       <pin id="57" name=""/>
  88       <pin id="58" name=""/>
  89       <pin id="59" name=""/>
  90       <pin id="60" name=""/>
  91       <pin id="61" name=""/>
  92       <pin id="62" name=""/>
  93       <pin id="63" name=""/>
  94       <pin id="64" name=""/>
  95     </package>
  96   </packages>
  97   <memory>
  98     <flash size="65536"/>
  99     <iospace start="$20" stop="$FF"/>
 100     <sram size="4096"/>
 101     <eram size="0"/>
 102   </memory>
 103   <ioregisters>
 104     <ioreg name="PINA" address="$00"/>
 105     <ioreg name="DDRA" address="$01"/>
 106     <ioreg name="PORTA" address="$02"/>
 107     <ioreg name="PINB" address="$03"/>
 108     <ioreg name="DDRB" address="$04"/>
 109     <ioreg name="PORTB" address="$05"/>
 110     <ioreg name="PINC" address="$06"/>
 111     <ioreg name="DDRC" address="$07"/>
 112     <ioreg name="PORTC" address="$08"/>
 113     <ioreg name="PIND" address="$09"/>
 114     <ioreg name="DDRD" address="$0A"/>
 115     <ioreg name="PORTD" address="$0B"/>
 116     <ioreg name="PINE" address="$0C"/>
 117     <ioreg name="DDRE" address="$0D"/>
 118     <ioreg name="PORTE" address="$0E"/>
 119     <ioreg name="PINF" address="$0F"/>
 120     <ioreg name="DDRF" address="$10"/>
 121     <ioreg name="PORTF" address="$11"/>
 122     <ioreg name="PING" address="$12"/>
 123     <ioreg name="DDRG" address="$13"/>
 124     <ioreg name="PORTG" address="$14"/>
 125     <ioreg name="TIFR0" address="$15"/>
 126     <ioreg name="TIFR1" address="$16"/>
 127     <ioreg name="TIFR2" address="$17"/>
 128     <ioreg name="EIFR" address="$1C"/>
 129     <ioreg name="EIMSK" address="$1D"/>
 130     <ioreg name="GPIOR0" address="$1E"/>
 131     <ioreg name="EECR" address="$1F"/>
 132     <ioreg name="EEDR" address="$20"/>
 133     <ioreg name="EEARL" address="$21"/>
 134     <ioreg name="EEARH" address="$22"/>
 135     <ioreg name="GTCCR" address="$23"/>
 136     <ioreg name="TCCR0A" address="$24"/>
 137     <ioreg name="TCNT0" address="$26"/>
 138     <ioreg name="OCR0A" address="$27"/>
 139     <ioreg name="GPIOR1" address="$2A"/>
 140     <ioreg name="GPIOR2" address="$2B"/>
 141     <ioreg name="SPCR" address="$2C"/>
 142     <ioreg name="SPSR" address="$2D"/>
 143     <ioreg name="SPDR" address="$2E"/>
 144     <ioreg name="ACSR" address="$30"/>
 145     <ioreg name="OCDR" address="$31"/>
 146     <ioreg name="SMCR" address="$33"/>
 147     <ioreg name="MCUSR" address="$34"/>
 148     <ioreg name="MCUCR" address="$35"/>
 149     <ioreg name="SPMCSR" address="$37"/>
 150     <ioreg name="SPL" address="$3D"/>
 151     <ioreg name="SPH" address="$3E"/>
 152     <ioreg name="SREG" address="$3F"/>
 153     <ioreg name="WDTCR" address="$60"/>
 154     <ioreg name="CLKPR" address="$61"/>
 155     <ioreg name="PRR" address="$64"/>
 156     <ioreg name="OSCCAL" address="$66"/>
 157     <ioreg name="EICRA" address="$69"/>
 158     <ioreg name="PCMSK0" address="$6B"/>
 159     <ioreg name="PCMSK1" address="$6C"/>
 160     <ioreg name="TIMSK0" address="$6E"/>
 161     <ioreg name="TIMSK1" address="$6F"/>
 162     <ioreg name="TIMSK2" address="$70"/>
 163     <ioreg name="ADCL" address="$78"/>
 164     <ioreg name="ADCH" address="$79"/>
 165     <ioreg name="ADCSRA" address="$7A"/>
 166     <ioreg name="ADCSRB" address="$7B"/>
 167     <ioreg name="ADMUX" address="$7C"/>
 168     <ioreg name="DIDR0" address="$7E"/>
 169     <ioreg name="DIDR1" address="$7F"/>
 170     <ioreg name="TCCR1A" address="$80"/>
 171     <ioreg name="TCCR1B" address="$81"/>
 172     <ioreg name="TCCR1C" address="$82"/>
 173     <ioreg name="TCNT1L" address="$84"/>
 174     <ioreg name="TCNT1H" address="$85"/>
 175     <ioreg name="ICR1L" address="$86"/>
 176     <ioreg name="ICR1H" address="$87"/>
 177     <ioreg name="OCR1AL" address="$88"/>
 178     <ioreg name="OCR1AH" address="$89"/>
 179     <ioreg name="OCR1BL" address="$8A"/>
 180     <ioreg name="OCR1BH" address="$8B"/>
 181     <ioreg name="TCCR2A" address="$B0"/>
 182     <ioreg name="TCNT2" address="$B2"/>
 183     <ioreg name="OCR2A" address="$B3"/>
 184     <ioreg name="ASSR" address="$B6"/>
 185     <ioreg name="USICR" address="$B8"/>
 186     <ioreg name="USISR" address="$B9"/>
 187     <ioreg name="USIDR" address="$BA"/>
 188     <ioreg name="UCSR0A" address="$C0"/>
 189     <ioreg name="UCSR0B" address="$C1"/>
 190     <ioreg name="UCSR0C" address="$C2"/>
 191     <ioreg name="UBRR0L" address="$C4"/>
 192     <ioreg name="UBRR0H" address="$C5"/>
 193     <ioreg name="UDR0" address="$C6"/>
 194     <ioreg name="LCDCRA" address="$E4"/>
 195     <ioreg name="LCDCRB" address="$E5"/>
 196     <ioreg name="LCDFRR" address="$E6"/>
 197     <ioreg name="LCDCCR" address="$E7"/>
 198     <ioreg name="LCDDR0" address="$EC"/>
 199     <ioreg name="LCDDR1" address="$ED"/>
 200     <ioreg name="LCDDR2" address="$EE"/>
 201     <ioreg name="LCDDR3" address="$EF"/>
 202     <ioreg name="LCDDR4" address="$F0"/>
 203     <ioreg name="LCDDR5" address="$F1"/>
 204     <ioreg name="LCDDR6" address="$F2"/>
 205     <ioreg name="LCDDR7" address="$F3"/>
 206     <ioreg name="LCDDR8" address="$F4"/>
 207     <ioreg name="LCDDR9" address="$F5"/>
 208     <ioreg name="LCDDR10" address="$F6"/>
 209     <ioreg name="LCDDR11" address="$F7"/>
 210     <ioreg name="LCDDR12" address="$F8"/>
 211     <ioreg name="LCDDR13" address="$F9"/>
 212     <ioreg name="LCDDR14" address="$FA"/>
 213     <ioreg name="LCDDR15" address="$FB"/>
 214     <ioreg name="LCDDR16" address="$FC"/>
 215     <ioreg name="LCDDR17" address="$FD"/>
 216     <ioreg name="LCDDR18" address="$FE"/>
 217     <ioreg name="LCDDR19" address="$FF"/>
 218   </ioregisters>
 219   <hardware>
 220 <!--Everything after this needs editing!!!-->
 221     <module class="FUSE">
 222       <registers name="FUSE" memspace="FUSE">
 223           <reg size="1" name="EXTENDED" offset="0x02">
 224             <bitfield name="BODLEVEL" mask="0x06" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 225             <bitfield name="RSTDISBL" mask="0x01" text="External Reset Disable" icon=""/>
 226           </reg>
 227           <reg size="1" name="HIGH" offset="0x01">
 228             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 229             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 230             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enable" icon=""/>
 231             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 232             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 233             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 234             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 235           </reg>
 236           <reg size="1" name="LOW" offset="0x00">
 237             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 238             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTE7" icon=""/>
 239             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 240           </reg>
 241         </registers>
 242     </module>
 243     <module class="LOCKBIT">
 244       <registers name="LOCKBIT" memspace="LOCKBIT">
 245           <reg size="1" name="LOCKBIT" offset="0x00">
 246             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 247             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 248             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 249           </reg>
 250         </registers>
 251     </module>
 252     <module class="AD_CONVERTER">
 253       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 254           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 255             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF3"/>
 256             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 257             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 258           </reg>
 259           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 260             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 261             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 262             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 263             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 264             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 265             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 266           </reg>
 267           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 268           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp">
 269             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon=""/>
 270           </reg>
 271           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp">
 272             <bitfield name="ADC7D" mask="0x80" text="ADC7 Digital input Disable" icon=""/>
 273             <bitfield name="ADC6D" mask="0x40" text="ADC6 Digital input Disable" icon=""/>
 274             <bitfield name="ADC5D" mask="0x20" text="ADC5 Digital input Disable" icon=""/>
 275             <bitfield name="ADC4D" mask="0x10" text="ADC4 Digital input Disable" icon=""/>
 276             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 277             <bitfield name="ADC2D" mask="0x04" text="ADC2 Digital input Disable" icon=""/>
 278             <bitfield name="ADC1D" mask="0x02" text="ADC1 Digital input Disable" icon=""/>
 279             <bitfield name="ADC0D" mask="0x01" text="ADC0 Digital input Disable" icon=""/>
 280           </reg>
 281         </registers>
 282     </module>
 283     <module class="ANALOG_COMPARATOR">
 284       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 285           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_flag.bmp">
 286             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 287           </reg>
 288           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 289             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 290             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 291             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 292             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 293             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 294             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 295             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 296           </reg>
 297           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 298             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 299             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 300           </reg>
 301         </registers>
 302     </module>
 303     <module class="SPI">
 304       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 305           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 306             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 307             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 308             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 309             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 310             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 311             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 312             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 313           </reg>
 314           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 315             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 316             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 317             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 318           </reg>
 319           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 320         </registers>
 321     </module>
 322     <module class="USI">
 323       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 324           <reg size="1" name="USIDR" offset="0xBA" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 325           <reg size="1" name="USISR" offset="0xB9" text="USI Status Register" icon="io_flag.bmp">
 326             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 327             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 328             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 329             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 330             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 331           </reg>
 332           <reg size="1" name="USICR" offset="0xB8" text="USI Control Register" icon="io_flag.bmp">
 333             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 334             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 335             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 336             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 337             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 338             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 339           </reg>
 340         </registers>
 341     </module>
 342     <module class="USART0">
 343       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 344           <reg size="1" name="UDR0" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 345           <reg size="1" name="UCSR0A" offset="0xC0" text="USART Control and Status Register A" icon="io_flag.bmp">
 346             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 347             <bitfield name="TXC0" mask="0x40" text="USART Transmit Complete" icon=""/>
 348             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 349             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 350             <bitfield name="DOR0" mask="0x08" text="Data OverRun" icon=""/>
 351             <bitfield name="UPE0" mask="0x04" text="USART Parity Error" icon=""/>
 352             <bitfield name="U2X0" mask="0x02" text="Double the USART Transmission Speed" icon=""/>
 353             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 354           </reg>
 355           <reg size="1" name="UCSR0B" offset="0xC1" text="USART Control and Status Register B" icon="io_flag.bmp">
 356             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 357             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 358             <bitfield name="UDRIE0" mask="0x20" text="USART Data Register Empty Interrupt Enable" icon=""/>
 359             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 360             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 361             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 362             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 363             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 364           </reg>
 365           <reg size="1" name="UCSR0C" offset="0xC2" text="USART Control and Status Register C" icon="io_flag.bmp">
 366             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 367             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 368             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 369             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 370             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 371           </reg>
 372           <reg size="2" name="UBRR0" offset="0xC4" text="USART Baud Rate Register  Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 373         </registers>
 374     </module>
 375     <module class="CPU">
 376       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 377           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 378             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 379             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 380             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 381             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 382             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 383             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 384             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 385             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 386           </reg>
 387           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 388           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 389             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 390             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 391             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 392           </reg>
 393           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 394             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 395             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 396             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 397             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 398             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 399           </reg>
 400           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 401           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_cpu.bmp">
 402             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 403             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 404           </reg>
 405           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 406             <bitfield name="PRLCD" mask="0x10" text="Power Reduction LCD" icon=""/>
 407             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 408             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 409             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 410             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 411           </reg>
 412           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 413             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 414             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 415           </reg>
 416           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp" mask="0xFF"/>
 417           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp" mask="0xFF"/>
 418           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp" mask="0xFF"/>
 419         </registers>
 420     </module>
 421     <module class="JTAG">
 422       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 423           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp" mask="0xFF"/>
 424           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 425             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 426           </reg>
 427           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 428             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 429           </reg>
 430         </registers>
 431     </module>
 432     <module class="LCD">
 433       <registers name="LCD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 434           <reg size="1" name="LCDDR18" offset="0xFE" text="LCD Data Register 18" icon="io_flag.bmp" mask="0x01"/>
 435           <reg size="1" name="LCDDR17" offset="0xFD" text="LCD Data Register 17" icon="io_flag.bmp" mask="0xFF"/>
 436           <reg size="1" name="LCDDR16" offset="0xFC" text="LCD Data Register 16" icon="io_flag.bmp" mask="0xFF"/>
 437           <reg size="1" name="LCDDR15" offset="0xFB" text="LCD Data Register 15" icon="io_flag.bmp" mask="0xFF"/>
 438           <reg size="1" name="LCDDR13" offset="0xF9" text="LCD Data Register 13" icon="io_flag.bmp" mask="0x01"/>
 439           <reg size="1" name="LCDDR12" offset="0xF8" text="LCD Data Register 12" icon="io_flag.bmp" mask="0xFF"/>
 440           <reg size="1" name="LCDDR11" offset="0xF7" text="LCD Data Register 11" icon="io_flag.bmp" mask="0xFF"/>
 441           <reg size="1" name="LCDDR10" offset="0xF6" text="LCD Data Register 10" icon="io_flag.bmp" mask="0xFF"/>
 442           <reg size="1" name="LCDDR8" offset="0xF4" text="LCD Data Register 8" icon="io_flag.bmp" mask="0x01"/>
 443           <reg size="1" name="LCDDR7" offset="0xF3" text="LCD Data Register 7" icon="io_flag.bmp" mask="0xFF"/>
 444           <reg size="1" name="LCDDR6" offset="0xF2" text="LCD Data Register 6" icon="io_flag.bmp" mask="0xFF"/>
 445           <reg size="1" name="LCDDR5" offset="0xF1" text="LCD Data Register 5" icon="io_flag.bmp" mask="0xFF"/>
 446           <reg size="1" name="LCDDR3" offset="0xEF" text="LCD Data Register 3" icon="io_flag.bmp" mask="0x01"/>
 447           <reg size="1" name="LCDDR2" offset="0xEE" text="LCD Data Register 2" icon="io_flag.bmp" mask="0xFF"/>
 448           <reg size="1" name="LCDDR1" offset="0xED" text="LCD Data Register 1" icon="io_flag.bmp" mask="0xFF"/>
 449           <reg size="1" name="LCDDR0" offset="0xEC" text="LCD Data Register 0" icon="io_flag.bmp" mask="0xFF"/>
 450           <reg size="1" name="LCDCCR" offset="0xE7" text="LCD Contrast Control Register" icon="io_flag.bmp" mask="0xEF"/>
 451           <reg size="1" name="LCDFRR" offset="0xE6" text="LCD Frame Rate Register" icon="io_flag.bmp">
 452             <bitfield name="LCDPS" mask="0x70" text="LCD Prescaler Selects" icon="" enum="LCD_PRESCALE"/>
 453             <bitfield name="LCDCD" mask="0x07" text="LCD Clock Dividers" icon="" enum="MISC_3BIT_COUNT"/>
 454           </reg>
 455           <reg size="1" name="LCDCRB" offset="0xE5" text="LCD Control and Status Register B" icon="io_flag.bmp">
 456             <bitfield name="LCDCS" mask="0x80" text="LCD CLock Select" icon=""/>
 457             <bitfield name="LCD2B" mask="0x40" text="LCD 1/2 Bias Select" icon=""/>
 458             <bitfield name="LCDMUX" mask="0x30" text="LCD Mux Selects" icon=""/>
 459             <bitfield name="LCDPM" mask="0x0F" text="LCD Port Masks" icon="" enum="LCD_PORT_MASK_4BIT"/>
 460           </reg>
 461           <reg size="1" name="LCDCRA" offset="0xE4" text="LCD Control Register A" icon="io_flag.bmp">
 462             <bitfield name="LCDEN" mask="0x80" text="LCD Enable" icon=""/>
 463             <bitfield name="LCDAB" mask="0x40" text="LCD A or B waveform" icon=""/>
 464             <bitfield name="LCDIF" mask="0x10" text="LCD Interrupt Flag" icon=""/>
 465             <bitfield name="LCDIE" mask="0x08" text="LCD Interrupt Enable" icon=""/>
 466             <bitfield name="LCDBL" mask="0x01" text="LCD Blanking" icon=""/>
 467           </reg>
 468         </registers>
 469     </module>
 470     <module class="EXTERNAL_INTERRUPT">
 471       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 472           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 473             <bitfield name="ISC01" mask="0x02" text="External Interrupt Sense Control 0 Bit 1" icon=""/>
 474             <bitfield name="ISC00" mask="0x01" text="External Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 475           </reg>
 476           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 477             <bitfield name="PCIE" mask="0xF0" text="Pin Change Interrupt Enables" icon=""/>
 478             <bitfield name="INT0" mask="0x01" text="External Interrupt Request 0 Enable" icon=""/>
 479           </reg>
 480           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 481             <bitfield name="PCIF" mask="0xF0" text="Pin Change Interrupt Flags" icon=""/>
 482             <bitfield name="INTF0" mask="0x01" text="External Interrupt Flag 0" icon=""/>
 483           </reg>
 484           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp" mask="0xFF"/>
 485           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp" mask="0xFF"/>
 486         </registers>
 487     </module>
 488     <module class="EEPROM">
 489       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 490           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x07FF"/>
 491           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 492           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 493             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 494             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 495             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 496             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 497           </reg>
 498         </registers>
 499     </module>
 500     <module class="PORTA">
 501       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 502           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 503           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 504           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 505         </registers>
 506     </module>
 507     <module class="PORTB">
 508       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 509           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 510           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 511           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 512         </registers>
 513     </module>
 514     <module class="PORTC">
 515       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 516           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 517           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 518           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 519         </registers>
 520     </module>
 521     <module class="PORTD">
 522       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 523           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 524           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 525           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 526         </registers>
 527     </module>
 528     <module class="PORTE">
 529       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 530           <reg size="1" name="PORTE" offset="0x2E" text="Data Register, Port E" icon="io_port.bmp" mask="0xFF"/>
 531           <reg size="1" name="DDRE" offset="0x2D" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0xFF"/>
 532           <reg size="1" name="PINE" offset="0x2C" text="Input Pins, Port E" icon="io_port.bmp" mask="0xFF"/>
 533         </registers>
 534     </module>
 535     <module class="PORTF">
 536       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 537           <reg size="1" name="PORTF" offset="0x31" text="Data Register, Port F" icon="io_port.bmp" mask="0xFF"/>
 538           <reg size="1" name="DDRF" offset="0x30" text="Data Direction Register, Port F" icon="io_flag.bmp" mask="0xFF"/>
 539           <reg size="1" name="PINF" offset="0x2F" text="Input Pins, Port F" icon="io_port.bmp" mask="0xFF"/>
 540         </registers>
 541     </module>
 542     <module class="PORTG">
 543       <registers name="PORTG" memspace="DATAMEM" text="" icon="io_port.bmp">
 544           <reg size="1" name="PORTG" offset="0x34" text="Port G Data Register" icon="io_port.bmp" mask="0x1F"/>
 545           <reg size="1" name="DDRG" offset="0x33" text="Port G Data Direction Register" icon="io_flag.bmp" mask="0x1F"/>
 546           <reg size="1" name="PING" offset="0x32" text="Port G Input Pins" icon="io_port.bmp" mask="0x3F"/>
 547         </registers>
 548     </module>
 549     <module class="TIMER_COUNTER_0">
 550       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 551           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 552             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare" icon=""/>
 553             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 554             <bitfield name="COM0A" mask="0x30" text="Compare Match Output Modes" icon=""/>
 555             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 556             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 557           </reg>
 558           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 559           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 560           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 561             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt Enable" icon=""/>
 562             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 563           </reg>
 564           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 565             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0" icon=""/>
 566             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 567           </reg>
 568           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Control Register" icon="io_cpu.bmp">
 569             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 570             <bitfield name="PSR310" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 571           </reg>
 572         </registers>
 573     </module>
 574     <module class="TIMER_COUNTER_1">
 575       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 576           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 577             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 578             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 579             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 580           </reg>
 581           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 582             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 583             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 584             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 585             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 586           </reg>
 587           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter 1 Control Register C" icon="io_flag.bmp">
 588             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare 1A" icon=""/>
 589             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare 1B" icon=""/>
 590           </reg>
 591           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 592           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Outbut Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 593           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 594           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 595           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 596             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 597             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 598             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 599             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 600           </reg>
 601           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter1 Interrupt Flag register" icon="io_flag.bmp">
 602             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 603             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 604             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 605             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 606           </reg>
 607         </registers>
 608     </module>
 609     <module class="TIMER_COUNTER_2">
 610       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 611           <reg size="1" name="TCCR2A" offset="0xB0" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 612             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare A" icon=""/>
 613             <bitfield name="WGM20" mask="0x40" text="Waveform Generation Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 614             <bitfield name="COM2A" mask="0x30" text="Compare Output Mode bits" icon=""/>
 615             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 616             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 617           </reg>
 618           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 619           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 620           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter2 Interrupt Mask register" icon="io_flag.bmp">
 621             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 622             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 623           </reg>
 624           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter2 Interrupt Flag Register" icon="io_flag.bmp">
 625             <bitfield name="OCF2A" mask="0x02" text="Timer/Counter2 Output Compare Flag 2" icon=""/>
 626             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 627           </reg>
 628           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_cpu.bmp">
 629             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 630           </reg>
 631           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.bmp">
 632             <bitfield name="EXCLK" mask="0x10" text="Enable External Clock Interrupt" icon=""/>
 633             <bitfield name="AS2" mask="0x08" text="AS2: Asynchronous Timer/Counter2" icon=""/>
 634             <bitfield name="TCN2UB" mask="0x04" text="TCN2UB: Timer/Counter2 Update Busy" icon=""/>
 635             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 636             <bitfield name="TCR2UB" mask="0x01" text="TCR2UB: Timer/Counter Control Register2 Update Busy" icon=""/>
 637           </reg>
 638         </registers>
 639     </module>
 640     <module class="WATCHDOG">
 641       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 642           <reg size="1" name="WDTCR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 643             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 644             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 645             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 646           </reg>
 647         </registers>
 648     </module>
 649     <module class="BOOT_LOAD">
 650       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 651           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 652             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 653             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 654             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 655             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 656             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 657             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 658             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 659           </reg>
 660         </registers>
 661     </module>
 662   </hardware>
 663 </device>