devices/atmega406

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="23">
   5     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="BPINT">Battery Protection Interrupt</interrupt>
   7     <interrupt vector="3" address="$004" name="INT0">External Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$006" name="INT1">External Interrupt Request 1</interrupt>
   9     <interrupt vector="5" address="$008" name="INT2">External Interrupt Request 2</interrupt>
  10     <interrupt vector="6" address="$00A" name="INT3">External Interrupt Request 3</interrupt>
  11     <interrupt vector="7" address="$00C" name="PCINT0">Pin Change Interrupt 0</interrupt>
  12     <interrupt vector="8" address="$00E" name="PCINT1">Pin Change Interrupt 1</interrupt>
  13     <interrupt vector="9" address="$010" name="WDT">Watchdog Timeout Interrupt</interrupt>
  14     <interrupt vector="10" address="$0012" name="WAKE_UP">Wakeup timer overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIM1_COMP">Timer/Counter 1 Compare Match</interrupt>
  16     <interrupt vector="12" address="$016" name="TIM1_OVF">Timer/Counter 1 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="TIM0_COMPA">Timer/Counter0 Compare A Match</interrupt>
  18     <interrupt vector="14" address="$01A" name="TIM0_COMPB">Timer/Counter0 Compare B Match</interrupt>
  19     <interrupt vector="15" address="$001C" name="TIM0_OVF">Timer/Counter0 Overflow</interrupt>
  20     <interrupt vector="16" address="$001E" name="TWI_BUS_CD">Two-Wire Bus Connect/Disconnect</interrupt>
  21     <interrupt vector="17" address="$0020" name="TWI">Two-Wire Serial Interface</interrupt>
  22     <interrupt vector="18" address="$0022" name="VADC">Voltage ADC Conversion Complete</interrupt>
  23     <interrupt vector="19" address="$0024" name="CCADC_CONV">Coulomb Counter ADC Conversion Complete</interrupt>
  24     <interrupt vector="20" address="$0026" name="CCADC_REG_CUR">Coloumb Counter ADC Regular Current</interrupt>
  25     <interrupt vector="21" address="$0028" name="CCADC_ACC">Coloumb Counter ADC Accumulator</interrupt>
  26     <interrupt vector="22" address="$02A" name="EE READY">EEPROM Ready</interrupt>
  27     <interrupt vector="23" address="$02C" name="SPM READY">Store Program Memory Ready</interrupt>
  28   </interrupts>
  29   <memory>
  30     <flash size="40960"/>
  31     <iospace start="$20" stop="$FF"/>
  32     <sram size="2048"/>
  33     <eram size="0"/>
  34   </memory>
  35   <ioregisters>
  36     <ioreg name="PINA" address="0x00"/>
  37     <ioreg name="DDRA" address="0x01"/>
  38     <ioreg name="PORTA" address="0x02"/>
  39     <ioreg name="PINB" address="0x03"/>
  40     <ioreg name="DDRB" address="0x04"/>
  41     <ioreg name="PORTB" address="0x05"/>
  42     <ioreg name="PORTC" address="0x08"/>
  43     <ioreg name="PIND" address="0x09"/>
  44     <ioreg name="DDRD" address="0x0A"/>
  45     <ioreg name="PORTD" address="0x0B"/>
  46     <ioreg name="TIFR0" address="0x15"/>
  47     <ioreg name="TIFR1" address="0x16"/>
  48     <ioreg name="PCIFR" address="0x1B"/>
  49     <ioreg name="EIFR" address="0x1C"/>
  50     <ioreg name="EIMSK" address="0x1D"/>
  51     <ioreg name="GPIOR0" address="0x1E"/>
  52     <ioreg name="EECR" address="0x1F"/>
  53     <ioreg name="EEDR" address="0x20"/>
  54     <ioreg name="EEARL" address="0x21"/>
  55     <ioreg name="EEARH" address="0x22"/>
  56     <ioreg name="GTCCR" address="0x23"/>
  57     <ioreg name="TCCR0A" address="0x24"/>
  58     <ioreg name="TCCR0B" address="0x25"/>
  59     <ioreg name="TCNT0" address="0x26"/>
  60     <ioreg name="OCR0A" address="0x27"/>
  61     <ioreg name="OCR0B" address="0x28"/>
  62     <ioreg name="GPIOR1" address="0x2A"/>
  63     <ioreg name="GPIOR2" address="0x2B"/>
  64     <ioreg name="OCDR" address="0x31"/>
  65     <ioreg name="SMCR" address="0x33"/>
  66     <ioreg name="MCUSR" address="0x34"/>
  67     <ioreg name="MCUCR" address="0x35"/>
  68     <ioreg name="SPMCSR" address="0x37"/>
  69     <ioreg name="SPL" address="0x3D"/>
  70     <ioreg name="SPH" address="0x3E"/>
  71     <ioreg name="SREG" address="0x3F"/>
  72     <ioreg name="WDTCSR" address="0x60"/>
  73     <ioreg name="WUTCSR" address="0x62"/>
  74     <ioreg name="PRR0" address="0x64"/>
  75     <ioreg name="FOSCCAL" address="0x66"/>
  76     <ioreg name="PCICR" address="0x68"/>
  77     <ioreg name="EICRA" address="0x69"/>
  78     <ioreg name="PCMSK0" address="0x6B"/>
  79     <ioreg name="PCMSK1" address="0x6C"/>
  80     <ioreg name="TIMSK0" address="0x6E"/>
  81     <ioreg name="TIMSK1" address="0x6F"/>
  82     <ioreg name="VADCL" address="0x78"/>
  83     <ioreg name="VADCH" address="0x79"/>
  84     <ioreg name="VADCSR" address="0x7A"/>
  85     <ioreg name="VADMUX" address="0x7C"/>
  86     <ioreg name="DIDR0" address="0x7E"/>
  87     <ioreg name="TCCR1B" address="0x81"/>
  88     <ioreg name="TCNT1L" address="0x84"/>
  89     <ioreg name="TCNT1H" address="0x85"/>
  90     <ioreg name="OCR1AL" address="0x88"/>
  91     <ioreg name="OCR1AH" address="0x89"/>
  92     <ioreg name="TWBR" address="0xB8"/>
  93     <ioreg name="TWSR" address="0xB9"/>
  94     <ioreg name="TWAR" address="0xBA"/>
  95     <ioreg name="TWDR" address="0xBB"/>
  96     <ioreg name="TWCR" address="0xBC"/>
  97     <ioreg name="TWAMR" address="0xBD"/>
  98     <ioreg name="TWBCSR" address="0xBE"/>
  99     <ioreg name="CCSR" address="0xC0"/>
 100     <ioreg name="BGCCR" address="0xD0"/>
 101     <ioreg name="BGCRR" address="0xD1"/>
 102     <ioreg name="CADAC0" address="0xE0"/>
 103     <ioreg name="CADAC1" address="0xE1"/>
 104     <ioreg name="CADAC2" address="0xE2"/>
 105     <ioreg name="CADAC3" address="0xE3"/>
 106     <ioreg name="CADCSRA" address="0xE4"/>
 107     <ioreg name="CADCSRB" address="0xE5"/>
 108     <ioreg name="CADRCC" address="0xE6"/>
 109     <ioreg name="CADRDC" address="0xE7"/>
 110     <ioreg name="CADICL" address="0xE8"/>
 111     <ioreg name="CADICH" address="0xE9"/>
 112     <ioreg name="FCSR" address="0xF0"/>
 113     <ioreg name="CBCR" address="0xF1"/>
 114     <ioreg name="BPIR" address="0xF2"/>
 115     <ioreg name="BPDUV" address="0xF3"/>
 116     <ioreg name="BPSCD" address="0xF4"/>
 117     <ioreg name="BPOCD" address="0xF5"/>
 118     <ioreg name="CBPTR" address="0xF6"/>
 119     <ioreg name="BPCR" address="0xF7"/>
 120     <ioreg name="BPPLR" address="0xF8"/>
 121   </ioregisters>
 122   <packages/>
 123   <hardware>
 124 <!--Everything after this needs editing!!!-->
 125     <module class="FUSE">
 126       <registers name="FUSE" memspace="FUSE">
 127           <reg size="1" name="HIGH" offset="0x01">
 128             <bitfield name="OCDEN" mask="0x02" text="On-Chip Debug Enabled" icon=""/>
 129             <bitfield name="JTAGEN" mask="0x01" text="JTAG Interface Enabled" icon=""/>
 130           </reg>
 131           <reg size="1" name="LOW" offset="0x00">
 132             <bitfield name="WDTON" mask="0x80" text="Watchdog timer always on" icon=""/>
 133             <bitfield name="EESAVE" mask="0x40" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 134             <bitfield name="BOOTSZ" mask="0x30" text="Select boot size" icon="" enum="ENUM_BOOTSZ"/>
 135             <bitfield name="BOOTRST" mask="0x08" text="Boot Reset vector Enabled" icon=""/>
 136             <bitfield name="SUT_CKSEL" mask="0x07" text="Clock Selection" icon="" enum="ENUM_SUT_CKSEL"/>
 137           </reg>
 138         </registers>
 139     </module>
 140     <module class="LOCKBIT">
 141       <registers name="LOCKBIT" memspace="LOCKBIT">
 142           <reg size="1" name="LOCKBIT" offset="0x00">
 143             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 144             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 145             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 146           </reg>
 147         </registers>
 148     </module>
 149     <module class="AD_CONVERTER">
 150       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 151           <reg size="1" name="VADMUX" offset="0x7C" text="The VADC multiplexer Selection Register" icon="io_analo.bmp">
 152             <bitfield name="VADMUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 153           </reg>
 154           <reg size="2" name="VADC" offset="0x78" text="VADC Data Register  Bytes" icon="io_analo.bmp" mask="0x0FFF"/>
 155           <reg size="1" name="VADCSR" offset="0x7A" text="The VADC Control and Status register" icon="io_flag.bmp">
 156             <bitfield name="VADEN" mask="0x08" text="VADC Enable" icon=""/>
 157             <bitfield name="VADSC" mask="0x04" text="VADC Satrt Conversion" icon=""/>
 158             <bitfield name="VADCCIF" mask="0x02" text="VADC Conversion Complete Interrupt Flag" icon=""/>
 159             <bitfield name="VADCCIE" mask="0x01" text="VADC Conversion Complete Interrupt Enable" icon=""/>
 160           </reg>
 161         </registers>
 162     </module>
 163     <module class="EXTERNAL_INTERRUPT">
 164       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 165           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register" icon="io_flag.bmp">
 166             <bitfield name="ISC3" mask="0xC0" text="External Interrupt Sense Control 3 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 167             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control 2 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 168             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 169             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 170           </reg>
 171           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 172             <bitfield name="INT" mask="0x0F" text="External Interrupt Request 1 Enable" icon=""/>
 173           </reg>
 174           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 175             <bitfield name="INTF" mask="0x0F" text="External Interrupt Flags" icon=""/>
 176           </reg>
 177           <reg size="1" name="PCICR" offset="0x68" text="Pin Change Interrupt Control Register" icon="io_flag.bmp">
 178             <bitfield name="PCIE" mask="0x03" text="Pin Change Interrupt Enables" icon=""/>
 179           </reg>
 180           <reg size="1" name="PCIFR" offset="0x3B" text="Pin Change Interrupt Flag Register" icon="io_flag.bmp">
 181             <bitfield name="PCIF" mask="0x03" text="Pin Change Interrupt Flags" icon=""/>
 182           </reg>
 183           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Enable Mask Register 1" icon="io_flag.bmp" mask="0xFF"/>
 184           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Enable Mask Register 0" icon="io_flag.bmp" mask="0xFF"/>
 185         </registers>
 186     </module>
 187     <module class="TIMER_COUNTER_1">
 188       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 189           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 190             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter on Compare Match" icon=""/>
 191             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT"/>
 192           </reg>
 193           <reg size="2" name="TCNT1" offset="0x84" text="Timer Counter 1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 194           <reg size="1" name="OCR1AL" offset="0x88" text="Output Compare Register 1A Low byte" icon="io_flag.bmp" mask="0xFF"/>
 195           <reg size="1" name="OCR1AH" offset="0x89" text="Output Compare Register 1A High byte" icon="io_flag.bmp" mask="0xFF"/>
 196           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 197             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare Interrupt Enable" icon=""/>
 198             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 199           </reg>
 200           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 201             <bitfield name="OCF1A" mask="0x02" text="Timer/Counter1 Output Compare Flag A" icon=""/>
 202             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 203           </reg>
 204           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 205             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 206             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset" icon=""/>
 207           </reg>
 208         </registers>
 209     </module>
 210     <module class="WAKEUP_TIMER">
 211       <registers name="WAKEUP_TIMER" memspace="DATAMEM" text="" icon="io_timer.bmp">
 212           <reg size="1" name="WUTCSR" offset="0x62" text="Wake-up Timer Control Register" icon="io_flag.bmp">
 213             <bitfield name="WUTIF" mask="0x80" text="Wake-up Timer Interrupt Flag" icon=""/>
 214             <bitfield name="WUTIE" mask="0x40" text="Wake-up Timer Interrupt Enable" icon=""/>
 215             <bitfield name="WUTCF" mask="0x20" text="Wake-up timer Calibration Flag" icon=""/>
 216             <bitfield name="WUTR" mask="0x10" text="Wake-up Timer Reset" icon=""/>
 217             <bitfield name="WUTE" mask="0x08" text="Wake-up Timer Enable" icon=""/>
 218             <bitfield name="WUTP" mask="0x07" text="Wake-up Timer Prescaler Bits" icon="" enum="CLK_SEL_3BIT_ONLY_PRESCALE"/>
 219           </reg>
 220         </registers>
 221     </module>
 222     <module class="BATTERY_PROTECTION">
 223       <registers name="BATTERY_PROTECTION" memspace="DATAMEM" text="" icon="io_analo.bmp">
 224           <reg size="1" name="BPPLR" offset="0xF8" text="Battery Protection Parameter Lock Register" icon="io_analo.bmp">
 225             <bitfield name="BPPLE" mask="0x02" text="Battery Protection Parameter Lock Enable" icon=""/>
 226             <bitfield name="BPPL" mask="0x01" text="Battery Protection Parameter Lock" icon=""/>
 227           </reg>
 228           <reg size="1" name="BPCR" offset="0xF7" text="Battery Protection Control Register" icon="io_analo.bmp">
 229             <bitfield name="DUVD" mask="0x08" text="" icon=""/>
 230             <bitfield name="SCD" mask="0x04" text="" icon=""/>
 231             <bitfield name="DCD" mask="0x02" text="" icon=""/>
 232             <bitfield name="CCD" mask="0x01" text="" icon=""/>
 233           </reg>
 234           <reg size="1" name="CBPTR" offset="0xF6" text="Current Battery Protection Timing Register" icon="io_analo.bmp">
 235             <bitfield name="SCPT" mask="0xF0" text="" icon="" enum="BAT_SHORT_CIRC_DELAY"/>
 236             <bitfield name="OCPT" mask="0x0F" text="" icon="" enum="BAT_OVER_CURRENT_DELAY"/>
 237           </reg>
 238           <reg size="1" name="BPOCD" offset="0xF5" text="Battery Protection OverCurrent Detection Level Register" icon="io_analo.bmp">
 239             <bitfield name="DCDL" mask="0xF0" text="" icon="" enum="BAT_VOLT_SENSE"/>
 240             <bitfield name="CCDL" mask="0x0F" text="" icon="" enum="BAT_VOLT_SENSE"/>
 241           </reg>
 242           <reg size="1" name="BPSCD" offset="0xF4" text="Battery Protection Short-Circuit Detection Level Register" icon="io_analo.bmp">
 243             <bitfield name="SCDL" mask="0x0F" text="" icon="" enum="BAT_VOLT_SENSE2"/>
 244           </reg>
 245           <reg size="1" name="BPDUV" offset="0xF3" text="Battery Protection Deep Under Voltage Register" icon="io_analo.bmp">
 246             <bitfield name="DUVT" mask="0x30" text="" icon="" enum="BAT_DEEP_UNDER_DELAY"/>
 247             <bitfield name="DUDL" mask="0x0F" text="" icon="" enum="BAT_DEEP_UNDER_LEVEL"/>
 248           </reg>
 249           <reg size="1" name="BPIR" offset="0xF2" text="Battery Protection Interrupt Register" icon="io_analo.bmp">
 250             <bitfield name="DUVIF" mask="0x80" text="Deep Under-voltage Early Warning Interrupt Flag" icon=""/>
 251             <bitfield name="COCIF" mask="0x40" text="Charge Over-current Protection Activated Interrupt Flag" icon=""/>
 252             <bitfield name="DOCIF" mask="0x20" text="" icon=""/>
 253             <bitfield name="SCIF" mask="0x10" text="" icon=""/>
 254             <bitfield name="DUVIE" mask="0x08" text="Deep Under-voltage Early Warning Interrupt Enable" icon=""/>
 255             <bitfield name="COCIE" mask="0x04" text="" icon=""/>
 256             <bitfield name="DOCIE" mask="0x02" text="" icon=""/>
 257             <bitfield name="SCIE" mask="0x01" text="" icon=""/>
 258           </reg>
 259         </registers>
 260     </module>
 261     <module class="FET">
 262       <registers name="FET" memspace="DATAMEM" text="" icon="io_analo.bmp">
 263           <reg size="1" name="FCSR" offset="0xF0" text="" icon="io_analo.bmp">
 264             <bitfield name="PWMOC" mask="0x20" text="Pulse Width Modulation of OC output" icon=""/>
 265             <bitfield name="PWMOPC" mask="0x10" text="Pulse Width Modulation Modulation of OPC output" icon=""/>
 266             <bitfield name="CPS" mask="0x08" text="Current Protection Status" icon=""/>
 267             <bitfield name="DFE" mask="0x04" text="Discharge FET Enable" icon=""/>
 268             <bitfield name="CFE" mask="0x02" text="Charge FET Enable" icon=""/>
 269             <bitfield name="PFD" mask="0x01" text="Precharge FET disable" icon=""/>
 270           </reg>
 271         </registers>
 272     </module>
 273     <module class="COULOMB_COUNTER">
 274       <registers name="COULOMB_COUNTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 275           <reg size="1" name="CADCSRA" offset="0xE4" text="CC-ADC Control and Status Register A" icon="io_analo.bmp">
 276             <bitfield name="CADEN" mask="0x80" text="When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled." icon=""/>
 277             <bitfield name="CADUB" mask="0x20" text="CC_ADC Update Busy" icon=""/>
 278             <bitfield name="CADAS" mask="0x18" text="CC_ADC Accumulate Current Select Bits" icon="" enum="ANALOG_CADA_ACC_TIME"/>
 279             <bitfield name="CADSI" mask="0x06" text="The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined." icon="" enum="ANALOG_CADA_ACC_TIME"/>
 280             <bitfield name="CADSE" mask="0x01" text="When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode." icon=""/>
 281           </reg>
 282           <reg size="1" name="CADCSRB" offset="0xE5" text="CC-ADC Control and Status Register B" icon="io_analo.bmp">
 283             <bitfield name="CADACIE" mask="0x40" text="" icon=""/>
 284             <bitfield name="CADRCIE" mask="0x20" text="Regular Current Interrupt Enable" icon=""/>
 285             <bitfield name="CADICIE" mask="0x10" text="CAD Instantenous Current Interrupt Enable" icon=""/>
 286             <bitfield name="CADACIF" mask="0x04" text="CC-ADC Accumulate Current Interrupt Flag" icon=""/>
 287             <bitfield name="CADRCIF" mask="0x02" text="CC-ADC Accumulate Current Interrupt Flag" icon=""/>
 288             <bitfield name="CADICIF" mask="0x01" text="CC-ADC Instantaneous Current Interrupt Flag" icon=""/>
 289           </reg>
 290           <reg size="2" name="CADIC" offset="0xE8" text="CC-ADC Instantaneous Current" icon="io_analo.bmp" mask="0xFFFF"/>
 291           <reg size="1" name="CADAC3" offset="0xE3" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 292           <reg size="1" name="CADAC2" offset="0xE2" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 293           <reg size="1" name="CADAC1" offset="0xE1" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 294           <reg size="1" name="CADAC0" offset="0xE0" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 295           <reg size="1" name="CADRCC" offset="0xE6" text="CC-ADC Regular Charge Current" icon="io_analo.bmp" mask="0xFF"/>
 296           <reg size="1" name="CADRDC" offset="0xE7" text="CC-ADC Regular Discharge Current" icon="io_analo.bmp" mask="0xFF"/>
 297         </registers>
 298     </module>
 299     <module class="CELL_BALANCING">
 300       <registers name="CELL_BALANCING" memspace="DATAMEM" text="" icon="io_analo.bmp">
 301           <reg size="1" name="CBCR" offset="0xF1" text="Cell Balancing Control Register" icon="io_analo.bmp">
 302             <bitfield name="CBE" mask="0x0F" text="Cell Balancing Enables" icon="" lsb="1"/>
 303           </reg>
 304         </registers>
 305     </module>
 306     <module class="CPU">
 307       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 308           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 309             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 310             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 311             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 312             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 313             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 314             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 315             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 316             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 317           </reg>
 318           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 319           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 320             <bitfield name="JTD" mask="0x80" text="JTAG Disable" icon=""/>
 321             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 322             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 323             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 324           </reg>
 325           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 326             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 327             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 328             <bitfield name="BODRF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 329             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 330             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 331           </reg>
 332           <reg size="1" name="FOSCCAL" offset="0x66" text="Fast Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 333           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 334             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS3"/>
 335             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 336           </reg>
 337           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp" mask="0xFF"/>
 338           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp" mask="0xFF"/>
 339           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp" mask="0xFF"/>
 340           <reg size="1" name="CCSR" offset="0xC0" text="Clock Control and Status Register" icon="io_cpu.bmp">
 341             <bitfield name="XOE" mask="0x02" text="32 kHz Crystal Oscillator Enable" icon=""/>
 342             <bitfield name="ACS" mask="0x01" text="Asynchronous Clock Select" icon=""/>
 343           </reg>
 344           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register" icon="io_cpu.bmp" mask="0x0F"/>
 345           <reg size="1" name="PRR0" offset="0x64" text="Power Reduction Register 0" icon="io_cpu.bmp">
 346             <bitfield name="PRTWI" mask="0x08" text="Power Reduction TWI" icon=""/>
 347             <bitfield name="PRTIM1" mask="0x04" text="Power Reduction Timer/Counter1" icon=""/>
 348             <bitfield name="PRTIM0" mask="0x02" text="Power Reduction Timer/Counter0" icon=""/>
 349             <bitfield name="PRVADC" mask="0x01" text="Power Reduction V-ADC" icon=""/>
 350           </reg>
 351         </registers>
 352     </module>
 353     <module class="WATCHDOG">
 354       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 355           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 356             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 357             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 358             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 359             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 360             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 361           </reg>
 362         </registers>
 363     </module>
 364     <module class="TIMER_COUNTER_0">
 365       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 366           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 367             <bitfield name="COM0A" mask="0xC0" text="Force Output Compare" icon=""/>
 368             <bitfield name="COM0B" mask="0x30" text="" icon=""/>
 369             <bitfield name="WGM0" mask="0x03" text="Clock Select0 bits" icon=""/>
 370           </reg>
 371           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 372             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare" icon=""/>
 373             <bitfield name="FOC0B" mask="0x40" text="Waveform Generation Mode" icon=""/>
 374             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 375             <bitfield name="CS0" mask="0x07" text="Clock Select0 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 376           </reg>
 377           <reg size="1" name="TCNT0" offset="0x46" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 378           <reg size="1" name="OCR0A" offset="0x47" text="Output compare Register A" icon="io_flag.bmp">
 379             <bitfield name="OCR0A" mask="0xFF" text="" icon=""/>
 380           </reg>
 381           <reg size="1" name="OCR0B" offset="0x48" text="Output compare Register B" icon="io_flag.bmp">
 382             <bitfield name="OCR0B" mask="0xFF" text="" icon=""/>
 383           </reg>
 384           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 385             <bitfield name="OCIE0B" mask="0x04" text="Output Compare Interrupt Enable" icon=""/>
 386             <bitfield name="OCIE0A" mask="0x02" text="Output Compare Interrupt Enable" icon=""/>
 387             <bitfield name="TOIE0" mask="0x01" text="Overflow Interrupt Enable" icon=""/>
 388           </reg>
 389           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 390             <bitfield name="OCF0B" mask="0x04" text="Output Compare Flag" icon=""/>
 391             <bitfield name="OCF0A" mask="0x02" text="Output Compare Flag" icon=""/>
 392             <bitfield name="TOV0" mask="0x01" text="Overflow Flag" icon=""/>
 393           </reg>
 394         </registers>
 395     </module>
 396     <module class="PORTA">
 397       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 398           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 399           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 400           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 401         </registers>
 402     </module>
 403     <module class="PORTB">
 404       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 405           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 406           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 407           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 408         </registers>
 409     </module>
 410     <module class="PORTC">
 411       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 412           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0x01"/>
 413         </registers>
 414     </module>
 415     <module class="PORTD">
 416       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 417           <reg size="1" name="PORTD" offset="0x2B" text="Data Register, Port D" icon="io_port.bmp" mask="0x03"/>
 418           <reg size="1" name="DDRD" offset="0x2A" text="Data Direction Register, Port D" icon="io_flag.bmp" mask="0x03"/>
 419           <reg size="1" name="PIND" offset="0x29" text="Input Pins, Port D" icon="io_port.bmp" mask="0x03"/>
 420         </registers>
 421     </module>
 422     <module class="BOOT_LOAD">
 423       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 424           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 425             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 426             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 427             <bitfield name="SIGRD" mask="0x20" text="Signature Row Read" icon=""/>
 428             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 429             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 430             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 431             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 432             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 433           </reg>
 434         </registers>
 435     </module>
 436     <module class="TWI">
 437       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 438           <reg size="1" name="TWBCSR" offset="0xBE" text="TWI Bus Control and Status Register" icon="io_com.bmp">
 439             <bitfield name="TWBCIF" mask="0x80" text="TWI Bus Connect/Disconnect Interrupt Flag" icon=""/>
 440             <bitfield name="TWBCIE" mask="0x40" text="TWI Bus Connect/Disconnect Interrupt Enable" icon=""/>
 441             <bitfield name="TWBDT" mask="0x06" text="TWI Bus Disconnect Time-out Period" icon="" enum="COMM_TW_BUS_TIMEOUT"/>
 442             <bitfield name="TWBCIP" mask="0x01" text="TWI Bus Connect/Disconnect Interrupt Polarity" icon=""/>
 443           </reg>
 444           <reg size="1" name="TWAMR" offset="0xBD" text="TWI (Slave) Address Mask Register" icon="io_com.bmp">
 445             <bitfield name="TWAM" mask="0xFE" text="" icon=""/>
 446           </reg>
 447           <reg size="1" name="TWBR" offset="0xB8" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 448           <reg size="1" name="TWCR" offset="0xBC" text="TWI Control Register" icon="io_flag.bmp">
 449             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 450             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 451             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 452             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 453             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 454             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 455             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 456           </reg>
 457           <reg size="1" name="TWSR" offset="0xB9" text="TWI Status Register" icon="io_flag.bmp">
 458             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 459             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 460           </reg>
 461           <reg size="1" name="TWDR" offset="0xBB" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 462           <reg size="1" name="TWAR" offset="0xBA" text="TWI (Slave) Address register" icon="io_com.bmp">
 463             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 464             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 465           </reg>
 466         </registers>
 467     </module>
 468     <module class="BANDGAP">
 469       <registers name="BANDGAP" memspace="DATAMEM" text="" icon="io_analo.bmp">
 470           <reg size="1" name="BGCRR" offset="0xD1" text="Bandgap Calibration of Resistor Ladder" icon="io_analo.bmp" mask="0xFF"/>
 471           <reg size="1" name="BGCCR" offset="0xD0" text="Bandgap Calibration Register" icon="io_analo.bmp">
 472             <bitfield name="BGD" mask="0x80" text="Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled." icon=""/>
 473             <bitfield name="BGCC" mask="0x3F" text="BG Calibration of PTAT Current Bits" icon=""/>
 474           </reg>
 475         </registers>
 476     </module>
 477     <module class="EEPROM">
 478       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 479           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 480           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 481           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 482             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 483             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 484             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Programming Enable" icon=""/>
 485             <bitfield name="EEPE" mask="0x02" text="EEPROM Programming Enable" icon=""/>
 486             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 487           </reg>
 488         </registers>
 489     </module>
 490   </hardware>
 491 </device>