devices/atmega3290p

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="25">
   5     <interrupt vector="1" address="$000" name="RESET">External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.     </interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$004" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$006" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1 COMPB">Timer/Counter Compare Match B</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
  18     <interrupt vector="14" address="$01A" name="USART, RX">USART, Rx Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="USART, UDRE">USART Data register Empty</interrupt>
  20     <interrupt vector="16" address="$01E" name="USART0, TX">USART0, Tx Complete</interrupt>
  21     <interrupt vector="17" address="$020" name="USI START">USI Start Condition</interrupt>
  22     <interrupt vector="18" address="$022" name="USI OVERFLOW">USI Overflow</interrupt>
  23     <interrupt vector="19" address="$024" name="ANALOG COMP">Analog Comparator</interrupt>
  24     <interrupt vector="20" address="$026" name="ADC">ADC Conversion Complete</interrupt>
  25     <interrupt vector="21" address="$028" name="EE_READY">EEPROM Ready</interrupt>
  26     <interrupt vector="22" address="$02A" name="SPM_READY">Store Program Memory Read</interrupt>
  27     <interrupt vector="23" address="$02C" name="LCD">LCD Start of Frame</interrupt>
  28     <interrupt vector="24" address="$02E" name="PCINT2">Pin Change Interrupt Request 2</interrupt>
  29     <interrupt vector="25" address="$030" name="PCINT3">Pin Change Interrupt Request 3</interrupt>
  30   </interrupts>
  31   <packages>
  32     <package name="TQFP" pins="100">
  33       <pin id="1" name=""/>
  34       <pin id="2" name=""/>
  35       <pin id="3" name=""/>
  36       <pin id="4" name=""/>
  37       <pin id="5" name=""/>
  38       <pin id="6" name=""/>
  39       <pin id="7" name=""/>
  40       <pin id="8" name=""/>
  41       <pin id="9" name=""/>
  42       <pin id="10" name=""/>
  43       <pin id="11" name=""/>
  44       <pin id="12" name=""/>
  45       <pin id="13" name=""/>
  46       <pin id="14" name=""/>
  47       <pin id="15" name=""/>
  48       <pin id="16" name=""/>
  49       <pin id="17" name=""/>
  50       <pin id="18" name=""/>
  51       <pin id="19" name=""/>
  52       <pin id="20" name=""/>
  53       <pin id="21" name=""/>
  54       <pin id="22" name=""/>
  55       <pin id="23" name=""/>
  56       <pin id="24" name=""/>
  57       <pin id="25" name=""/>
  58       <pin id="26" name=""/>
  59       <pin id="27" name=""/>
  60       <pin id="28" name=""/>
  61       <pin id="29" name=""/>
  62       <pin id="30" name=""/>
  63       <pin id="31" name=""/>
  64       <pin id="32" name=""/>
  65       <pin id="33" name=""/>
  66       <pin id="34" name=""/>
  67       <pin id="35" name=""/>
  68       <pin id="36" name=""/>
  69       <pin id="37" name=""/>
  70       <pin id="38" name=""/>
  71       <pin id="39" name=""/>
  72       <pin id="40" name=""/>
  73       <pin id="41" name=""/>
  74       <pin id="42" name=""/>
  75       <pin id="43" name=""/>
  76       <pin id="44" name=""/>
  77       <pin id="45" name=""/>
  78       <pin id="46" name=""/>
  79       <pin id="47" name=""/>
  80       <pin id="48" name=""/>
  81       <pin id="49" name=""/>
  82       <pin id="50" name=""/>
  83       <pin id="51" name=""/>
  84       <pin id="52" name=""/>
  85       <pin id="53" name=""/>
  86       <pin id="54" name=""/>
  87       <pin id="55" name=""/>
  88       <pin id="56" name=""/>
  89       <pin id="57" name=""/>
  90       <pin id="58" name=""/>
  91       <pin id="59" name=""/>
  92       <pin id="60" name=""/>
  93       <pin id="61" name=""/>
  94       <pin id="62" name=""/>
  95       <pin id="63" name=""/>
  96       <pin id="64" name=""/>
  97       <pin id="65" name=""/>
  98       <pin id="66" name=""/>
  99       <pin id="67" name=""/>
 100       <pin id="68" name=""/>
 101       <pin id="69" name=""/>
 102       <pin id="70" name=""/>
 103       <pin id="71" name=""/>
 104       <pin id="72" name=""/>
 105       <pin id="73" name=""/>
 106       <pin id="74" name=""/>
 107       <pin id="75" name=""/>
 108       <pin id="76" name=""/>
 109       <pin id="77" name=""/>
 110       <pin id="78" name=""/>
 111       <pin id="79" name=""/>
 112       <pin id="80" name=""/>
 113       <pin id="81" name=""/>
 114       <pin id="82" name=""/>
 115       <pin id="83" name=""/>
 116       <pin id="84" name=""/>
 117       <pin id="85" name=""/>
 118       <pin id="86" name=""/>
 119       <pin id="87" name=""/>
 120       <pin id="88" name=""/>
 121       <pin id="89" name=""/>
 122       <pin id="90" name=""/>
 123       <pin id="91" name=""/>
 124       <pin id="92" name=""/>
 125       <pin id="93" name=""/>
 126       <pin id="94" name=""/>
 127       <pin id="95" name=""/>
 128       <pin id="96" name=""/>
 129       <pin id="97" name=""/>
 130       <pin id="98" name=""/>
 131       <pin id="99" name=""/>
 132       <pin id="100" name=""/>
 133     </package>
 134   </packages>
 135   <memory>
 136     <flash size="32768"/>
 137     <iospace start="$20" stop="$FF"/>
 138     <sram size="2048"/>
 139     <eram size="0"/>
 140   </memory>
 141   <ioregisters>
 142     <ioreg name="PINA" address="$00"/>
 143     <ioreg name="DDRA" address="$01"/>
 144     <ioreg name="PORTA" address="$02"/>
 145     <ioreg name="PINB" address="$03"/>
 146     <ioreg name="DDRB" address="$04"/>
 147     <ioreg name="PORTB" address="$05"/>
 148     <ioreg name="PINC" address="$06"/>
 149     <ioreg name="DDRC" address="$07"/>
 150     <ioreg name="PORTC" address="$08"/>
 151     <ioreg name="PIND" address="$09"/>
 152     <ioreg name="DDRD" address="$0A"/>
 153     <ioreg name="PORTD" address="$0B"/>
 154     <ioreg name="PINE" address="$0C"/>
 155     <ioreg name="DDRE" address="$0D"/>
 156     <ioreg name="PORTE" address="$0E"/>
 157     <ioreg name="PINF" address="$0F"/>
 158     <ioreg name="DDRF" address="$10"/>
 159     <ioreg name="PORTF" address="$11"/>
 160     <ioreg name="PING" address="$12"/>
 161     <ioreg name="DDRG" address="$13"/>
 162     <ioreg name="PORTG" address="$14"/>
 163     <ioreg name="TIFR0" address="$15"/>
 164     <ioreg name="TIFR1" address="$16"/>
 165     <ioreg name="TIFR2" address="$17"/>
 166     <ioreg name="EIFR" address="$1C"/>
 167     <ioreg name="EIMSK" address="$1D"/>
 168     <ioreg name="GPIOR0" address="$1E"/>
 169     <ioreg name="EECR" address="$1F"/>
 170     <ioreg name="EEDR" address="$20"/>
 171     <ioreg name="EEARL" address="$21"/>
 172     <ioreg name="EEARH" address="$22"/>
 173     <ioreg name="GTCCR" address="$23"/>
 174     <ioreg name="TCCR0A" address="$24"/>
 175     <ioreg name="TCNT0" address="$26"/>
 176     <ioreg name="OCR0A" address="$27"/>
 177     <ioreg name="GPIOR1" address="$2A"/>
 178     <ioreg name="GPIOR2" address="$2B"/>
 179     <ioreg name="SPCR" address="$2C"/>
 180     <ioreg name="SPSR" address="$2D"/>
 181     <ioreg name="SPDR" address="$2E"/>
 182     <ioreg name="ACSR" address="$30"/>
 183     <ioreg name="OCDR" address="$31"/>
 184     <ioreg name="SMCR" address="$33"/>
 185     <ioreg name="MCUSR" address="$34"/>
 186     <ioreg name="MCUCR" address="$35"/>
 187     <ioreg name="SPMCSR" address="$37"/>
 188     <ioreg name="SPL" address="$3D"/>
 189     <ioreg name="SPH" address="$3E"/>
 190     <ioreg name="SREG" address="$3F"/>
 191     <ioreg name="WDTCR" address="$60"/>
 192     <ioreg name="CLKPR" address="$61"/>
 193     <ioreg name="PRR" address="$64"/>
 194     <ioreg name="OSCCAL" address="$66"/>
 195     <ioreg name="EICRA" address="$69"/>
 196     <ioreg name="PCMSK0" address="$6B"/>
 197     <ioreg name="PCMSK1" address="$6C"/>
 198     <ioreg name="PCMSK2" address="$6D"/>
 199     <ioreg name="TIMSK0" address="$6E"/>
 200     <ioreg name="TIMSK1" address="$6F"/>
 201     <ioreg name="TIMSK2" address="$70"/>
 202     <ioreg name="PCMSK3" address="$73"/>
 203     <ioreg name="ADCL" address="$78"/>
 204     <ioreg name="ADCH" address="$79"/>
 205     <ioreg name="ADCSRA" address="$7A"/>
 206     <ioreg name="ADCSRB" address="$7B"/>
 207     <ioreg name="ADMUX" address="$7C"/>
 208     <ioreg name="DIDR0" address="$7E"/>
 209     <ioreg name="DIDR1" address="$7F"/>
 210     <ioreg name="TCCR1A" address="$80"/>
 211     <ioreg name="TCCR1B" address="$81"/>
 212     <ioreg name="TCCR1C" address="$82"/>
 213     <ioreg name="TCNT1L" address="$84"/>
 214     <ioreg name="TCNT1H" address="$85"/>
 215     <ioreg name="ICR1L" address="$86"/>
 216     <ioreg name="ICR1H" address="$87"/>
 217     <ioreg name="OCR1AL" address="$88"/>
 218     <ioreg name="OCR1AH" address="$89"/>
 219     <ioreg name="OCR1BL" address="$8A"/>
 220     <ioreg name="OCR1BH" address="$8B"/>
 221     <ioreg name="TCCR2A" address="$B0"/>
 222     <ioreg name="TCNT2" address="$B2"/>
 223     <ioreg name="OCR2A" address="$B3"/>
 224     <ioreg name="ASSR" address="$B6"/>
 225     <ioreg name="USICR" address="$B8"/>
 226     <ioreg name="USISR" address="$B9"/>
 227     <ioreg name="USIDR" address="$BA"/>
 228     <ioreg name="UCSR0A" address="$C0"/>
 229     <ioreg name="UCSR0B" address="$C1"/>
 230     <ioreg name="UCSR0C" address="$C2"/>
 231     <ioreg name="UBRR0L" address="$C4"/>
 232     <ioreg name="UBRR0H" address="$C5"/>
 233     <ioreg name="UDR0" address="$C6"/>
 234     <ioreg name="PINH" address="$D8"/>
 235     <ioreg name="DDRH" address="$D9"/>
 236     <ioreg name="PORTH" address="$DA"/>
 237     <ioreg name="PINJ" address="$DB"/>
 238     <ioreg name="DDRJ" address="$DC"/>
 239     <ioreg name="PORTJ" address="$DD"/>
 240     <ioreg name="LCDCRA" address="$E4"/>
 241     <ioreg name="LCDCRB" address="$E5"/>
 242     <ioreg name="LCDFRR" address="$E6"/>
 243     <ioreg name="LCDCCR" address="$E7"/>
 244     <ioreg name="LCDDR0" address="$EC"/>
 245     <ioreg name="LCDDR1" address="$ED"/>
 246     <ioreg name="LCDDR2" address="$EE"/>
 247     <ioreg name="LCDDR3" address="$EF"/>
 248     <ioreg name="LCDDR4" address="$F0"/>
 249     <ioreg name="LCDDR5" address="$F1"/>
 250     <ioreg name="LCDDR6" address="$F2"/>
 251     <ioreg name="LCDDR7" address="$F3"/>
 252     <ioreg name="LCDDR8" address="$F4"/>
 253     <ioreg name="LCDDR9" address="$F5"/>
 254     <ioreg name="LCDDR10" address="$F6"/>
 255     <ioreg name="LCDDR11" address="$F7"/>
 256     <ioreg name="LCDDR12" address="$F8"/>
 257     <ioreg name="LCDDR13" address="$F9"/>
 258     <ioreg name="LCDDR14" address="$FA"/>
 259     <ioreg name="LCDDR15" address="$FB"/>
 260     <ioreg name="LCDDR16" address="$FC"/>
 261     <ioreg name="LCDDR17" address="$FD"/>
 262     <ioreg name="LCDDR18" address="$FE"/>
 263     <ioreg name="LCDDR19" address="$FF"/>
 264   </ioregisters>
 265   <hardware>
 266 <!--Everything after this needs editing!!!-->
 267     <module class="FUSE">
 268       <registers name="FUSE" memspace="FUSE">
 269           <reg size="1" name="EXTENDED" offset="0x02">
 270             <bitfield name="BODLEVEL" mask="0x06" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 271             <bitfield name="RSTDISBL" mask="0x01" text="External Reset Disable" icon=""/>
 272           </reg>
 273           <reg size="1" name="HIGH" offset="0x01">
 274             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 275             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 276             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 277             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 278             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM memory through the Chip Erase cycle" icon=""/>
 279             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 280             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 281           </reg>
 282           <reg size="1" name="LOW" offset="0x00">
 283             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 284             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTE7" icon=""/>
 285             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 286           </reg>
 287         </registers>
 288     </module>
 289     <module class="LOCKBIT">
 290       <registers name="LOCKBIT" memspace="LOCKBIT">
 291           <reg size="1" name="LOCKBIT" offset="0x00">
 292             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 293             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 294             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 295           </reg>
 296         </registers>
 297     </module>
 298     <module class="TIMER_COUNTER_0">
 299       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 300           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 301             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare" icon=""/>
 302             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 303             <bitfield name="COM0A" mask="0x30" text="Compare Match Output Modes" icon=""/>
 304             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 305             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 306           </reg>
 307           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 308           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 309           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 310             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt Enable" icon=""/>
 311             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 312           </reg>
 313           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 314             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0" icon=""/>
 315             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 316           </reg>
 317           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Control Register" icon="io_cpu.bmp">
 318             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 319             <bitfield name="PSR310" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 320           </reg>
 321         </registers>
 322     </module>
 323     <module class="TIMER_COUNTER_1">
 324       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 325           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 326             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 327             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 328             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 329           </reg>
 330           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 331             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 332             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 333             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 334             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 335           </reg>
 336           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter 1 Control Register C" icon="io_flag.bmp">
 337             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare 1A" icon=""/>
 338             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare 1B" icon=""/>
 339           </reg>
 340           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 341           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Outbut Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 342           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 343           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 344           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 345             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 346             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 347             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 348             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 349           </reg>
 350           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter1 Interrupt Flag register" icon="io_flag.bmp">
 351             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 352             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 353             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 354             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 355           </reg>
 356         </registers>
 357     </module>
 358     <module class="TIMER_COUNTER_2">
 359       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 360           <reg size="1" name="TCCR2A" offset="0xB0" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 361             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare A" icon=""/>
 362             <bitfield name="WGM20" mask="0x40" text="Waveform Generation Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 363             <bitfield name="COM2A" mask="0x30" text="Compare Output Mode bits" icon=""/>
 364             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 365             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 366           </reg>
 367           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 368           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 369           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter2 Interrupt Mask register" icon="io_flag.bmp">
 370             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 371             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 372           </reg>
 373           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter2 Interrupt Flag Register" icon="io_flag.bmp">
 374             <bitfield name="OCF2A" mask="0x02" text="Timer/Counter2 Output Compare Flag 2" icon=""/>
 375             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 376           </reg>
 377           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_cpu.bmp">
 378             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 379           </reg>
 380           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.bmp">
 381             <bitfield name="EXCLK" mask="0x10" text="Enable External Clock Interrupt" icon=""/>
 382             <bitfield name="AS2" mask="0x08" text="AS2: Asynchronous Timer/Counter2" icon=""/>
 383             <bitfield name="TCN2UB" mask="0x04" text="TCN2UB: Timer/Counter2 Update Busy" icon=""/>
 384             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 385             <bitfield name="TCR2UB" mask="0x01" text="TCR2UB: Timer/Counter Control Register2 Update Busy" icon=""/>
 386           </reg>
 387         </registers>
 388     </module>
 389     <module class="WATCHDOG">
 390       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 391           <reg size="1" name="WDTCR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 392             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 393             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 394             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 395           </reg>
 396         </registers>
 397     </module>
 398     <module class="EEPROM">
 399       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 400           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x03FF"/>
 401           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 402           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 403             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 404             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 405             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 406             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 407           </reg>
 408         </registers>
 409     </module>
 410     <module class="SPI">
 411       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 412           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 413             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 414             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 415             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 416             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 417             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 418             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 419             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 420           </reg>
 421           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 422             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 423             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 424             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 425           </reg>
 426           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 427         </registers>
 428     </module>
 429     <module class="PORTA">
 430       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 431           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 432           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 433           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 434         </registers>
 435     </module>
 436     <module class="PORTB">
 437       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 438           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 439           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 440           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 441         </registers>
 442     </module>
 443     <module class="PORTC">
 444       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 445           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 446           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 447           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 448         </registers>
 449     </module>
 450     <module class="PORTD">
 451       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 452           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 453           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 454           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 455         </registers>
 456     </module>
 457     <module class="ANALOG_COMPARATOR">
 458       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 459           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_flag.bmp">
 460             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 461           </reg>
 462           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 463             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 464             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 465             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 466             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 467             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 468             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 469             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 470           </reg>
 471           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 472             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 473             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 474           </reg>
 475         </registers>
 476     </module>
 477     <module class="PORTE">
 478       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 479           <reg size="1" name="PORTE" offset="0x2E" text="Data Register, Port E" icon="io_port.bmp" mask="0xFF"/>
 480           <reg size="1" name="DDRE" offset="0x2D" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0xFF"/>
 481           <reg size="1" name="PINE" offset="0x2C" text="Input Pins, Port E" icon="io_port.bmp" mask="0xFF"/>
 482         </registers>
 483     </module>
 484     <module class="PORTF">
 485       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 486           <reg size="1" name="PORTF" offset="0x31" text="Data Register, Port F" icon="io_port.bmp" mask="0xFF"/>
 487           <reg size="1" name="DDRF" offset="0x30" text="Data Direction Register, Port F" icon="io_flag.bmp" mask="0xFF"/>
 488           <reg size="1" name="PINF" offset="0x2F" text="Input Pins, Port F" icon="io_port.bmp" mask="0xFF"/>
 489         </registers>
 490     </module>
 491     <module class="PORTG">
 492       <registers name="PORTG" memspace="DATAMEM" text="" icon="io_port.bmp">
 493           <reg size="1" name="PORTG" offset="0x34" text="Port G Data Register" icon="io_port.bmp" mask="0x1F"/>
 494           <reg size="1" name="DDRG" offset="0x33" text="Port G Data Direction Register" icon="io_flag.bmp" mask="0x1F"/>
 495           <reg size="1" name="PING" offset="0x32" text="Port G Input Pins" icon="io_port.bmp" mask="0x3F"/>
 496         </registers>
 497     </module>
 498     <module class="JTAG">
 499       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 500           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp" mask="0xFF"/>
 501           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 502             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 503           </reg>
 504           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 505             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 506           </reg>
 507         </registers>
 508     </module>
 509     <module class="EXTERNAL_INTERRUPT">
 510       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 511           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 512             <bitfield name="ISC01" mask="0x02" text="External Interrupt Sense Control 0 Bit 1" icon=""/>
 513             <bitfield name="ISC00" mask="0x01" text="External Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 514           </reg>
 515           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 516             <bitfield name="PCIE" mask="0xF0" text="Pin Change Interrupt Enables" icon=""/>
 517             <bitfield name="INT0" mask="0x01" text="External Interrupt Request 0 Enable" icon=""/>
 518           </reg>
 519           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 520             <bitfield name="PCIF" mask="0xF0" text="Pin Change Interrupt Flags" icon=""/>
 521             <bitfield name="INTF0" mask="0x01" text="External Interrupt Flag 0" icon=""/>
 522           </reg>
 523           <reg size="1" name="PCMSK3" offset="0x73" text="Pin Change Mask Register 3" icon="io_flag.bmp" mask="0x7F"/>
 524           <reg size="1" name="PCMSK2" offset="0x6D" text="Pin Change Mask Register 2" icon="io_flag.bmp" mask="0xFF"/>
 525           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp" mask="0xFF"/>
 526           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp" mask="0xFF"/>
 527         </registers>
 528     </module>
 529     <module class="USI">
 530       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 531           <reg size="1" name="USIDR" offset="0xBA" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 532           <reg size="1" name="USISR" offset="0xB9" text="USI Status Register" icon="io_flag.bmp">
 533             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 534             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 535             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 536             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 537             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 538           </reg>
 539           <reg size="1" name="USICR" offset="0xB8" text="USI Control Register" icon="io_flag.bmp">
 540             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 541             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 542             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 543             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 544             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 545             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 546           </reg>
 547         </registers>
 548     </module>
 549     <module class="AD_CONVERTER">
 550       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 551           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 552             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF3"/>
 553             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 554             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 555           </reg>
 556           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 557             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 558             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 559             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 560             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 561             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 562             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 563           </reg>
 564           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 565           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp">
 566             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon=""/>
 567           </reg>
 568           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp">
 569             <bitfield name="ADC7D" mask="0x80" text="ADC7 Digital input Disable" icon=""/>
 570             <bitfield name="ADC6D" mask="0x40" text="ADC6 Digital input Disable" icon=""/>
 571             <bitfield name="ADC5D" mask="0x20" text="ADC5 Digital input Disable" icon=""/>
 572             <bitfield name="ADC4D" mask="0x10" text="ADC4 Digital input Disable" icon=""/>
 573             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 574             <bitfield name="ADC2D" mask="0x04" text="ADC2 Digital input Disable" icon=""/>
 575             <bitfield name="ADC1D" mask="0x02" text="ADC1 Digital input Disable" icon=""/>
 576             <bitfield name="ADC0D" mask="0x01" text="ADC0 Digital input Disable" icon=""/>
 577           </reg>
 578         </registers>
 579     </module>
 580     <module class="BOOT_LOAD">
 581       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 582           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 583             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 584             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 585             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 586             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 587             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 588             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 589             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 590           </reg>
 591         </registers>
 592     </module>
 593     <module class="USART0">
 594       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 595           <reg size="1" name="UDR0" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 596           <reg size="1" name="UCSR0A" offset="0xC0" text="USART Control and Status Register A" icon="io_flag.bmp">
 597             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 598             <bitfield name="TXC0" mask="0x40" text="USART Transmit Complete" icon=""/>
 599             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 600             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 601             <bitfield name="DOR0" mask="0x08" text="Data OverRun" icon=""/>
 602             <bitfield name="UPE0" mask="0x04" text="USART Parity Error" icon=""/>
 603             <bitfield name="U2X0" mask="0x02" text="Double the USART Transmission Speed" icon=""/>
 604             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 605           </reg>
 606           <reg size="1" name="UCSR0B" offset="0xC1" text="USART Control and Status Register B" icon="io_flag.bmp">
 607             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 608             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 609             <bitfield name="UDRIE0" mask="0x20" text="USART Data Register Empty Interrupt Enable" icon=""/>
 610             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 611             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 612             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 613             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 614             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 615           </reg>
 616           <reg size="1" name="UCSR0C" offset="0xC2" text="USART Control and Status Register C" icon="io_flag.bmp">
 617             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 618             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 619             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 620             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 621             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 622           </reg>
 623           <reg size="2" name="UBRR0" offset="0xC4" text="USART Baud Rate Register  Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 624         </registers>
 625     </module>
 626     <module class="PORTH">
 627       <registers name="PORTH" memspace="DATAMEM" text="" icon="io_port.bmp">
 628           <reg size="1" name="PORTH" offset="0xDA" text="PORT H Data Register" icon="io_port.bmp" mask="0xFF"/>
 629           <reg size="1" name="DDRH" offset="0xD9" text="PORT H Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 630           <reg size="1" name="PINH" offset="0xD8" text="PORT H Input Pins" icon="io_port.bmp" mask="0xFF"/>
 631         </registers>
 632     </module>
 633     <module class="PORTJ">
 634       <registers name="PORTJ" memspace="DATAMEM" text="" icon="io_port.bmp">
 635           <reg size="1" name="PORTJ" offset="0xDD" text="PORT J Data Register" icon="io_port.bmp" mask="0x7F"/>
 636           <reg size="1" name="DDRJ" offset="0xDC" text="PORT J Data Direction Register" icon="io_flag.bmp" mask="0x7F"/>
 637           <reg size="1" name="PINJ" offset="0xDB" text="PORT J Input Pins" icon="io_port.bmp" mask="0x7F"/>
 638         </registers>
 639     </module>
 640     <module class="LCD">
 641       <registers name="LCD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 642           <reg size="1" name="LCDDR19" offset="0xFF" text="LCD Data Register 19" icon="io_flag.bmp" mask="0xFF"/>
 643           <reg size="1" name="LCDDR18" offset="0xFE" text="LCD Data Register 18" icon="io_flag.bmp" mask="0xFF"/>
 644           <reg size="1" name="LCDDR17" offset="0xFD" text="LCD Data Register 17" icon="io_flag.bmp" mask="0xFF"/>
 645           <reg size="1" name="LCDDR16" offset="0xFC" text="LCD Data Register 16" icon="io_flag.bmp" mask="0xFF"/>
 646           <reg size="1" name="LCDDR15" offset="0xFB" text="LCD Data Register 15" icon="io_flag.bmp" mask="0xFF"/>
 647           <reg size="1" name="LCDDR14" offset="0xFA" text="LCD Data Register 14" icon="io_flag.bmp" mask="0xFF"/>
 648           <reg size="1" name="LCDDR13" offset="0xF9" text="LCD Data Register 13" icon="io_flag.bmp" mask="0xFF"/>
 649           <reg size="1" name="LCDDR12" offset="0xF8" text="LCD Data Register 12" icon="io_flag.bmp" mask="0xFF"/>
 650           <reg size="1" name="LCDDR11" offset="0xF7" text="LCD Data Register 11" icon="io_flag.bmp" mask="0xFF"/>
 651           <reg size="1" name="LCDDR10" offset="0xF6" text="LCD Data Register 10" icon="io_flag.bmp" mask="0xFF"/>
 652           <reg size="1" name="LCDDR9" offset="0xF5" text="LCD Data Register 9" icon="io_flag.bmp" mask="0xFF"/>
 653           <reg size="1" name="LCDDR8" offset="0xF4" text="LCD Data Register 8" icon="io_flag.bmp" mask="0xFF"/>
 654           <reg size="1" name="LCDDR7" offset="0xF3" text="LCD Data Register 7" icon="io_flag.bmp" mask="0xFF"/>
 655           <reg size="1" name="LCDDR6" offset="0xF2" text="LCD Data Register 6" icon="io_flag.bmp" mask="0xFF"/>
 656           <reg size="1" name="LCDDR5" offset="0xF1" text="LCD Data Register 5" icon="io_flag.bmp" mask="0xFF"/>
 657           <reg size="1" name="LCDDR4" offset="0xF0" text="LCD Data Register 4" icon="io_flag.bmp" mask="0xFF"/>
 658           <reg size="1" name="LCDDR3" offset="0xEF" text="LCD Data Register 3" icon="io_flag.bmp" mask="0xFF"/>
 659           <reg size="1" name="LCDDR2" offset="0xEE" text="LCD Data Register 2" icon="io_flag.bmp" mask="0xFF"/>
 660           <reg size="1" name="LCDDR1" offset="0xED" text="LCD Data Register 1" icon="io_flag.bmp" mask="0xFF"/>
 661           <reg size="1" name="LCDDR0" offset="0xEC" text="LCD Data Register 0" icon="io_flag.bmp" mask="0xFF"/>
 662           <reg size="1" name="LCDCCR" offset="0xE7" text="LCD Contrast Control Register" icon="io_flag.bmp">
 663             <bitfield name="LCDDC" mask="0xE0" text="LCD Display Configurations" icon="" enum="LCD_DISP_CONF_DRIVE"/>
 664             <bitfield name="LCDMDT" mask="0x10" text="LCD Maximum Drive Time" icon=""/>
 665             <bitfield name="LCDCC" mask="0x0F" text="LCD Contrast Controls" icon="" enum="LCD_CONTRAST"/>
 666           </reg>
 667           <reg size="1" name="LCDFRR" offset="0xE6" text="LCD Frame Rate Register" icon="io_flag.bmp">
 668             <bitfield name="LCDPS" mask="0x70" text="LCD Prescaler Selects" icon="" enum="LCD_PRESCALE"/>
 669             <bitfield name="LCDCD" mask="0x07" text="LCD Clock Dividers" icon="" enum="MISC_3BIT_COUNT"/>
 670           </reg>
 671           <reg size="1" name="LCDCRB" offset="0xE5" text="LCD Control and Status Register B" icon="io_flag.bmp">
 672             <bitfield name="LCDCS" mask="0x80" text="LCD CLock Select" icon=""/>
 673             <bitfield name="LCD2B" mask="0x40" text="LCD 1/2 Bias Select" icon=""/>
 674             <bitfield name="LCDMUX" mask="0x30" text="LCD Mux Selects" icon=""/>
 675             <bitfield name="LCDPM" mask="0x0F" text="LCD Port Masks" icon="" enum="LCD_PORT_MASK_4BIT"/>
 676           </reg>
 677           <reg size="1" name="LCDCRA" offset="0xE4" text="LCD Control and Status Register A" icon="io_flag.bmp">
 678             <bitfield name="LCDEN" mask="0x80" text="LCD Enable" icon=""/>
 679             <bitfield name="LCDAB" mask="0x40" text="LCD A or B waveform" icon=""/>
 680             <bitfield name="LCDIF" mask="0x10" text="LCD Interrupt Flag" icon=""/>
 681             <bitfield name="LCDIE" mask="0x08" text="LCD Interrupt Enable" icon=""/>
 682             <bitfield name="LCDBD" mask="0x04" text="LCD Buffer Disable" icon=""/>
 683             <bitfield name="LCDCCD" mask="0x02" text="LCD Contrast Control Disable" icon=""/>
 684             <bitfield name="LCDBL" mask="0x01" text="LCD Blanking" icon=""/>
 685           </reg>
 686         </registers>
 687     </module>
 688     <module class="CPU">
 689       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 690           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 691             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 692             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 693             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 694             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 695             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 696             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 697             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 698             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 699           </reg>
 700           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 701           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 702             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 703             <bitfield name="BODS" mask="0x40" text="BOD Sleep" icon=""/>
 704             <bitfield name="BODSE" mask="0x20" text="BOD Sleep Enable" icon=""/>
 705             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 706             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 707             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 708           </reg>
 709           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 710             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 711             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 712             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 713             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 714             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 715           </reg>
 716           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 717           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_cpu.bmp">
 718             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 719             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 720           </reg>
 721           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 722             <bitfield name="PRLCD" mask="0x10" text="Power Reduction LCD" icon=""/>
 723             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 724             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 725             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 726             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 727           </reg>
 728           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 729             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 730             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 731           </reg>
 732           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp" mask="0xFF"/>
 733           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp" mask="0xFF"/>
 734           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp" mask="0xFF"/>
 735         </registers>
 736     </module>
 737   </hardware>
 738 </device>