devices/atmega168p

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <packages>
   5     <package name="TQFP" pins="32">
   6       <pin id="1" name="[PD3:PCINT19:OC2B:INT1]">INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.</pin>
   7       <pin id="2" name="[PD4:XCK:T0:PCINT20]">XCK, USART external clock. T0,Timer/Counter0 counter source.</pin>
   8       <pin id="3" name="[GND]"/>
   9       <pin id="4" name="[VCC]"/>
  10       <pin id="5" name="[GND]"/>
  11       <pin id="6" name="[VCC]"/>
  12       <pin id="7" name="[PB6:XTAL1:TOSC1:PCINT6]">XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea</pin>
  13       <pin id="8" name="[PB7:XTAL2:TOSC2:PCINT7]">XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read</pin>
  14       <pin id="9" name="[PD5:T1:OC0B:PCINT21]">T1,Timer/Counter1 counter source.</pin>
  15       <pin id="10" name="[PD6:AIN0:OC0A:PCINT22]">AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  16       <pin id="11" name="[PD7:AIN1:PCINT23]">AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  17       <pin id="12" name="[PB0:ICP1:CLKO:PCINT0]">ICP1 -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1.</pin>
  18       <pin id="13" name="[PB1:OC1A:PCINT1]">OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.</pin>
  19       <pin id="14" name="[PB2:'SS:OC1B:PCINT2]">SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu</pin>
  20       <pin id="15" name="[PB3:MOSI:OC2A:PCINT3]">MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.</pin>
  21       <pin id="16" name="[PB4:MISO:PCINT4]">MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.</pin>
  22       <pin id="17" name="[PB5:SCK:PCINT5]">SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.</pin>
  23       <pin id="18" name="[AVCC]"/>
  24       <pin id="19" name="[ADC6]"/>
  25       <pin id="20" name="[AREF]"/>
  26       <pin id="21" name="[GND]"/>
  27       <pin id="22" name="[ADC7]"/>
  28       <pin id="23" name="[PC0:ADC0:PCINT8]">PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.</pin>
  29       <pin id="24" name="[PC1:ADC1:PCINT9]">PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.</pin>
  30       <pin id="25" name="[PC2:ADC2:PCINT10]">PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.</pin>
  31       <pin id="26" name="[PC3:ADC3:PCINT11]">PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.</pin>
  32       <pin id="27" name="[PC4:ADC4:SDA:PCINT12]">SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.</pin>
  33       <pin id="28" name="[PC5:ADC5:SCL:PCINT13]">SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.</pin>
  34       <pin id="29" name="[PC6:'RESET:PCINT14]">RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.</pin>
  35       <pin id="30" name="[PD0:RXD:PCINT16]">RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.</pin>
  36       <pin id="31" name="[PD1:TXD:PCINT17]">TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.</pin>
  37       <pin id="32" name="[PD2:INT0:PCINT18]">INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.</pin>
  38     </package>
  39     <package name="MLF" pins="32">
  40       <pin id="1" name="[PD3:PCINT19:OC2B:INT1]">INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.</pin>
  41       <pin id="2" name="[PD4:XCK:T0:PCINT20]">XCK, USART external clock. T0,Timer/Counter0 counter source.</pin>
  42       <pin id="3" name="[GND]"/>
  43       <pin id="4" name="[VCC]"/>
  44       <pin id="5" name="[GND]"/>
  45       <pin id="6" name="[VCC]"/>
  46       <pin id="7" name="[PB6:XTAL1:TOSC1:PCINT6]">XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea</pin>
  47       <pin id="8" name="[PB7:XTAL2:TOSC2:PCINT7]">XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read</pin>
  48       <pin id="9" name="[PD5:T1:OC0B:PCINT21]">T1,Timer/Counter1 counter source.</pin>
  49       <pin id="10" name="[PD6:AIN0:OC0A:PCINT22]">AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  50       <pin id="11" name="[PD7:AIN1:PCINT23]">AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  51       <pin id="12" name="[PB0:ICP:CLKO:PCINT0]">ICP -Input Capture Pin:The PB0 pin can act as an input capture pin for Timer/Counter1.</pin>
  52       <pin id="13" name="[PB1:OC1A:PCINT1]">OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.</pin>
  53       <pin id="14" name="[PB2:'SS:OC1B:PCINT2]">SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fu</pin>
  54       <pin id="15" name="[PB3:MOSI:OC2A:PCINT3]">MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.</pin>
  55       <pin id="16" name="[PB4:MISO:PCINT4]">MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.</pin>
  56       <pin id="17" name="[PB5:SCK:PCINT5]">SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.</pin>
  57       <pin id="18" name="[AVCC]"/>
  58       <pin id="19" name="[ADC6]"/>
  59       <pin id="20" name="[AREF]"/>
  60       <pin id="21" name="[GND]"/>
  61       <pin id="22" name="[ADC7]"/>
  62       <pin id="23" name="[PC0:ADC0:PCINT8]">PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.</pin>
  63       <pin id="24" name="[PC1:ADC1:PCINT9]">PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.</pin>
  64       <pin id="25" name="[PC2:ADC2:PCINT10]">PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.</pin>
  65       <pin id="26" name="[PC3:ADC3:PCINT11]">PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.</pin>
  66       <pin id="27" name="[PC4:ADC4:SDA:PCINT12]">SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.</pin>
  67       <pin id="28" name="[PC5:ADC5:SCL:PCINT13]">SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.</pin>
  68       <pin id="29" name="[PC6:'RESET:PCINT14]">RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.</pin>
  69       <pin id="30" name="[PD0:RXD:PCINT16]">RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.</pin>
  70       <pin id="31" name="[PD1:TXD:PCINT17]">TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.</pin>
  71       <pin id="32" name="[PD2:INT0:PCINT18]">INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.</pin>
  72     </package>
  73     <package name="PDIP" pins="28">
  74       <pin id="1" name="[PC6:'RESET:PCINT14]">RESET, Reset pin: When the RSTDISBL fuse is set,this pin functions as a normal I/O pin,and the part will have to rely on Power-On Reset and Brown-Out Reset as its reset sources.When the RSTDISBL fuse is cleared,the reset circuitry is connected to the pin,and the pin can not be used as an I/O pin. If PC6 is used as a reset pin,DDC6,PORTC6 and PINC6 will all read 0.</pin>
  75       <pin id="2" name="[PD0:RXD:PCINT16]">RXD,Receive Data (Data input pin for the USART).When the USART receiver is enabled this pin is configured as an input regardless of the value of DDD0.When the USART forces this pin to be an input,the pull-up can still be controlled by the PORTD0 bit.</pin>
  76       <pin id="3" name="[PD1:TXD:PCINT17]">TXD,Transmit Data (Data output pin for the USART).When the USART transmitter is enabled,this pin is configured as an output regardless of the value of DDD1.</pin>
  77       <pin id="4" name="[PD2:INT0:PCINT18]">INT0,External Interrupt source 0:The PD2 pin can serve as an external interrupt source.</pin>
  78       <pin id="5" name="[PD3:PCINT19:OC2B:INT1]">INT1,External Interrupt source 1:The PD3 pin can serve as an external interrupt source.</pin>
  79       <pin id="6" name="[PD4:XCK:T0:PCINT20]">XCK, USART external clock. T0,Timer/Counter0 counter source.</pin>
  80       <pin id="7" name="[VCC]"/>
  81       <pin id="8" name="[GND]"/>
  82       <pin id="9" name="[PB6:XTAL1:TOSC1:PCINT6]">XTAL1:Chipclock oscillator pin 1.Used for all chipclock sources except internal calibratable RC oscillator.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator as chip clock source,PB6 functions as an ordinary I/O pin. TOSC1:Timer Oscillator pin 1.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchronous clocking of Timer/Counter1,pin PB6 is disconnected from the port,and becomes the input of the inverting oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB6 is used as a clock pin,DDB6,PORTB6 and PINB6 will all rea</pin>
  83       <pin id="10" name="[PB7:XTAL2:TOSC2:PCINT7]">XTAL2:Chip clock oscillator pin 2.Used as clock pin for all chip clock sources except internal calibratable RC oscillator and external clock.When used as a clock pin,the pin can not be used as an I/O pin.When using internal calibratable RC oscillator or external clock as chipclock sources,PB7 functions as an ordinary I/O pin. TOSC2:Timer Oscillator pin 2.Used only if internal calibratable RC oscillator is selected as chip clock source,and the asynchronous timer is enabled by the correct setting in ASSR.When the AS2 bit in ASSR is set (one)to enable asynchro- nous clocking of Timer/Counter2,pin PB7 is disconnected from the port,and becomes the inverting output of the oscillator amplifier.In this mode,a crystal oscillator is connected to this pin,and the pin can not be used as an I/O pin. If PB7 is used as a clock pin,DDB7,PORTB7 and PINB7 will all read</pin>
  84       <pin id="11" name="[PD5:T1:OC0B:PCINT21]">T1,Timer/Counter1 counter source.</pin>
  85       <pin id="12" name="[PD6:AIN0:OC0A:PCINT22]">AIN0,Analog Comparator Positive Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  86       <pin id="13" name="[PD7:AIN1:PCINT23]">AIN1,Analog Comparator Negative Input.Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the analog comparator.</pin>
  87       <pin id="14" name="[PB0:ICP1:CLKO:PCINT0]">ICP1 -Input Capture Pin1:The PB0 pin can act as an input capture pin for Timer/Counter1.</pin>
  88       <pin id="15" name="[PB1:OC1A:PCINT1]">OC1A,Output compare match output:The PB1 pin can serve as an external output for the Timer/Counter1 compare match A.The PB1 pin has to be configured as an output (DDB1 set (one))to serve this function.The OC1A pin is also the output pin for the PWM mode timer function.</pin>
  89       <pin id="16" name="[PB2:'SS:OC1B:PCINT2]">SS:Slave Select input.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB4.As a slave,the SPI is activated when this pin is driven low.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB4.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB4 bit. OC1B,Output compare match output:The PB2 pin can serve as an external output for the Timer/Counter1 compare match B.The PB2 pin has to be configured as an output (DDB2 set (one))to serve this function.The OC1B pin is also the output pin for the PWM mode timer fun</pin>
  90       <pin id="17" name="[PB3:MOSI:OC2A:PCINT3]">MOSI:SPI Master data output,slave data input for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB5.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB bit.</pin>
  91       <pin id="18" name="[PB4:MISO:PCINT4]">MISO:Master data Input,Slave data Output pin for SPI channel.When the SPI is enabled as a master,this pin is configured as an input regardless of the setting of DDB6.When the SPI is enabled as a slave,the data direction of this pin is controlled by DDB6.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB6 bit.</pin>
  92       <pin id="19" name="[PB5:SCK:PCINT5]">SCK:Master clock output,slave clock input pin for SPI channel.When the SPI is enabled as a slave,this pin is configured as an input regardless of the setting of DDB7.When the SPI is enabled as a master,the data direction of this pin is controlled by DDB7.When the pin is forced by the SPI to be an input,the pull-up can still be controlled by the PORTB7 bit.</pin>
  93       <pin id="20" name="[AVCC]"/>
  94       <pin id="21" name="[AREF]"/>
  95       <pin id="22" name="[GND]"/>
  96       <pin id="23" name="[PC0:ADC0:PCINT8]">PC0 can also be used as ADC input Channel 0.Note that ADC input channel 0 uses analog ground.</pin>
  97       <pin id="24" name="[PC1:ADC1:PCINT9]">PC1 can also be used as ADC input Channel 1.Note that ADC input channel 1 uses analog ground.</pin>
  98       <pin id="25" name="[PC2:ADC2:PCINT10]">PC2 can also be used as ADC input Channel 2.Note that ADC input channel 2 uses analog ground.</pin>
  99       <pin id="26" name="[PC3:ADC3:PCINT11]">PC3 can also be used as ADC input Channel 3.Note that ADC input channel 3 uses analog ground.</pin>
 100       <pin id="27" name="[PC4:ADC4:SDA:PCINT12]">SDA,2-wire Serial Interface Data:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC4 can also be used as ADC input Channel 4.Note that ADC input channel 4 uses digital ground.</pin>
 101       <pin id="28" name="[PC5:ADC5:SCL:PCINT13]">SCL,2-wire Serial Interface Clock:When the TWEN bit in TWCR is set (one)to enable the 2-wire Serial Interface,pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface.In this mode,there is a spike filter on the pin to suppress spikes shorter than 0 ns on the input signal,and the pin is driven by an open drain driver with slew-rate limitation. PC can also be used as ADC input Channel 5.Note that ADC input channel uses digital ground.</pin>
 102     </package>
 103   </packages>
 104   <memory>
 105     <flash size="16384"/>
 106     <iospace start="$20" stop="$FF"/>
 107     <sram size="1024"/>
 108     <eram size="0"/>
 109   </memory>
 110   <ioregisters>
 111     <ioreg name="PINB" address="0x03"/>
 112     <ioreg name="DDRB" address="0x04"/>
 113     <ioreg name="PORTB" address="0x05"/>
 114     <ioreg name="PINC" address="0x06"/>
 115     <ioreg name="DDRC" address="0x07"/>
 116     <ioreg name="PORTC" address="0x08"/>
 117     <ioreg name="PIND" address="0x09"/>
 118     <ioreg name="DDRD" address="0x0A"/>
 119     <ioreg name="PORTD" address="0x0B"/>
 120     <ioreg name="TIFR0" address="0x15"/>
 121     <ioreg name="TIFR1" address="0x16"/>
 122     <ioreg name="TIFR2" address="0x17"/>
 123     <ioreg name="PCIFR" address="0x1B"/>
 124     <ioreg name="EIFR" address="0x1C"/>
 125     <ioreg name="EIMSK" address="0x1D"/>
 126     <ioreg name="GPIOR0" address="0x1E"/>
 127     <ioreg name="EECR" address="0x1F"/>
 128     <ioreg name="EEDR" address="0x20"/>
 129     <ioreg name="EEARL" address="0x21"/>
 130     <ioreg name="EEARH" address="0x22"/>
 131     <ioreg name="GTCCR" address="0x23"/>
 132     <ioreg name="TCCR0A" address="0x24"/>
 133     <ioreg name="TCCR0B" address="0x25"/>
 134     <ioreg name="TCNT0" address="0x26"/>
 135     <ioreg name="OCR0A" address="0x27"/>
 136     <ioreg name="OCR0B" address="0x28"/>
 137     <ioreg name="GPIOR1" address="0x2A"/>
 138     <ioreg name="GPIOR2" address="0x2B"/>
 139     <ioreg name="SPCR" address="0x2c"/>
 140     <ioreg name="SPSR" address="0x2D"/>
 141     <ioreg name="SPDR" address="0x2E"/>
 142     <ioreg name="ACSR" address="0x30"/>
 143     <ioreg name="SMCR" address="0x33"/>
 144     <ioreg name="MCUSR" address="0x34"/>
 145     <ioreg name="MCUCR" address="0x35"/>
 146     <ioreg name="SPMCSR" address="0x37"/>
 147     <ioreg name="SPL" address="0x3D"/>
 148     <ioreg name="SPH" address="0x3E"/>
 149     <ioreg name="SREG" address="0x3F"/>
 150     <ioreg name="WDTCSR" address="0x60"/>
 151     <ioreg name="CLKPR" address="0x61"/>
 152     <ioreg name="PRR" address="0x64"/>
 153     <ioreg name="OSCCAL" address="0x66"/>
 154     <ioreg name="PCICR" address="0x68"/>
 155     <ioreg name="EICRA" address="0x69"/>
 156     <ioreg name="PCMSK0" address="0x6B"/>
 157     <ioreg name="PCMSK1" address="0x6C"/>
 158     <ioreg name="PCMSK2" address="0x6D"/>
 159     <ioreg name="TIMSK0" address="0x6E"/>
 160     <ioreg name="TIMSK1" address="0x6F"/>
 161     <ioreg name="TIMSK2" address="0x70"/>
 162     <ioreg name="ADCL" address="0x78"/>
 163     <ioreg name="ADCH" address="0x79"/>
 164     <ioreg name="ADCSRA" address="0x7A"/>
 165     <ioreg name="ADCSRB" address="0x7B"/>
 166     <ioreg name="ADMUX" address="0x7C"/>
 167     <ioreg name="DIDR0" address="0x7E"/>
 168     <ioreg name="DIDR1" address="0x7F"/>
 169     <ioreg name="TCCR1A" address="0x80"/>
 170     <ioreg name="TCCR1B" address="0x81"/>
 171     <ioreg name="TCCR1C" address="0x82"/>
 172     <ioreg name="TCNT1L" address="0x84"/>
 173     <ioreg name="TCNT1H" address="0x85"/>
 174     <ioreg name="ICR1L" address="0x86"/>
 175     <ioreg name="ICR1H" address="0x87"/>
 176     <ioreg name="OCR1AL" address="0x88"/>
 177     <ioreg name="OCR1AH" address="0x89"/>
 178     <ioreg name="OCR1BL" address="0x8A"/>
 179     <ioreg name="OCR1BH" address="0x8B"/>
 180     <ioreg name="TCCR2A" address="0xB0"/>
 181     <ioreg name="TCCR2B" address="0xB1"/>
 182     <ioreg name="TCNT2" address="0xB2"/>
 183     <ioreg name="OCR2A" address="0xB3"/>
 184     <ioreg name="OCR2B" address="0xB4"/>
 185     <ioreg name="ASSR" address="0xB6"/>
 186     <ioreg name="TWBR" address="0xB8"/>
 187     <ioreg name="TWSR" address="0xB9"/>
 188     <ioreg name="TWAR" address="0xBA"/>
 189     <ioreg name="TWDR" address="0xBB"/>
 190     <ioreg name="TWCR" address="0xBC"/>
 191     <ioreg name="TWAMR" address="0xBD"/>
 192     <ioreg name="UCSR0A" address="0xC0"/>
 193     <ioreg name="UCSR0B" address="0xC1"/>
 194     <ioreg name="UCSR0C" address="0xC2"/>
 195     <ioreg name="UBRR0L" address="0xC4"/>
 196     <ioreg name="UBRR0H" address="0xC5"/>
 197     <ioreg name="UDR0" address="0xC6"/>
 198   </ioregisters>
 199   <interrupts num="26">
 200     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset</interrupt>
 201     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
 202     <interrupt vector="3" address="$004" name="INT1">External Interrupt Request 1</interrupt>
 203     <interrupt vector="4" address="$006" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
 204     <interrupt vector="5" address="$008" name="PCINT1">Pin Change Interrupt Request 0</interrupt>
 205     <interrupt vector="6" address="$00A" name="PCINT2">Pin Change Interrupt Request 1</interrupt>
 206     <interrupt vector="7" address="$00C" name="WDT">Watchdog Time-out Interrupt</interrupt>
 207     <interrupt vector="8" address="$00E" name="TIMER2 COMPA">Timer/Counter2 Compare Match A</interrupt>
 208     <interrupt vector="9" address="$0010" name="TIMER2 COMPB">Timer/Counter2 Compare Match A</interrupt>
 209     <interrupt vector="10" address="$0012" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
 210     <interrupt vector="11" address="$0014" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
 211     <interrupt vector="12" address="$0016" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
 212     <interrupt vector="13" address="$0018" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
 213     <interrupt vector="14" address="$001A" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
 214     <interrupt vector="15" address="$001C" name="TIMER0 COMPA">TimerCounter0 Compare Match A</interrupt>
 215     <interrupt vector="16" address="$001E" name="TIMER0 COMPB">TimerCounter0 Compare Match B</interrupt>
 216     <interrupt vector="17" address="$020" name="TIMER0 OVF">Timer/Couner0 Overflow</interrupt>
 217     <interrupt vector="18" address="$022" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
 218     <interrupt vector="19" address="$024" name="USART, RX">USART Rx Complete</interrupt>
 219     <interrupt vector="20" address="$026" name="USART, UDRE">USART, Data Register Empty</interrupt>
 220     <interrupt vector="21" address="$028" name="USART, TX">USART Tx Complete</interrupt>
 221     <interrupt vector="22" address="$02A" name="ADC">ADC Conversion Complete</interrupt>
 222     <interrupt vector="23" address="$02C" name="EE READY">EEPROM Ready</interrupt>
 223     <interrupt vector="24" address="$02E" name="ANALOG COMP">Analog Comparator</interrupt>
 224     <interrupt vector="25" address="$030" name="TWI">Two-wire Serial Interface</interrupt>
 225     <interrupt vector="26" address="$032" name="SPM Ready">Store Program Memory Read</interrupt>
 226   </interrupts>
 227   <hardware>
 228 <!--Everything after this needs editing!!!-->
 229     <module class="FUSE">
 230       <registers name="FUSE" memspace="FUSE">
 231           <reg size="1" name="EXTENDED" offset="0x02">
 232             <bitfield name="BOOTSZ" mask="0x06" text="Select boot size" icon="" enum="ENUM_BOOTSZ"/>
 233             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 234           </reg>
 235           <reg size="1" name="HIGH" offset="0x01">
 236             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PC6 as i/o pin)" icon=""/>
 237             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 238             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 239             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
 240             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 241             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 242           </reg>
 243           <reg size="1" name="LOW" offset="0x00">
 244             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 245             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB0" icon=""/>
 246             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 247           </reg>
 248         </registers>
 249     </module>
 250     <module class="LOCKBIT">
 251       <registers name="LOCKBIT" memspace="LOCKBIT">
 252           <reg size="1" name="LOCKBIT" offset="0x00">
 253             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 254             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 255             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 256           </reg>
 257         </registers>
 258     </module>
 259     <module class="USART0">
 260       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 261           <reg size="1" name="UDR0" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 262           <reg size="1" name="UCSR0A" offset="0xC0" text="USART Control and Status Register A" icon="io_flag.bmp">
 263             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 264             <bitfield name="TXC0" mask="0x40" text="USART Transmitt Complete" icon=""/>
 265             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 266             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 267             <bitfield name="DOR0" mask="0x08" text="Data overRun" icon=""/>
 268             <bitfield name="UPE0" mask="0x04" text="Parity Error" icon=""/>
 269             <bitfield name="U2X0" mask="0x02" text="Double the USART transmission speed" icon=""/>
 270             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 271           </reg>
 272           <reg size="1" name="UCSR0B" offset="0xC1" text="USART Control and Status Register B" icon="io_flag.bmp">
 273             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 274             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 275             <bitfield name="UDRIE0" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 276             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 277             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 278             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 279             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 280             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 281           </reg>
 282           <reg size="1" name="UCSR0C" offset="0xC2" text="USART Control and Status Register C" icon="io_flag.bmp">
 283             <bitfield name="UMSEL0" mask="0xC0" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 284             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 285             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 286             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 287             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 288           </reg>
 289           <reg size="2" name="UBRR0" offset="0xC4" text="USART Baud Rate Register  Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 290         </registers>
 291     </module>
 292     <module class="TWI">
 293       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 294           <reg size="1" name="TWAMR" offset="0xBD" text="TWI (Slave) Address Mask Register" icon="io_com.bmp">
 295             <bitfield name="TWAM" mask="0xFE" text="" icon=""/>
 296           </reg>
 297           <reg size="1" name="TWBR" offset="0xB8" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 298           <reg size="1" name="TWCR" offset="0xBC" text="TWI Control Register" icon="io_flag.bmp">
 299             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 300             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 301             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 302             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 303             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 304             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 305             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 306           </reg>
 307           <reg size="1" name="TWSR" offset="0xB9" text="TWI Status Register" icon="io_flag.bmp">
 308             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 309             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 310           </reg>
 311           <reg size="1" name="TWDR" offset="0xBB" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 312           <reg size="1" name="TWAR" offset="0xBA" text="TWI (Slave) Address register" icon="io_com.bmp">
 313             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 314             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 315           </reg>
 316         </registers>
 317     </module>
 318     <module class="TIMER_COUNTER_1">
 319       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 320           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 321             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 322             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 323             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 324             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 325           </reg>
 326           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 327             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 328             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 329             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 330             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 331           </reg>
 332           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 333             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 334             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 335             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 336           </reg>
 337           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 338             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 339             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 340             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 341             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 342           </reg>
 343           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter1 Control Register C" icon="io_flag.bmp">
 344             <bitfield name="FOC1A" mask="0x80" text="" icon=""/>
 345             <bitfield name="FOC1B" mask="0x40" text="" icon=""/>
 346           </reg>
 347           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 348           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 349           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 350           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 351           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 352             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 353             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 354           </reg>
 355         </registers>
 356     </module>
 357     <module class="TIMER_COUNTER_2">
 358       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 359           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 360             <bitfield name="OCIE2B" mask="0x04" text="Timer/Counter2 Output Compare Match B Interrupt Enable" icon=""/>
 361             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match A Interrupt Enable" icon=""/>
 362             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 363           </reg>
 364           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 365             <bitfield name="OCF2B" mask="0x04" text="Output Compare Flag 2B" icon=""/>
 366             <bitfield name="OCF2A" mask="0x02" text="Output Compare Flag 2A" icon=""/>
 367             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 368           </reg>
 369           <reg size="1" name="TCCR2A" offset="0xB0" text="Timer/Counter2 Control Register A" icon="io_flag.bmp">
 370             <bitfield name="COM2A" mask="0xC0" text="Compare Output Mode bits" icon=""/>
 371             <bitfield name="COM2B" mask="0x30" text="Compare Output Mode bits" icon=""/>
 372             <bitfield name="WGM2" mask="0x03" text="Waveform Genration Mode" icon=""/>
 373           </reg>
 374           <reg size="1" name="TCCR2B" offset="0xB1" text="Timer/Counter2 Control Register B" icon="io_flag.bmp">
 375             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare A" icon=""/>
 376             <bitfield name="FOC2B" mask="0x40" text="Force Output Compare B" icon=""/>
 377             <bitfield name="WGM22" mask="0x08" text="Waveform Generation Mode" icon=""/>
 378             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 379           </reg>
 380           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 381           <reg size="1" name="OCR2B" offset="0xB4" text="Timer/Counter2 Output Compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 382           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 383           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.bmp">
 384             <bitfield name="EXCLK" mask="0x40" text="Enable External Clock Input" icon=""/>
 385             <bitfield name="AS2" mask="0x20" text="Asynchronous Timer/Counter2" icon=""/>
 386             <bitfield name="TCN2UB" mask="0x10" text="Timer/Counter2 Update Busy" icon=""/>
 387             <bitfield name="OCR2AUB" mask="0x08" text="Output Compare Register2 Update Busy" icon=""/>
 388             <bitfield name="OCR2BUB" mask="0x04" text="Output Compare Register 2 Update Busy" icon=""/>
 389             <bitfield name="TCR2AUB" mask="0x02" text="Timer/Counter Control Register2 Update Busy" icon=""/>
 390             <bitfield name="TCR2BUB" mask="0x01" text="Timer/Counter Control Register2 Update Busy" icon=""/>
 391           </reg>
 392           <reg size="1" name="GTCCR" offset="0x43" text="General Timer Counter Control register" icon="io_flag.bmp">
 393             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 394             <bitfield name="PSRASY" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 395           </reg>
 396         </registers>
 397     </module>
 398     <module class="AD_CONVERTER">
 399       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 400           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 401             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF3"/>
 402             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 403             <bitfield name="MUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 404           </reg>
 405           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 406           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register A" icon="io_flag.bmp">
 407             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 408             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 409             <bitfield name="ADATE" mask="0x20" text="ADC  Auto Trigger Enable" icon=""/>
 410             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 411             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 412             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 413           </reg>
 414           <reg size="1" name="ADCSRB" offset="0x7B" text="The ADC Control and Status register B" icon="io_flag.bmp">
 415             <bitfield name="ACME" mask="0x40" text="" icon=""/>
 416             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Source bits" icon="" enum="ANALIG_ADC_AUTO_TRIGGER"/>
 417           </reg>
 418           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register" icon="io_analo.bmp">
 419             <bitfield name="ADC5D" mask="0x20" text="" icon=""/>
 420             <bitfield name="ADC4D" mask="0x10" text="" icon=""/>
 421             <bitfield name="ADC3D" mask="0x08" text="" icon=""/>
 422             <bitfield name="ADC2D" mask="0x04" text="" icon=""/>
 423             <bitfield name="ADC1D" mask="0x02" text="" icon=""/>
 424             <bitfield name="ADC0D" mask="0x01" text="" icon=""/>
 425           </reg>
 426         </registers>
 427     </module>
 428     <module class="ANALOG_COMPARATOR">
 429       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 430           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 431             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 432             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 433             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 434             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 435             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 436             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 437             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 438           </reg>
 439           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 440             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 441             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 442           </reg>
 443         </registers>
 444     </module>
 445     <module class="PORTB">
 446       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 447           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 448           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 449           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 450         </registers>
 451     </module>
 452     <module class="PORTC">
 453       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 454           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0x7F"/>
 455           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0x7F"/>
 456           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0x7F"/>
 457         </registers>
 458     </module>
 459     <module class="PORTD">
 460       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 461           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 462           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 463           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 464         </registers>
 465     </module>
 466     <module class="TIMER_COUNTER_0">
 467       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 468           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 469           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 470           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 471           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 472             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 473             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 474             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 475             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 476           </reg>
 477           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 478             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 479             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 480             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 481           </reg>
 482           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 483             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 484             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 485             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 486           </reg>
 487           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 488             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 489             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 490             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 491           </reg>
 492           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 493             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 494             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 495           </reg>
 496         </registers>
 497     </module>
 498     <module class="EXTERNAL_INTERRUPT">
 499       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 500           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register" icon="io_flag.bmp">
 501             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 502             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 503           </reg>
 504           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 505             <bitfield name="INT" mask="0x03" text="External Interrupt Request 1 Enable" icon=""/>
 506           </reg>
 507           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 508             <bitfield name="INTF" mask="0x03" text="External Interrupt Flags" icon=""/>
 509           </reg>
 510           <reg size="1" name="PCICR" offset="0x68" text="Pin Change Interrupt Control Register" icon="io_cpu.bmp">
 511             <bitfield name="PCIE" mask="0x07" text="Pin Change Interrupt Enables" icon=""/>
 512           </reg>
 513           <reg size="1" name="PCMSK2" offset="0x6D" text="Pin Change Mask Register 2" icon="io_flag.bmp">
 514             <bitfield name="PCINT" mask="0xFF" text="Pin Change Enable Masks" icon="" lsb="16"/>
 515           </reg>
 516           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp">
 517             <bitfield name="PCINT" mask="0x7F" text="Pin Change Enable Masks" icon="" lsb="8"/>
 518           </reg>
 519           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp">
 520             <bitfield name="PCINT" mask="0xFF" text="Pin Change Enable Masks" icon=""/>
 521           </reg>
 522           <reg size="1" name="PCIFR" offset="0x3B" text="Pin Change Interrupt Flag Register" icon="io_flag.bmp">
 523             <bitfield name="PCIF" mask="0x07" text="Pin Change Interrupt Flags" icon=""/>
 524           </reg>
 525         </registers>
 526     </module>
 527     <module class="SPI">
 528       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 529           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 530           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 531             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 532             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 533             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 534           </reg>
 535           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 536             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 537             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 538             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 539             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 540             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 541             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 542             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 543           </reg>
 544         </registers>
 545     </module>
 546     <module class="WATCHDOG">
 547       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 548           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 549             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 550             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 551             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 552             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 553             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 554           </reg>
 555         </registers>
 556     </module>
 557     <module class="EEPROM">
 558       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 559           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 560           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 561           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 562             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 563             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 564             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 565             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 566             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 567           </reg>
 568         </registers>
 569     </module>
 570     <module class="CPU">
 571       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 572           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 573             <bitfield name="PRTWI" mask="0x80" text="Power Reduction TWI" icon=""/>
 574             <bitfield name="PRTIM2" mask="0x40" text="Power Reduction Timer/Counter2" icon=""/>
 575             <bitfield name="PRTIM0" mask="0x20" text="Power Reduction Timer/Counter0" icon=""/>
 576             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 577             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 578             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 579             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 580           </reg>
 581           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 582           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_flag.bmp">
 583             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 584             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 585           </reg>
 586           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 587             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 588             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 589             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 590             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 591             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 592             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 593             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 594             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 595           </reg>
 596           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x07FF"/>
 597           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control and Status Register" icon="io_cpu.bmp">
 598             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 599             <bitfield name="RWWSB" mask="0x40" text="Read-While-Write Section Busy" icon=""/>
 600             <bitfield name="RWWSRE" mask="0x10" text="Read-While-Write section read enable" icon=""/>
 601             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 602             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 603             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 604             <bitfield name="SELFPRGEN" mask="0x01" text="Self Programming Enable" icon=""/>
 605           </reg>
 606           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 607             <bitfield name="BODS" mask="0x40" text="BOD Sleep" icon=""/>
 608             <bitfield name="BODSE" mask="0x20" text="BOD Sleep Enable" icon=""/>
 609             <bitfield name="PUD" mask="0x10" text="" icon=""/>
 610             <bitfield name="IVSEL" mask="0x02" text="" icon=""/>
 611             <bitfield name="IVCE" mask="0x01" text="" icon=""/>
 612           </reg>
 613           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 614             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 615             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 616             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 617             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 618           </reg>
 619           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_flag.bmp">
 620             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 621             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 622           </reg>
 623           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose I/O Register 2" icon="io_flag.bmp" mask="0xFF"/>
 624           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose I/O Register 1" icon="io_flag.bmp" mask="0xFF"/>
 625           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose I/O Register 0" icon="io_flag.bmp" mask="0xFF"/>
 626         </registers>
 627     </module>
 628   </hardware>
 629 </device>