devices/atmega161comp

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="21">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt 1</interrupt>
   8     <interrupt vector="4" address="$006" name="INT2">External Interrupt 2</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2_COMP">Timer/Counter2 Compare Match</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER2_OVF">Timer/Counter2 Overflow</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER0_COMP">Timer/Counter0 Compare Match</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="SPI,STC">Serial Transfer Complete</interrupt>
  18     <interrupt vector="14" address="$01A" name="UART0,RX">UART0, Rx Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="UART1,RX">UART1, Rx Complete</interrupt>
  20     <interrupt vector="16" address="$01E" name="UART0,UDRE">UART0 Data Register Empty</interrupt>
  21     <interrupt vector="17" address="$020" name="UART1,UDRE">UART1 Data Register Empty</interrupt>
  22     <interrupt vector="18" address="$022" name="UART0,TX">UART0, Tx Complete</interrupt>
  23     <interrupt vector="19" address="$024" name="UART1,TX">UART1, Tx Complete</interrupt>
  24     <interrupt vector="20" address="$026" name="EE_RDY">EEPROM Ready</interrupt>
  25     <interrupt vector="21" address="$028" name="ANA_COMP">Analog Comparator</interrupt>
  26   </interrupts>
  27   <packages>
  28     <package name="TQFP" pins="44">
  29       <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
  30       <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
  31       <pin id="3" name="[PB7:SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
  32       <pin id="4" name="['RESET]"/>
  33       <pin id="5" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART receiver is enabled, this pin is configured as an input, regardless of the value of DDRD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
  34       <pin id="6" name="[NC]"/>
  35       <pin id="7" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART transmitter is enabled, this pin is configured as an output, regardless of the value of DDRD1.</pin>
  36       <pin id="8" name="[PD2:INT0]">INT0: External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
  37       <pin id="9" name="[PD3:INT1]">INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
  38       <pin id="10" name="[PD4]"/>
  39       <pin id="11" name="[PD5:OC1A:TOSC2]">OC1A: Output compare match output. The PD5 pin can serve as an external output when the Timer/Counter1 compare matches. The PD5 pin has to be configured as an output (DDD5 set [one]) to serve this function. See the Timer/Counter1 description for further details and how to enable the output. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
  40       <pin id="12" name="[PD6:'WR]">WR is the external data memory write control strobe. See “Interface to External SRAM” on page 52 for detailed information.</pin>
  41       <pin id="13" name="[PD7:'RD]">RD is the external data memory read control strobe. See “Interface to External SRAM” on page 52 for detailed information.</pin>
  42       <pin id="14" name="[XTAL2]"/>
  43       <pin id="15" name="[XTAL1]"/>
  44       <pin id="16" name="[GND]"/>
  45       <pin id="17" name="[NC]"/>
  46       <pin id="18" name="[PC0:A8]"/>
  47       <pin id="19" name="[PC1:A9]"/>
  48       <pin id="20" name="[PC2:A10]"/>
  49       <pin id="21" name="[PC3:A11]"/>
  50       <pin id="22" name="[PC4:A12]"/>
  51       <pin id="23" name="[PC5:A13]"/>
  52       <pin id="24" name="[PC6:A14]"/>
  53       <pin id="25" name="[PC7:A15]"/>
  54       <pin id="26" name="[PE2:OC1B]"/>
  55       <pin id="27" name="[PE1:ALE]"/>
  56       <pin id="28" name="[NC]"/>
  57       <pin id="29" name="[PE0:ICP/INT2]"/>
  58       <pin id="30" name="[PA7:AD7]"/>
  59       <pin id="31" name="[PA6:AD6]"/>
  60       <pin id="32" name="[PA5:AD5]"/>
  61       <pin id="33" name="[PA4:AD4]"/>
  62       <pin id="34" name="[PA3:AD3]"/>
  63       <pin id="35" name="[PA2:AD2]"/>
  64       <pin id="36" name="[PA1:AD1]"/>
  65       <pin id="37" name="[PA0:AD0]"/>
  66       <pin id="38" name="[VCC]"/>
  67       <pin id="39" name="[NC]"/>
  68       <pin id="40" name="[PB0:OC0/T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
  69       <pin id="41" name="[PB1:OC2/T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
  70       <pin id="42" name="[PB2:RXD1:AIN0]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
  71       <pin id="43" name="[PB3:TXD1:AIN1]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
  72       <pin id="44" name="[PB4:SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
  73     </package>
  74   </packages>
  75   <memory>
  76     <flash size="16384"/>
  77     <iospace start="$20" stop="$5f"/>
  78     <sram size="1024"/>
  79     <eram size="65536"/>
  80   </memory>
  81   <ioregisters>
  82     <ioreg name="UBRR1L" address="$00"/>
  83     <ioreg name="UCSR1B" address="$01"/>
  84     <ioreg name="UCSR1A" address="$02"/>
  85     <ioreg name="UDR1" address="$03"/>
  86     <ioreg name="OSCCAL" address="$04"/>
  87     <ioreg name="OCDR" address="$04"/>
  88     <ioreg name="PINE" address="$05"/>
  89     <ioreg name="DDRE" address="$06"/>
  90     <ioreg name="PORTE" address="$07"/>
  91     <ioreg name="ACSR" address="$08"/>
  92     <ioreg name="UBRR0L" address="$09"/>
  93     <ioreg name="UCSR0B" address="$0A"/>
  94     <ioreg name="UCSR0A" address="$0B"/>
  95     <ioreg name="UDR0" address="$0C"/>
  96     <ioreg name="SPCR" address="$0D"/>
  97     <ioreg name="SPSR" address="$0E"/>
  98     <ioreg name="SPDR" address="$0F"/>
  99     <ioreg name="PIND" address="$10"/>
 100     <ioreg name="DDRD" address="$11"/>
 101     <ioreg name="PORTD" address="$12"/>
 102     <ioreg name="PINC" address="$13"/>
 103     <ioreg name="DDRC" address="$14"/>
 104     <ioreg name="PORTC" address="$15"/>
 105     <ioreg name="PINB" address="$16"/>
 106     <ioreg name="DDRB" address="$17"/>
 107     <ioreg name="PORTB" address="$18"/>
 108     <ioreg name="PINA" address="$19"/>
 109     <ioreg name="DDRA" address="$1A"/>
 110     <ioreg name="PORTA" address="$1B"/>
 111     <ioreg name="EECR" address="$1C"/>
 112     <ioreg name="EEDR" address="$1D"/>
 113     <ioreg name="EEARL" address="$1E"/>
 114     <ioreg name="EEARH" address="$1F"/>
 115     <ioreg name="UBRR0H" address="$20"/>
 116     <ioreg name="UCSR0C" address="$20"/>
 117     <ioreg name="WDTCR" address="$21"/>
 118     <ioreg name="OCR2" address="$22"/>
 119     <ioreg name="TCNT2" address="$23"/>
 120     <ioreg name="ICR1L" address="$24"/>
 121     <ioreg name="ICR1H" address="$25"/>
 122     <ioreg name="ASSR" address="$26"/>
 123     <ioreg name="TCCR2" address="$27"/>
 124     <ioreg name="OCR1BL" address="$28"/>
 125     <ioreg name="OCR1BH" address="$29"/>
 126     <ioreg name="OCR1AL" address="$2A"/>
 127     <ioreg name="OCR1AH" address="$2B"/>
 128     <ioreg name="TCNT1L" address="$2C"/>
 129     <ioreg name="TCNT1H" address="$2D"/>
 130     <ioreg name="TCCR1B" address="$2E"/>
 131     <ioreg name="TCCR1A" address="$2F"/>
 132     <ioreg name="SFIOR" address="$30"/>
 133     <ioreg name="OCR0" address="$31"/>
 134     <ioreg name="TCNT0" address="$32"/>
 135     <ioreg name="TCCR0" address="$33"/>
 136     <ioreg name="MCUCSR" address="$34"/>
 137     <ioreg name="MCUCR" address="$35"/>
 138     <ioreg name="EMCUCR" address="$36"/>
 139     <ioreg name="SPMCR" address="$37"/>
 140     <ioreg name="TIFR" address="$38"/>
 141     <ioreg name="TIMSK" address="$39"/>
 142     <ioreg name="GIFR" address="$3A"/>
 143     <ioreg name="GICR" address="$3B"/>
 144     <ioreg name="UBRR1H" address="$3C"/>
 145     <ioreg name="UCSR1C" address="$3C"/>
 146     <ioreg name="SPL" address="$3D"/>
 147     <ioreg name="SPH" address="$3E"/>
 148     <ioreg name="SREG" address="$3F"/>
 149     <ioreg name="CLKPR" address="$61"/>
 150     <ioreg name="PCMSK0" address="$6B"/>
 151     <ioreg name="PCMSK1" address="$6C"/>
 152     <ioreg name="ETIFR" address="$7C"/>
 153     <ioreg name="ETIMSK" address="$7D"/>
 154     <ioreg name="ICR3L" address="$80"/>
 155     <ioreg name="ICR3H" address="$81"/>
 156     <ioreg name="OCR3BL" address="$84"/>
 157     <ioreg name="OCR3BH" address="$85"/>
 158     <ioreg name="OCR3AL" address="$86"/>
 159     <ioreg name="OCR3AH" address="$87"/>
 160     <ioreg name="TCNT3L" address="$88"/>
 161     <ioreg name="TCNT3H" address="$89"/>
 162     <ioreg name="TCCR3B" address="$8A"/>
 163     <ioreg name="TCCR3A" address="$8B"/>
 164   </ioregisters>
 165   <hardware>
 166 <!--Everything after this needs editing!!!-->
 167     <module class="FUSE">
 168       <registers name="FUSE" memspace="FUSE">
 169           <reg size="1" name="EXTENDED" offset="0x02">
 170             <bitfield name="M161C" mask="0x10" text="ATmega161 compability mode" icon=""/>
 171             <bitfield name="BODLEVEL" mask="0x0E" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 172           </reg>
 173           <reg size="1" name="HIGH" offset="0x01">
 174             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 175             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 176             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 177             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 178             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROMthrough the Chip Erase cycle" icon=""/>
 179             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 180             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 181           </reg>
 182           <reg size="1" name="LOW" offset="0x00">
 183             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 184             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB0" icon=""/>
 185             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 186           </reg>
 187         </registers>
 188     </module>
 189     <module class="LOCKBIT">
 190       <registers name="LOCKBIT" memspace="LOCKBIT">
 191           <reg size="1" name="LOCKBIT" offset="0x00">
 192             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 193             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 194             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 195           </reg>
 196         </registers>
 197     </module>
 198     <module class="SPI">
 199       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 200           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 201           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 202             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 203             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 204             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 205           </reg>
 206           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 207             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 208             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 209             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 210             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 211             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 212             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 213             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 214           </reg>
 215         </registers>
 216     </module>
 217     <module class="PORTA">
 218       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 219           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 220           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 221           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 222         </registers>
 223     </module>
 224     <module class="PORTB">
 225       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 226           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 227           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 228           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 229         </registers>
 230     </module>
 231     <module class="PORTC">
 232       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 233           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 234           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 235           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 236         </registers>
 237     </module>
 238     <module class="PORTD">
 239       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 240           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 241           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 242           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 243         </registers>
 244     </module>
 245     <module class="PORTE">
 246       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 247           <reg size="1" name="PORTE" offset="0x27" text="Port E Data Register" icon="io_port.bmp" mask="0x07"/>
 248           <reg size="1" name="DDRE" offset="0x26" text="Port E Data Direction Register" icon="io_flag.bmp" mask="0x07"/>
 249           <reg size="1" name="PINE" offset="0x25" text="Port E Input Pins" icon="io_port.bmp" mask="0x07"/>
 250         </registers>
 251     </module>
 252     <module class="EEPROM">
 253       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 254           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 255           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 256           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 257             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 258             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 259             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 260             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 261           </reg>
 262         </registers>
 263     </module>
 264     <module class="TIMER_COUNTER_0">
 265       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 266           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter Control Register" icon="io_flag.bmp">
 267             <bitfield name="FOC0" mask="0x80" text="Force Output Compare" icon=""/>
 268             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon=""/>
 269             <bitfield name="COM0" mask="0x30" text="Compare Match Output Modes" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 270             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 271             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 272           </reg>
 273           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 274           <reg size="1" name="OCR0" offset="0x51" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 275           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 276             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 277             <bitfield name="OCIE0" mask="0x01" text="Timer/Counter0 Output Compare Match Interrupt register" icon=""/>
 278           </reg>
 279           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 280             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 281             <bitfield name="OCF0" mask="0x01" text="Output Compare Flag 0" icon=""/>
 282           </reg>
 283           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 284             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 285           </reg>
 286         </registers>
 287     </module>
 288     <module class="TIMER_COUNTER_1">
 289       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 290           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 291             <bitfield name="TOIE1" mask="0x80" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 292             <bitfield name="OCIE1A" mask="0x40" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 293             <bitfield name="OCIE1B" mask="0x20" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 294             <bitfield name="TICIE1" mask="0x08" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 295           </reg>
 296           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 297             <bitfield name="TOV1" mask="0x80" text="Timer/Counter1 Overflow Flag" icon=""/>
 298             <bitfield name="OCF1A" mask="0x40" text="Output Compare Flag 1A" icon=""/>
 299             <bitfield name="OCF1B" mask="0x20" text="Output Compare Flag 1B" icon=""/>
 300             <bitfield name="ICF1" mask="0x08" text="Input Capture Flag 1" icon=""/>
 301           </reg>
 302           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 303             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 304             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 305             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
 306             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
 307             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 308           </reg>
 309           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 310             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 311             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 312             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 313             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 314           </reg>
 315           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 316           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 317           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 318           <reg size="2" name="ICR1" offset="0x44" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 319         </registers>
 320     </module>
 321     <module class="WATCHDOG">
 322       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 323           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 324             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 325             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 326             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 327           </reg>
 328         </registers>
 329     </module>
 330     <module class="USART0">
 331       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 332           <reg size="1" name="UDR0" offset="0x2C" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 333           <reg size="1" name="UCSR0A" offset="0x2B" text="USART Control and Status Register A" icon="io_flag.bmp">
 334             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 335             <bitfield name="TXC0" mask="0x40" text="USART Transmitt Complete" icon=""/>
 336             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 337             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 338             <bitfield name="DOR0" mask="0x08" text="Data overRun" icon=""/>
 339             <bitfield name="UPE0" mask="0x04" text="Parity Error" icon=""/>
 340             <bitfield name="U2X0" mask="0x02" text="Double the USART transmission speed" icon=""/>
 341             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 342           </reg>
 343           <reg size="1" name="UCSR0B" offset="0x2A" text="USART Control and Status Register B" icon="io_flag.bmp">
 344             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 345             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 346             <bitfield name="UDRIE0" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 347             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 348             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 349             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 350             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 351             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 352           </reg>
 353           <reg size="1" name="UCSR0C" offset="0x40" text="USART Control and Status Register C" icon="io_flag.bmp">
 354             <bitfield name="URSEL0" mask="0x80" text="Register Select" icon=""/>
 355             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 356             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 357             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 358             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 359             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 360           </reg>
 361           <reg size="1" name="UBRR0H" offset="0x40" text="USART Baud Rate Register Hight Byte" icon="io_com.bmp" mask="0x8F"/>
 362           <reg size="1" name="UBRR0L" offset="0x29" text="USART Baud Rate Register Low Byte" icon="io_com.bmp" mask="0xFF"/>
 363         </registers>
 364     </module>
 365     <module class="USART1">
 366       <registers name="USART1" memspace="DATAMEM" text="" icon="io_com.bmp">
 367           <reg size="1" name="UDR" offset="0x23" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 368           <reg size="1" name="UCSR1A" offset="0x22" text="USART Control and Status Register A" icon="io_flag.bmp">
 369             <bitfield name="RXC1" mask="0x80" text="USART Receive Complete" icon=""/>
 370             <bitfield name="TXC1" mask="0x40" text="USART Transmitt Complete" icon=""/>
 371             <bitfield name="UDRE1" mask="0x20" text="USART Data Register Empty" icon=""/>
 372             <bitfield name="FE1" mask="0x10" text="Framing Error" icon=""/>
 373             <bitfield name="DOR1" mask="0x08" text="Data overRun" icon=""/>
 374             <bitfield name="UPE1" mask="0x04" text="Parity Error" icon=""/>
 375             <bitfield name="U2X1" mask="0x02" text="Double the USART transmission speed" icon=""/>
 376             <bitfield name="MPCM1" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 377           </reg>
 378           <reg size="1" name="UCSR1B" offset="0x21" text="USART Control and Status Register B" icon="io_flag.bmp">
 379             <bitfield name="RXCIE1" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 380             <bitfield name="TXCIE1" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 381             <bitfield name="UDRIE1" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 382             <bitfield name="RXEN1" mask="0x10" text="Receiver Enable" icon=""/>
 383             <bitfield name="TXEN1" mask="0x08" text="Transmitter Enable" icon=""/>
 384             <bitfield name="UCSZ12" mask="0x04" text="Character Size" icon=""/>
 385             <bitfield name="RXB81" mask="0x02" text="Receive Data Bit 8" icon=""/>
 386             <bitfield name="TXB81" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 387           </reg>
 388           <reg size="1" name="UCSR1C" offset="0x5C" text="USART Control and Status Register C" icon="io_flag.bmp">
 389             <bitfield name="URSEL1" mask="0x80" text="Register Select" icon=""/>
 390             <bitfield name="UMSEL1" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 391             <bitfield name="UPM1" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 392             <bitfield name="USBS1" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 393             <bitfield name="UCSZ1" mask="0x06" text="Character Size" icon=""/>
 394             <bitfield name="UCPOL1" mask="0x01" text="Clock Polarity" icon=""/>
 395           </reg>
 396           <reg size="1" name="UBRR1H" offset="0x5C" text="USART Baud Rate Register Highg Byte" icon="io_com.bmp" mask="0x0F"/>
 397           <reg size="1" name="UBRR1L" offset="0x20" text="USART Baud Rate Register Low Byte" icon="io_com.bmp" mask="0xFF"/>
 398         </registers>
 399     </module>
 400     <module class="TIMER_COUNTER_2">
 401       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 402           <reg size="1" name="TCCR2" offset="0x47" text="Timer/Counter Control Register" icon="io_flag.bmp">
 403             <bitfield name="FOC2" mask="0x80" text="Forde Output Compare" icon=""/>
 404             <bitfield name="WGM20" mask="0x40" text="Pulse Width Modulator Select Bit 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 405             <bitfield name="COM2" mask="0x30" text="Compare Match Output Mode" icon=""/>
 406             <bitfield name="WGM21" mask="0x08" text="Pulse Width Modulator Select Bit 1" icon=""/>
 407             <bitfield name="CS2" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT"/>
 408           </reg>
 409           <reg size="1" name="TCNT2" offset="0x43" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 410           <reg size="1" name="OCR2" offset="0x42" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 411           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 412             <bitfield name="OCIE2" mask="0x10" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 413             <bitfield name="TOIE2" mask="0x04" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 414           </reg>
 415           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 416             <bitfield name="OCF2" mask="0x10" text="Output Compare Flag 2" icon=""/>
 417             <bitfield name="TOV2" mask="0x04" text="Timer/Counter2 Overflow Flag" icon=""/>
 418           </reg>
 419           <reg size="1" name="ASSR" offset="0x46" text="Asynchronous Status Register" icon="io_flag.bmp">
 420             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer 2" icon=""/>
 421             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 422             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 423             <bitfield name="TCR2UB" mask="0x01" text="Timer/Counter Control Register2 Update Busy" icon=""/>
 424           </reg>
 425         </registers>
 426     </module>
 427     <module class="ANALOG_COMPARATOR">
 428       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 429           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 430             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 431             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 432             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 433             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 434             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 435             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 436             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 437           </reg>
 438         </registers>
 439     </module>
 440     <module class="CPU">
 441       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 442           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 443             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 444             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 445             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 446             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 447             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 448             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 449             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 450             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 451           </reg>
 452           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 453           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 454             <bitfield name="SRE" mask="0x80" text="External SRAM Enable" icon=""/>
 455             <bitfield name="SRW10" mask="0x40" text="External SRAM Wait State Select" icon=""/>
 456             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 457             <bitfield name="SM1" mask="0x10" text="Sleep Mode Select" icon=""/>
 458             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 459             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 460           </reg>
 461           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 462             <bitfield name="JDT" mask="0x80" text="JTAG Interface Disable" icon=""/>
 463             <bitfield name="SM2" mask="0x20" text="Sleep Mode Select Bit 2" icon=""/>
 464             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 465             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 466             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 467             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 468             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 469           </reg>
 470           <reg size="1" name="EMCUCR" offset="0x56" text="Extended MCU Control Register" icon="io_flag.bmp">
 471             <bitfield name="SM0" mask="0x80" text="Sleep mode Select Bit 0" icon=""/>
 472             <bitfield name="SRL" mask="0x70" text="Wait State Sector Limit Bits" icon="" enum="CPU_SECTOR_LIMITS"/>
 473             <bitfield name="SRW0" mask="0x0C" text="Wait State Select Bit 1 for Lower Sector" icon="" enum="CPU_WAIT_STATES"/>
 474             <bitfield name="SRW11" mask="0x02" text="Wait State Select Bit 1 for Upper Sector" icon=""/>
 475             <bitfield name="ISC2" mask="0x01" text="Interrupt Sense Control 2" icon=""/>
 476           </reg>
 477           <reg size="1" name="OSCCAL" offset="0x24" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0x7F"/>
 478           <reg size="1" name="CLKPR" offset="0x61" text="Clock prescale register" icon="io_cpu.bmp">
 479             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 480             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 481           </reg>
 482           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 483             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 484             <bitfield name="XMBK" mask="0x40" text="External Memory Bus Keeper Enable" icon=""/>
 485             <bitfield name="XMM" mask="0x38" text="External Memory High Mask Bits" icon=""/>
 486             <bitfield name="PUD" mask="0x04" text="Pull-up Disable" icon=""/>
 487             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 488             <bitfield name="PSR310" mask="0x01" text="Prescaler Reset Timer/Counter3, Timer/Counter1 and Timer/Counter0" icon=""/>
 489           </reg>
 490         </registers>
 491     </module>
 492     <module class="BOOT_LOAD">
 493       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 494           <reg size="1" name="SPMCR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 495             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 496             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 497             <bitfield name="RWWSRE" mask="0x10" text="Read While Write secion read enable" icon=""/>
 498             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 499             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 500             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 501             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 502           </reg>
 503         </registers>
 504     </module>
 505     <module class="EXTERNAL_INTERRUPT">
 506       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 507           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 508             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 509             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 510           </reg>
 511           <reg size="1" name="EMCUCR" offset="0x56" text="Extended MCU Control Register" icon="io_flag.bmp">
 512             <bitfield name="ISC2" mask="0x01" text="Interrupt Sense Control 2" icon=""/>
 513           </reg>
 514           <reg size="1" name="GICR" offset="0x5B" text="General Interrupt Control Register" icon="io_flag.bmp">
 515             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 516             <bitfield name="INT2" mask="0x20" text="External Interrupt Request 2 Enable" icon=""/>
 517             <bitfield name="PCIE" mask="0x18" text="Pin Change Interrupt Enables" icon=""/>
 518             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 519             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 520           </reg>
 521           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_flag.bmp">
 522             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 523             <bitfield name="INTF2" mask="0x20" text="External Interrupt Flag 2" icon=""/>
 524             <bitfield name="PCIF" mask="0x18" text="Pin Change Interrupt Flags" icon=""/>
 525           </reg>
 526           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp" mask="0xFF"/>
 527           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Enable Mask" icon="io_flag.bmp" mask="0xFF"/>
 528         </registers>
 529     </module>
 530   </hardware>
 531 </device>