devices/atmega103

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="24">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt 1</interrupt>
   8     <interrupt vector="4" address="$006" name="INT2">External Interrupt 2</interrupt>
   9     <interrupt vector="5" address="$008" name="INT3">External Interrupt 3</interrupt>
  10     <interrupt vector="6" address="$00A" name="INT4">External Interrupt 4</interrupt>
  11     <interrupt vector="7" address="$00C" name="INT5">External Interrupt 5</interrupt>
  12     <interrupt vector="8" address="$00E" name="INT6">External Interrupt 6</interrupt>
  13     <interrupt vector="9" address="$010" name="INT7">External Interrupt 7</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER2_COMP">Timer/Counter2 Compare Match</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER2_OVF">Timer/Counter2 Overflow</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
  17     <interrupt vector="13" address="$018" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
  18     <interrupt vector="14" address="$01A" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  19     <interrupt vector="15" address="$01C" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  20     <interrupt vector="16" address="$01E" name="TIMER0_COMP">Timer/Counter0 Compare Match</interrupt>
  21     <interrupt vector="17" address="$020" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  22     <interrupt vector="18" address="$022" name="SPI,STC">SPI Serial Transfer Complete</interrupt>
  23     <interrupt vector="19" address="$024" name="UART,RX">UART, Rx Complete</interrupt>
  24     <interrupt vector="20" address="$026" name="UART,UDRE">UART Data Register Empty</interrupt>
  25     <interrupt vector="21" address="$028" name="UART,TX">UART, Tx Complete</interrupt>
  26     <interrupt vector="22" address="$02A" name="ADC">ADC Conversion Complete</interrupt>
  27     <interrupt vector="23" address="$02C" name="EE_READY">EEPROM Ready</interrupt>
  28     <interrupt vector="24" address="$02E" name="ANALOG_COMP">Analog Comparator</interrupt>
  29   </interrupts>
  30   <memory>
  31     <flash size="131072"/>
  32     <iospace start="$20" stop="$5F"/>
  33     <sram size="4000"/>
  34     <eram size="65536"/>
  35   </memory>
  36   <ioregisters>
  37     <ioreg name="PINF" address="$00"/>
  38     <ioreg name="PINE" address="$01"/>
  39     <ioreg name="DDRE" address="$02"/>
  40     <ioreg name="PORTE" address="$03"/>
  41     <ioreg name="ADCL" address="$04"/>
  42     <ioreg name="ADCH" address="$05"/>
  43     <ioreg name="ADCSR" address="$06"/>
  44     <ioreg name="ADMUX" address="$07"/>
  45     <ioreg name="ACSR" address="$08"/>
  46     <ioreg name="UBRR" address="$09"/>
  47     <ioreg name="UCR" address="$0A"/>
  48     <ioreg name="USR" address="$0B"/>
  49     <ioreg name="UDR" address="$0C"/>
  50     <ioreg name="SPCR" address="$0D"/>
  51     <ioreg name="SPSR" address="$0E"/>
  52     <ioreg name="SPDR" address="$0F"/>
  53     <ioreg name="PIND" address="$10"/>
  54     <ioreg name="DDRD" address="$11"/>
  55     <ioreg name="PORTD" address="$12"/>
  56     <ioreg name="PORTC" address="$15"/>
  57     <ioreg name="PINB" address="$16"/>
  58     <ioreg name="DDRB" address="$17"/>
  59     <ioreg name="PORTB" address="$18"/>
  60     <ioreg name="PINA" address="$19"/>
  61     <ioreg name="DDRA" address="$1A"/>
  62     <ioreg name="PORTA" address="$1B"/>
  63     <ioreg name="EECR" address="$1C"/>
  64     <ioreg name="EEDR" address="$1D"/>
  65     <ioreg name="EEARL" address="$1E"/>
  66     <ioreg name="EEARH" address="$1F"/>
  67     <ioreg name="WDTCR" address="$21"/>
  68     <ioreg name="OCR2" address="$23"/>
  69     <ioreg name="TCNT2" address="$24"/>
  70     <ioreg name="TCCR2" address="$25"/>
  71     <ioreg name="ICR1L" address="$26"/>
  72     <ioreg name="ICR1H" address="$27"/>
  73     <ioreg name="OCR1BL" address="$28"/>
  74     <ioreg name="OCR1BH" address="$29"/>
  75     <ioreg name="OCR1AL" address="$2A"/>
  76     <ioreg name="OCR1AH" address="$2B"/>
  77     <ioreg name="TCNT1L" address="$2C"/>
  78     <ioreg name="TCNT1H" address="$2D"/>
  79     <ioreg name="TCCR1B" address="$2E"/>
  80     <ioreg name="TCCR1A" address="$2F"/>
  81     <ioreg name="ASSR" address="$30"/>
  82     <ioreg name="OCR0" address="$31"/>
  83     <ioreg name="TCNT0" address="$32"/>
  84     <ioreg name="TCCR0" address="$33"/>
  85     <ioreg name="MCUSR" address="$34"/>
  86     <ioreg name="MCUCR" address="$35"/>
  87     <ioreg name="TIFR" address="$36"/>
  88     <ioreg name="TIMSK" address="$37"/>
  89     <ioreg name="EIFR" address="$38"/>
  90     <ioreg name="EIMSK" address="$39"/>
  91     <ioreg name="EICR" address="$3A"/>
  92     <ioreg name="RAMPZ" address="$3B"/>
  93     <ioreg name="XDIV" address="$3C"/>
  94     <ioreg name="SPL" address="$3D"/>
  95     <ioreg name="SPH" address="$3E"/>
  96     <ioreg name="SREG" address="$3F"/>
  97   </ioregisters>
  98   <packages>
  99     <package name="TQFP" pins="64">
 100       <pin id="1" name="['PEN]"/>
 101       <pin id="2" name="[PE0:RXD0:PDI]">PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega104. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.</pin>
 102       <pin id="3" name="[PE1:TXD0:PDO]">PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega104. TXD0, UART0 Transmit Pin.</pin>
 103       <pin id="4" name="[PE2:AC+]"/>
 104       <pin id="5" name="[PE3:AC-]"/>
 105       <pin id="6" name="[PE4:INT4]">INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. </pin>
 106       <pin id="7" name="[PE5:INT5]">INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. </pin>
 107       <pin id="8" name="[PE6:INT6]">INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source.</pin>
 108       <pin id="9" name="[PE7:INT7]">INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source.</pin>
 109       <pin id="10" name="[PB0:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.</pin>
 110       <pin id="11" name="[PB1:SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.</pin>
 111       <pin id="12" name="[PB2:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.</pin>
 112       <pin id="13" name="[PB3:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.</pin>
 113       <pin id="14" name="[PB4:OC0:PWM0]">OC0, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function.</pin>
 114       <pin id="15" name="[PB5:OC1A:PWM1A]">OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 115       <pin id="16" name="[PB6:OC1B:PWM1B]">OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
 116       <pin id="17" name="[PB7:OC2:PWM2:OC1C]">OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
 117       <pin id="18" name="[TOSC2]">TOSC2, Timer Oscillator pin 2.</pin>
 118       <pin id="19" name="[TOSC1]">TOSC1, Timer Oscillator pin 1</pin>
 119       <pin id="20" name="['RESET]"/>
 120       <pin id="21" name="[VCC]"/>
 121       <pin id="22" name="[GND]"/>
 122       <pin id="23" name="[XTAL2]"/>
 123       <pin id="24" name="[XTAL1]"/>
 124       <pin id="25" name="[PD0:'INT0]">INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source.</pin>
 125       <pin id="26" name="[PD1:'INT1]">INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source.</pin>
 126       <pin id="27" name="[PD2:'INT2]">INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source.</pin>
 127       <pin id="28" name="[PD3:'INT3]">INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source.</pin>
 128       <pin id="29" name="[PD4:IC1]">IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1.</pin>
 129       <pin id="30" name="[PD5]"/>
 130       <pin id="31" name="[PD6:T1]">T1, Timer/Counter1 counter source.</pin>
 131       <pin id="32" name="[PD7:T2]">T2, Timer/Counter2 counter source.</pin>
 132       <pin id="33" name="['WR]">WR is the external data memory write control strobe.</pin>
 133       <pin id="34" name="['RD]">RD is the external data memory read control strobe.</pin>
 134       <pin id="35" name="[PC0:A8]"/>
 135       <pin id="36" name="[PC1:A9]"/>
 136       <pin id="37" name="[PC2:A10]"/>
 137       <pin id="38" name="[PC3:A11]"/>
 138       <pin id="39" name="[PC4:A12]"/>
 139       <pin id="40" name="[PC5:A13]"/>
 140       <pin id="41" name="[PC6:A14]"/>
 141       <pin id="42" name="[PC7:A15]"/>
 142       <pin id="43" name="[ALE]">ALE is the external data memory Address Latch Enable signal.</pin>
 143       <pin id="44" name="[PA7:AD7]"/>
 144       <pin id="45" name="[PA6:AD6]"/>
 145       <pin id="46" name="[PA5:AD5]"/>
 146       <pin id="47" name="[PA4:AD4]"/>
 147       <pin id="48" name="[PA3:AD3]"/>
 148       <pin id="49" name="[PA2:AD2]"/>
 149       <pin id="50" name="[PA1:AD1]"/>
 150       <pin id="51" name="[PA0:AD0]"/>
 151       <pin id="52" name="[VCC]"/>
 152       <pin id="53" name="[GND]"/>
 153       <pin id="54" name="[PF7:ADC7]">ADC7, Analog to Digital Converter, channel 7.</pin>
 154       <pin id="55" name="[PF6:ADC6]">ADC6, Analog to Digital Converter, channel 6. </pin>
 155       <pin id="56" name="[PF5:ADC5]">ADC5, Analog to Digital Converter, channel 5.</pin>
 156       <pin id="57" name="[PF4:ADC4]">ADC4, Analog to Digital Converter, channel 4. </pin>
 157       <pin id="58" name="[PF3:ADC3]">Analog to Digital Converter, Channel 3</pin>
 158       <pin id="59" name="[PF2:ADC2]">Analog to Digital Converter, Channel 2</pin>
 159       <pin id="60" name="[PF1:ADC1]">Analog to Digital Converter, Channel 1</pin>
 160       <pin id="61" name="[PF0:ADC0]">Analog to Digital Converter, Channel 0</pin>
 161       <pin id="62" name="[AREF]"/>
 162       <pin id="63" name="[GND]"/>
 163       <pin id="64" name="[AVCC]"/>
 164     </package>
 165   </packages>
 166   <hardware>
 167 <!--Everything after this needs editing!!!-->
 168     <module class="FUSE">
 169       <registers name="FUSE" memspace="FUSE">
 170           <reg size="1" name="LOW" offset="0x00">
 171             <bitfield name="SUT1" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 172             <bitfield name="CKSEL3" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 173             <bitfield name="CKSEL" mask="0x03" text="Select Clock Source" icon="" enum="ENUM_CKSEL"/>
 174           </reg>
 175         </registers>
 176     </module>
 177     <module class="LOCKBIT">
 178       <registers name="LOCKBIT" memspace="LOCKBIT">
 179           <reg size="1" name="LOCKBIT" offset="0x00">
 180             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
 181           </reg>
 182         </registers>
 183     </module>
 184     <module class="AD_CONVERTER">
 185       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 186           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp" mask="0x07"/>
 187           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 188             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 189             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 190             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 191             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 192             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 193           </reg>
 194           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0x03FF"/>
 195         </registers>
 196     </module>
 197     <module class="ANALOG_COMPARATOR">
 198       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 199           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 200             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 201             <bitfield name="ACO" mask="0x20" text="Analog Comparator Output" icon=""/>
 202             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 203             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 204             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 205             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 206           </reg>
 207         </registers>
 208     </module>
 209     <module class="SPI">
 210       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 211           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 212             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 213             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 214             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 215             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 216             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 217             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 218             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE"/>
 219           </reg>
 220           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 221             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 222             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 223           </reg>
 224           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 225         </registers>
 226     </module>
 227     <module class="UART">
 228       <registers name="UART" memspace="DATAMEM" text="" icon="io_com.bmp">
 229           <reg size="1" name="UDR" offset="0x2C" text="UART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 230           <reg size="1" name="USR" offset="0x2B" text="UART Status Register" icon="io_flag.bmp">
 231             <bitfield name="RXC" mask="0x80" text="UART Receive Complete" icon=""/>
 232             <bitfield name="TXC" mask="0x40" text="UART Transmit Complete" icon=""/>
 233             <bitfield name="UDRE" mask="0x20" text="UART Data Register Empty" icon=""/>
 234             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 235             <bitfield name="OR" mask="0x08" text="Overrun" icon=""/>
 236           </reg>
 237           <reg size="1" name="UCR" offset="0x2A" text="UART Control Register" icon="io_flag.bmp">
 238             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 239             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 240             <bitfield name="UDRIE" mask="0x20" text="UART Data Register Empty Interrupt Enable" icon=""/>
 241             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 242             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 243             <bitfield name="CHR9" mask="0x04" text="9-bit Characters" icon=""/>
 244             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 245             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 246           </reg>
 247           <reg size="1" name="UBRR" offset="0x29" text="UART BAUD Rate Register" icon="io_com.bmp" mask="0xFF"/>
 248         </registers>
 249     </module>
 250     <module class="CPU">
 251       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 252           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 253             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 254             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 255             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 256             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 257             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 258             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 259             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 260             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 261           </reg>
 262           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 263           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 264             <bitfield name="SRE" mask="0x80" text="External SRAM Enable" icon=""/>
 265             <bitfield name="SRW" mask="0x40" text="External SRAM Wait State Select" icon=""/>
 266             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 267             <bitfield name="SM" mask="0x18" text="Sleep Mode Select" icon="" enum="CPU_SLEEP_MODE"/>
 268           </reg>
 269           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 270             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 271             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 272           </reg>
 273           <reg size="1" name="XDIV" offset="0x5C" text="XTAL Divide Control Register" icon="io_cpu.bmp" mask="0xFF"/>
 274           <reg size="1" name="RAMPZ" offset="0x5B" text="RAM Page Z Select Register" icon="io_cpu.bmp">
 275             <bitfield name="RAMPZ0" mask="0x01" text="RAMPZ0 = 0: Program memory address $0000 - $7FFF.  RAMPZ0 = 1, program memory address $8000 - $FFFF." icon=""/>
 276           </reg>
 277         </registers>
 278     </module>
 279     <module class="EXTERNAL_INTERRUPT">
 280       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 281           <reg size="1" name="EICRB" offset="0x5A" text="External Interrupt Control Register B" icon="io_flag.bmp">
 282             <bitfield name="ISC7" mask="0xC0" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 283             <bitfield name="ISC6" mask="0x30" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 284             <bitfield name="ISC5" mask="0x0C" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 285             <bitfield name="ISC4" mask="0x03" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 286           </reg>
 287           <reg size="1" name="EIMSK" offset="0x59" text="External Interrupt Mask Register" icon="io_flag.bmp">
 288             <bitfield name="INT" mask="0xFF" text="External Interrupt Request 7 Enable" icon=""/>
 289           </reg>
 290           <reg size="1" name="EIFR" offset="0x58" text="External Interrupt Flag Register" icon="io_flag.bmp">
 291             <bitfield name="INTF" mask="0xF0" text="External Interrupt Flags" icon="" lsb="4"/>
 292           </reg>
 293         </registers>
 294     </module>
 295     <module class="EEPROM">
 296       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 297           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x0FFF"/>
 298           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 299           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 300             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 301             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 302             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 303             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 304           </reg>
 305         </registers>
 306     </module>
 307     <module class="PORTA">
 308       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 309           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 310           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 311           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 312         </registers>
 313     </module>
 314     <module class="PORTB">
 315       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 316           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 317           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 318           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 319         </registers>
 320     </module>
 321     <module class="PORTD">
 322       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 323           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 324           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 325           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 326         </registers>
 327     </module>
 328     <module class="PORTC">
 329       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 330           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 331         </registers>
 332     </module>
 333     <module class="PORTE">
 334       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 335           <reg size="1" name="PORTE" offset="0x23" text="Data Register, Port E" icon="io_port.bmp" mask="0xFF"/>
 336           <reg size="1" name="DDRE" offset="0x22" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0xFF"/>
 337           <reg size="1" name="PINE" offset="0x21" text="Input Pins, Port E" icon="io_port.bmp" mask="0xFF"/>
 338         </registers>
 339     </module>
 340     <module class="PORTF">
 341       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 342           <reg size="1" name="PINF" offset="0x20" text="Input Pins, Port F" icon="io_port.bmp" mask="0xFF"/>
 343         </registers>
 344     </module>
 345     <module class="TIMER_COUNTER_2">
 346       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 347           <reg size="1" name="TIMSK" offset="0x57" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 348             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 349             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 350           </reg>
 351           <reg size="1" name="TIFR" offset="0x56" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 352             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 353             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 354           </reg>
 355           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 356             <bitfield name="PWM2" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 357             <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 358             <bitfield name="CTC2" mask="0x08" text="Clear Timer/Counter2 on Compare Match" icon=""/>
 359             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 360           </reg>
 361           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 362           <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 363         </registers>
 364     </module>
 365     <module class="TIMER_COUNTER_0">
 366       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 367           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter Control Register" icon="io_flag.bmp">
 368             <bitfield name="PWM0" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 369             <bitfield name="COM0" mask="0x30" text="Compare Match Output Modes" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 370             <bitfield name="CTC0" mask="0x08" text="CLear Timer/Counter on Compare Match" icon=""/>
 371             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT"/>
 372           </reg>
 373           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter Register" icon="io_timer.bmp">
 374             <bitfield name="TCNT0_" mask="0xFF" text="" icon=""/>
 375           </reg>
 376           <reg size="1" name="OCR0" offset="0x51" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 377           <reg size="1" name="ASSR" offset="0x50" text="Asynchronus Status Register" icon="io_flag.bmp">
 378             <bitfield name="AS0" mask="0x08" text="Asynchronus Timer/Counter 0" icon=""/>
 379             <bitfield name="TCN0UB" mask="0x04" text="Timer/Couner0 Update Busy" icon=""/>
 380             <bitfield name="OCR0UB" mask="0x02" text="Output Compare register 0 Busy" icon=""/>
 381             <bitfield name="TCR0UB" mask="0x01" text="Timer/Counter Control Register 0 Update Busy" icon=""/>
 382           </reg>
 383           <reg size="1" name="TIMSK" offset="0x57" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 384             <bitfield name="OCIE0" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt register" icon=""/>
 385             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 386           </reg>
 387           <reg size="1" name="TIFR" offset="0x56" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 388             <bitfield name="OCF0" mask="0x02" text="Output Compare Flag 0" icon=""/>
 389             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 390           </reg>
 391         </registers>
 392     </module>
 393     <module class="TIMER_COUNTER_1">
 394       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 395           <reg size="1" name="TIMSK" offset="0x57" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 396             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 397             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 398             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 399             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 400           </reg>
 401           <reg size="1" name="TIFR" offset="0x56" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 402             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 403             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 404             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 405             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 406           </reg>
 407           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 408             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 409             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 410             <bitfield name="PWM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon="" enum="PULSE_WIDTH_MODU"/>
 411           </reg>
 412           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 413             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 414             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 415             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 416             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 417           </reg>
 418           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 419           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 420           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 421           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 422         </registers>
 423     </module>
 424     <module class="WATCHDOG">
 425       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 426           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 427             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 428             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 429             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 430           </reg>
 431         </registers>
 432     </module>
 433   </hardware>
 434 </device>