devices/at90s4434

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="17">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$002" name="INT1">External Interrupt 1</interrupt>
   8     <interrupt vector="4" address="$003" name="TIMER2_COMP">Timer/Counter2 Compare Match</interrupt>
   9     <interrupt vector="5" address="$004" name="TIMER2_OVF">Timer/Counter2 Overflow</interrupt>
  10     <interrupt vector="6" address="$005" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
  11     <interrupt vector="7" address="$006" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
  12     <interrupt vector="8" address="$007" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  13     <interrupt vector="9" address="$008" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  14     <interrupt vector="10" address="$009" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  15     <interrupt vector="11" address="$00A" name="SPI,STC">SPI Serial Transfer Complete</interrupt>
  16     <interrupt vector="12" address="$00B" name="UART,RX">UART, RX Complete</interrupt>
  17     <interrupt vector="13" address="$00C" name="UART,UDRE">UART Data Register Empty</interrupt>
  18     <interrupt vector="14" address="$00D" name="UART,TX">UART, TX Complete</interrupt>
  19     <interrupt vector="15" address="$00E" name="ADC">ADC Conversion Complete</interrupt>
  20     <interrupt vector="16" address="$00F" name="EE_RDY">EEPROM Ready</interrupt>
  21     <interrupt vector="17" address="$010" name="ANA_COMP">Analog Comparator</interrupt>
  22   </interrupts>
  23   <memory>
  24     <flash size="4096"/>
  25     <iospace start="$20" stop="$5F"/>
  26     <sram size="256"/>
  27     <eram size="0"/>
  28   </memory>
  29   <ioregisters>
  30     <ioreg name="ADCL" address="$04"/>
  31     <ioreg name="ADCH" address="$05"/>
  32     <ioreg name="ADCSR" address="$06"/>
  33     <ioreg name="ADMUX" address="$07"/>
  34     <ioreg name="ACSR" address="$08"/>
  35     <ioreg name="UBRR" address="$09"/>
  36     <ioreg name="UCR" address="$0A"/>
  37     <ioreg name="USR" address="$0B"/>
  38     <ioreg name="UDR" address="$0C"/>
  39     <ioreg name="SPCR" address="$0D"/>
  40     <ioreg name="SPSR" address="$0E"/>
  41     <ioreg name="SPDR" address="$0F"/>
  42     <ioreg name="PIND" address="$10"/>
  43     <ioreg name="DDRD" address="$11"/>
  44     <ioreg name="PORTD" address="$12"/>
  45     <ioreg name="PINC" address="$13"/>
  46     <ioreg name="DDRC" address="$14"/>
  47     <ioreg name="PORTC" address="$15"/>
  48     <ioreg name="PINB" address="$16"/>
  49     <ioreg name="DDRB" address="$17"/>
  50     <ioreg name="PORTB" address="$18"/>
  51     <ioreg name="PINA" address="$19"/>
  52     <ioreg name="DDRA" address="$1A"/>
  53     <ioreg name="PORTA" address="$1B"/>
  54     <ioreg name="EECR" address="$1C"/>
  55     <ioreg name="EEDR" address="$1D"/>
  56     <ioreg name="EEARL" address="$1E"/>
  57     <ioreg name="EEARH" address="$1F"/>
  58     <ioreg name="WDTCR" address="$21"/>
  59     <ioreg name="ASSR" address="$22"/>
  60     <ioreg name="OCR2" address="$23"/>
  61     <ioreg name="TCNT2" address="$24"/>
  62     <ioreg name="TCCR2" address="$25"/>
  63     <ioreg name="ICR1L" address="$26"/>
  64     <ioreg name="ICR1H" address="$27"/>
  65     <ioreg name="OCR1BL" address="$28"/>
  66     <ioreg name="OCR1BH" address="$29"/>
  67     <ioreg name="OCR1AL" address="$2A"/>
  68     <ioreg name="OCR1AH" address="$2B"/>
  69     <ioreg name="TCNT1L" address="$2C"/>
  70     <ioreg name="TCNT1H" address="$2D"/>
  71     <ioreg name="TCCR1B" address="$2E"/>
  72     <ioreg name="TCCR1A" address="$2F"/>
  73     <ioreg name="TCNT0" address="$32"/>
  74     <ioreg name="TCCR0" address="$33"/>
  75     <ioreg name="MCUSR" address="$34"/>
  76     <ioreg name="MCUCR" address="$35"/>
  77     <ioreg name="TIFR" address="$38"/>
  78     <ioreg name="TIMSK" address="$39"/>
  79     <ioreg name="GIFR" address="$3A"/>
  80     <ioreg name="GIMSK" address="$3B"/>
  81     <ioreg name="SPL" address="$3D"/>
  82     <ioreg name="SPH" address="$3E"/>
  83     <ioreg name="SREG" address="$3F"/>
  84   </ioregisters>
  85   <packages>
  86     <package name="TQFP" pins="44">
  87       <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
  88       <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
  89       <pin id="3" name="[PB7_SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
  90       <pin id="4" name="['RESET]"/>
  91       <pin id="5" name="[VCC]"/>
  92       <pin id="6" name="[GND]"/>
  93       <pin id="7" name="[XTAL2]"/>
  94       <pin id="8" name="[XTAL1]"/>
  95       <pin id="9" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
  96       <pin id="10" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
  97       <pin id="11" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
  98       <pin id="12" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
  99       <pin id="13" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
 100       <pin id="14" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 101       <pin id="15" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
 102       <pin id="16" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
 103       <pin id="17" name="[VCC]"/>
 104       <pin id="18" name="[GND]"/>
 105       <pin id="19" name="[PC0]"/>
 106       <pin id="20" name="[PC1]"/>
 107       <pin id="21" name="[PC2]"/>
 108       <pin id="22" name="[PC3]"/>
 109       <pin id="23" name="[PC4]"/>
 110       <pin id="24" name="[PC5]"/>
 111       <pin id="25" name="[PC6:TOSC1]"/>
 112       <pin id="26" name="[PC7:TOSC2]"/>
 113       <pin id="27" name="[AVCC]"/>
 114       <pin id="28" name="[AGND]"/>
 115       <pin id="29" name="[AREF]"/>
 116       <pin id="30" name="[PA7:ADC7]"/>
 117       <pin id="31" name="[PA6:ADC6]"/>
 118       <pin id="32" name="[PA5:ADc5]"/>
 119       <pin id="33" name="[PA4:ADC4]"/>
 120       <pin id="34" name="[PA3:ADC3]"/>
 121       <pin id="35" name="[PA2:ADC2]"/>
 122       <pin id="36" name="[PA1:ADC1]"/>
 123       <pin id="37" name="[PA0:ADC0]"/>
 124       <pin id="38" name="[VCC]"/>
 125       <pin id="39" name="[GND]"/>
 126       <pin id="40" name="[PB0:T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
 127       <pin id="41" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
 128       <pin id="42" name="[PB2:AIN0]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
 129       <pin id="43" name="[PB3:AIN1]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
 130       <pin id="44" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
 131     </package>
 132   </packages>
 133   <hardware>
 134 <!--Everything after this needs editing!!!-->
 135     <module class="FUSE">
 136       <registers name="FUSE" memspace="FUSE">
 137           <reg size="1" name="LOW" offset="0x00">
 138             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 139             <bitfield name="FSTRT" mask="0x01" text="Short start-up time enabled" icon=""/>
 140           </reg>
 141         </registers>
 142     </module>
 143     <module class="LOCKBIT">
 144       <registers name="LOCKBIT" memspace="LOCKBIT">
 145           <reg size="1" name="LOCKBIT" offset="0x00">
 146             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
 147           </reg>
 148         </registers>
 149     </module>
 150     <module class="TIMER_COUNTER_0">
 151       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 152           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 153             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 154           </reg>
 155           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 156             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 157           </reg>
 158           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 159             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon=""/>
 160             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 161             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon="" enum="CLK_SEL_3BIT_EXT"/>
 162           </reg>
 163           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 164         </registers>
 165     </module>
 166     <module class="TIMER_COUNTER_1">
 167       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 168           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 169             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 170             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 171             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 172             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 173           </reg>
 174           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 175             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 176             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 177             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 178             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 179           </reg>
 180           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 181             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 182             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 183             <bitfield name="PWM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon="" enum="PULSE_WIDTH_MODU"/>
 184           </reg>
 185           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 186             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 187             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 188             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 189             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 190           </reg>
 191           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 192           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 193           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 194           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 195         </registers>
 196     </module>
 197     <module class="TIMER_COUNTER_2">
 198       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 199           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter Control Register" icon="io_flag.bmp">
 200             <bitfield name="PWM2" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 201             <bitfield name="COM2" mask="0x30" text="Compare Match Output Mode" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 202             <bitfield name="CTC2" mask="0x08" text="Clear Timer/Counter Compare Match" icon=""/>
 203             <bitfield name="CS2" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT"/>
 204           </reg>
 205           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 206           <reg size="1" name="OCR2" offset="0x43" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 207           <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
 208             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer 2" icon=""/>
 209             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 210             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 211             <bitfield name="TCR2UB" mask="0x01" text="Timer/Counter Control Register2 Update Busy" icon=""/>
 212           </reg>
 213           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 214             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 215             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 216           </reg>
 217           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 218             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 219             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 220           </reg>
 221         </registers>
 222     </module>
 223     <module class="UART">
 224       <registers name="UART" memspace="DATAMEM" text="" icon="io_com.bmp">
 225           <reg size="1" name="UDR" offset="0x2C" text="UART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 226           <reg size="1" name="USR" offset="0x2B" text="UART Status Register" icon="io_flag.bmp">
 227             <bitfield name="RXC" mask="0x80" text="UART Receive Complete" icon=""/>
 228             <bitfield name="TXC" mask="0x40" text="UART Transmit Complete" icon=""/>
 229             <bitfield name="UDRE" mask="0x20" text="UART Data Register Empty" icon=""/>
 230             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 231             <bitfield name="OR" mask="0x08" text="Overrun" icon=""/>
 232           </reg>
 233           <reg size="1" name="UCR" offset="0x2A" text="UART Control Register" icon="io_flag.bmp">
 234             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 235             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 236             <bitfield name="UDRIE" mask="0x20" text="UART Data Register Empty Interrupt Enable" icon=""/>
 237             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 238             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 239             <bitfield name="CHR9" mask="0x04" text="9-bit Characters" icon=""/>
 240             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 241             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 242           </reg>
 243           <reg size="1" name="UBRR" offset="0x29" text="UART BAUD Rate Register" icon="io_com.bmp" mask="0xFF"/>
 244         </registers>
 245     </module>
 246     <module class="SPI">
 247       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 248           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 249             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 250             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 251             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 252             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 253             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 254             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 255             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE"/>
 256           </reg>
 257           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 258             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 259             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 260           </reg>
 261           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 262         </registers>
 263     </module>
 264     <module class="PORTA">
 265       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 266           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 267           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 268           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 269         </registers>
 270     </module>
 271     <module class="PORTB">
 272       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 273           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 274           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 275           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 276         </registers>
 277     </module>
 278     <module class="PORTC">
 279       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 280           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 281           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 282           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 283         </registers>
 284     </module>
 285     <module class="PORTD">
 286       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 287           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 288           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 289           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 290         </registers>
 291     </module>
 292     <module class="ANALOG_COMPARATOR">
 293       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 294           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 295             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 296             <bitfield name="ACO" mask="0x20" text="Analog Comparator Output" icon=""/>
 297             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 298             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 299             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 300             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 301           </reg>
 302         </registers>
 303     </module>
 304     <module class="AD_CONVERTER">
 305       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 306           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp" mask="0x07"/>
 307           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 308             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 309             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 310             <bitfield name="ADFR" mask="0x20" text="ADC  Free Running Select" icon=""/>
 311             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 312             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 313             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 314           </reg>
 315           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0x03FF"/>
 316         </registers>
 317     </module>
 318     <module class="WATCHDOG">
 319       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 320           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 321             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 322             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 323             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 324           </reg>
 325         </registers>
 326     </module>
 327     <module class="EEPROM">
 328       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 329           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 330           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 331           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 332             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 333             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 334             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 335             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 336           </reg>
 337         </registers>
 338     </module>
 339     <module class="CPU">
 340       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.com">
 341           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 342             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 343             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 344             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 345             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 346             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 347             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 348             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 349             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 350           </reg>
 351           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x03FF"/>
 352           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 353             <bitfield name="SE" mask="0x40" text="Sleep Enable" icon=""/>
 354             <bitfield name="SM" mask="0x30" text="Sleep Mode Selects" icon="" enum="CPU_SLEEP_MODE"/>
 355             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 356             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 357           </reg>
 358           <reg size="1" name="MCUSR" offset="0x54" text="" icon="io_cpu.bmp">
 359             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 360             <bitfield name="PORF" mask="0x01" text="Power-on Reset Flag" icon=""/>
 361           </reg>
 362         </registers>
 363     </module>
 364     <module class="EXTERNAL_INTERRUPT">
 365       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 366           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 367             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 368           </reg>
 369           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 370             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 371           </reg>
 372         </registers>
 373     </module>
 374   </hardware>
 375 </device>