devices/at90s4433

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="4096"/>
   6     <iospace start="$20" stop="$5F"/>
   7     <sram size="128"/>
   8     <eram size="0"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="UBRRHI" address="$03"/>
  12     <ioreg name="ADCL" address="$04"/>
  13     <ioreg name="ADCH" address="$05"/>
  14     <ioreg name="ADCSR" address="$06"/>
  15     <ioreg name="ADMUX" address="$07"/>
  16     <ioreg name="ACSR" address="$08"/>
  17     <ioreg name="UBRR" address="$09"/>
  18     <ioreg name="UCSRB" address="$0A"/>
  19     <ioreg name="UCSRA" address="$0B"/>
  20     <ioreg name="UDR" address="$0C"/>
  21     <ioreg name="SPCR" address="$0D"/>
  22     <ioreg name="SPSR" address="$0E"/>
  23     <ioreg name="SPDR" address="$0F"/>
  24     <ioreg name="PIND" address="$10"/>
  25     <ioreg name="DDRD" address="$11"/>
  26     <ioreg name="PORTD" address="$12"/>
  27     <ioreg name="PINC" address="$13"/>
  28     <ioreg name="DDRC" address="$14"/>
  29     <ioreg name="PORTC" address="$15"/>
  30     <ioreg name="PINB" address="$16"/>
  31     <ioreg name="DDRB" address="$17"/>
  32     <ioreg name="PORTB" address="$18"/>
  33     <ioreg name="EECR" address="$1C"/>
  34     <ioreg name="EEDR" address="$1D"/>
  35     <ioreg name="EEAR" address="$1E"/>
  36     <ioreg name="WDTCR" address="$21"/>
  37     <ioreg name="ICR1L" address="$26"/>
  38     <ioreg name="ICR1H" address="$27"/>
  39     <ioreg name="OCR1L" address="$2A"/>
  40     <ioreg name="OCR1H" address="$2B"/>
  41     <ioreg name="TCNT1L" address="$2C"/>
  42     <ioreg name="TCNT1H" address="$2D"/>
  43     <ioreg name="TCCR1B" address="$2E"/>
  44     <ioreg name="TCCR1A" address="$2F"/>
  45     <ioreg name="TCNT0" address="$32"/>
  46     <ioreg name="TCCR0" address="$33"/>
  47     <ioreg name="MCUSR" address="$34"/>
  48     <ioreg name="MCUCR" address="$35"/>
  49     <ioreg name="TIFR" address="$38"/>
  50     <ioreg name="TIMSK" address="$39"/>
  51     <ioreg name="GIFR" address="$3A"/>
  52     <ioreg name="GIMSK" address="$3B"/>
  53     <ioreg name="SP" address="$3D"/>
  54     <ioreg name="SREG" address="$3F"/>
  55   </ioregisters>
  56   <interrupts num="14">
  57     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
  58     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
  59     <interrupt vector="3" address="$002" name="INT1">External Interrupt 1</interrupt>
  60     <interrupt vector="4" address="$003" name="TIMER1_CAPT">Timer/Counter Capture Event</interrupt>
  61     <interrupt vector="5" address="$004" name="TIMER1_COMP">Timer/Counter1 Compare Match</interrupt>
  62     <interrupt vector="6" address="$005" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  63     <interrupt vector="7" address="$006" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  64     <interrupt vector="8" address="$007" name="SPI,STC">Serial Transfer Complete</interrupt>
  65     <interrupt vector="9" address="$008" name="UART,RX">UART, Rx Complete</interrupt>
  66     <interrupt vector="10" address="$009" name="UART,UDRE">UART Data Register Empty</interrupt>
  67     <interrupt vector="11" address="$00A" name="UART, TX">UART, Tx Complete</interrupt>
  68     <interrupt vector="12" address="$00B" name="ADC">ADC Conversion Complete</interrupt>
  69     <interrupt vector="13" address="$00C" name="EE_RDY">EEPROM Ready</interrupt>
  70     <interrupt vector="14" address="$00D" name="ANA_COMP">Analog Comparator</interrupt>
  71   </interrupts>
  72   <packages>
  73     <package name="TQFP" pins="32">
  74       <pin id="1" name="[INT1:PD3]"/>
  75       <pin id="2" name="[T0:PD4]"/>
  76       <pin id="3" name="[NC]"/>
  77       <pin id="4" name="[VCC]"/>
  78       <pin id="5" name="[GND]"/>
  79       <pin id="6" name="[NC]"/>
  80       <pin id="7" name="[XTAL1]"/>
  81       <pin id="8" name="[XTAL2]"/>
  82       <pin id="9" name="[T1:PD5]"/>
  83       <pin id="10" name="[AIN0:PD6]"/>
  84       <pin id="11" name="[AIN1:PD7]"/>
  85       <pin id="12" name="[ICP:PB0]"/>
  86       <pin id="13" name="[OC1:PB1]"/>
  87       <pin id="14" name="[SS:PB2]"/>
  88       <pin id="15" name="[MOS1:PB3]"/>
  89       <pin id="16" name="[MOS0:PB4]"/>
  90       <pin id="17" name="[SCK:PB5]"/>
  91       <pin id="18" name="[AVCC]"/>
  92       <pin id="19" name="[NC]"/>
  93       <pin id="20" name="[AREF]"/>
  94       <pin id="21" name="[AGND]"/>
  95       <pin id="22" name="[NC]"/>
  96       <pin id="23" name="[PC0:ADC0]"/>
  97       <pin id="24" name="[PC1:ADC1]"/>
  98       <pin id="25" name="[PC2:ADC2]"/>
  99       <pin id="26" name="[PC3:ADC3]"/>
 100       <pin id="27" name="[PC4:ADC4]"/>
 101       <pin id="28" name="[PC5:ADC5]"/>
 102       <pin id="29" name="[RESET]"/>
 103       <pin id="30" name="[PD0:RXD]"/>
 104       <pin id="31" name="[PD1:TXD]"/>
 105       <pin id="32" name="[PD2:INT0]"/>
 106     </package>
 107   </packages>
 108   <hardware>
 109 <!--Everything after this needs editing!!!-->
 110     <module class="FUSE">
 111       <registers name="FUSE" memspace="FUSE">
 112           <reg size="1" name="LOW" offset="0x00">
 113             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 114             <bitfield name="BODEN" mask="0x08" text="Brown-out Detection Enabled" icon=""/>
 115             <bitfield name="BODLEVEL" mask="0x10" text="Brown-out Detection Level" icon="" enum="ENUM1"/>
 116             <bitfield name="CKSEL" mask="0x07" text="Clock Select" icon="" enum="ENUM2"/>
 117           </reg>
 118         </registers>
 119     </module>
 120     <module class="LOCKBIT">
 121       <registers name="LOCKBIT" memspace="LOCKBIT">
 122           <reg size="1" name="LOCKBIT" offset="0x00">
 123             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
 124           </reg>
 125         </registers>
 126     </module>
 127     <module class="ANALOG_COMPARATOR">
 128       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 129           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 130             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 131             <bitfield name="AINBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 132             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 133             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 134             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 135             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 136             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 137           </reg>
 138         </registers>
 139     </module>
 140     <module class="AD_CONVERTER">
 141       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 142           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp" mask="0x47"/>
 143           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 144             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 145             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 146             <bitfield name="ADFR" mask="0x20" text="ADC  Free Running Select" icon=""/>
 147             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 148             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 149             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 150           </reg>
 151           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0x03FF"/>
 152         </registers>
 153     </module>
 154     <module class="UART">
 155       <registers name="UART" memspace="DATAMEM" text="" icon="io_com.bmp">
 156           <reg size="1" name="UDR" offset="0x2C" text="UART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 157           <reg size="1" name="UCSRA" offset="0x2B" text="UART Control and Status register A" icon="io_flag.bmp">
 158             <bitfield name="RXC" mask="0x80" text="UART Receive Complete" icon=""/>
 159             <bitfield name="TXC" mask="0x40" text="UART Transmitt Complete" icon=""/>
 160             <bitfield name="UDRE" mask="0x20" text="UART Data Register Empty" icon=""/>
 161             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 162             <bitfield name="OR" mask="0x08" text="Overrun" icon=""/>
 163             <bitfield name="MPCM" mask="0x01" text="Mulit-processor Communication Mode" icon=""/>
 164           </reg>
 165           <reg size="1" name="UCSRB" offset="0x2A" text="UART Control an Status register B" icon="io_flag.bmp">
 166             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 167             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 168             <bitfield name="UDRIE" mask="0x20" text="UART Data Register Empty Interrupt Enable" icon=""/>
 169             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 170             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 171             <bitfield name="CHR9" mask="0x04" text="9-bit Characters" icon=""/>
 172             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 173             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 174           </reg>
 175           <reg size="1" name="UBRRHI" offset="0x23" text="UART Baud Rate Register High Byte" icon="io_com.bmp" mask="0x0F"/>
 176           <reg size="1" name="UBRR" offset="0x29" text="UART Baud Rate Register" icon="io_com.bmp" mask="0xFF"/>
 177         </registers>
 178     </module>
 179     <module class="SPI">
 180       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 181           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 182             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 183             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 184             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 185             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 186             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 187             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 188             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE"/>
 189           </reg>
 190           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 191             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 192             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 193           </reg>
 194           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 195         </registers>
 196     </module>
 197     <module class="CPU">
 198       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.com">
 199           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 200             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 201             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 202             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 203             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 204             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 205             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 206             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 207             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 208           </reg>
 209           <reg size="1" name="SP" offset="0x5D" text="Stack Pointer" icon="" mask="0xFF"/>
 210           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 211             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 212             <bitfield name="SM" mask="0x10" text="Sleep Mode Select" icon=""/>
 213             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 214             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 215           </reg>
 216           <reg size="1" name="MCUSR" offset="0x54" text="" icon="io_cpu.bmp">
 217             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 218             <bitfield name="BORF" mask="0x04" text="Brown-Out Reset Flag" icon=""/>
 219             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 220             <bitfield name="PORF" mask="0x01" text="Power-on Reset Flag" icon=""/>
 221           </reg>
 222         </registers>
 223     </module>
 224     <module class="EXTERNAL_INTERRUPT">
 225       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 226           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 227             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 228           </reg>
 229           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 230             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 231           </reg>
 232         </registers>
 233     </module>
 234     <module class="EEPROM">
 235       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 236           <reg size="1" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0xFF"/>
 237           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 238           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 239             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 240             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 241             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 242             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 243           </reg>
 244         </registers>
 245     </module>
 246     <module class="PORTB">
 247       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 248           <reg size="1" name="PORTB" offset="0x38" text="Data Register, Port B" icon="io_port.bmp" mask="0x3F"/>
 249           <reg size="1" name="DDRB" offset="0x37" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x3F"/>
 250           <reg size="1" name="PINB" offset="0x36" text="Input Pins, Port B" icon="io_port.bmp" mask="0x3F"/>
 251         </registers>
 252     </module>
 253     <module class="PORTC">
 254       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 255           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0x3F"/>
 256           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0x3F"/>
 257           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0x3F"/>
 258         </registers>
 259     </module>
 260     <module class="PORTD">
 261       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 262           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 263           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 264           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 265         </registers>
 266     </module>
 267     <module class="TIMER_COUNTER_0">
 268       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 269           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 270             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 271           </reg>
 272           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 273             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 274           </reg>
 275           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 276             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon="" enum="CLK_SEL_3BIT_EXT"/>
 277             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 278             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
 279           </reg>
 280           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 281         </registers>
 282     </module>
 283     <module class="TIMER_COUNTER_1">
 284       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 285           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 286             <bitfield name="TOIE1" mask="0x80" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 287             <bitfield name="OCIE1" mask="0x40" text="Timer/Counter1 Output Compare Match Interrupt Enable" icon=""/>
 288             <bitfield name="TICIE1" mask="0x08" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 289           </reg>
 290           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 291             <bitfield name="TOV1" mask="0x80" text="Timer/Counter1 Overflow Flag" icon=""/>
 292             <bitfield name="OCF1" mask="0x40" text="Output Compare Flag 1" icon=""/>
 293             <bitfield name="ICF1" mask="0x08" text="Input Capture Flag 1" icon=""/>
 294           </reg>
 295           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 296             <bitfield name="COM1" mask="0xC0" text="Compare Output Mode 1, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 297             <bitfield name="PWM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon="" enum="PULSE_WIDTH_MODU"/>
 298           </reg>
 299           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 300             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 301             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 302             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 303             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 304           </reg>
 305           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 306           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 307           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 308         </registers>
 309     </module>
 310     <module class="WATCHDOG">
 311       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 312           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 313             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 314             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 315             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 316           </reg>
 317         </registers>
 318     </module>
 319   </hardware>
 320 </device>