devices/at90s2313

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="11">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$002" name="INT1">External Interrupt Request 1</interrupt>
   8     <interrupt vector="4" address="$003" name="TIMER1 CAPT1">Timer/Counter1 Capture Event</interrupt>
   9     <interrupt vector="5" address="$004" name="TIMER1 COMP1">Timer/Counter1 Compare Match</interrupt>
  10     <interrupt vector="6" address="$005" name="TIMER1 OVF1">Timer/Counter1 Overflow</interrupt>
  11     <interrupt vector="7" address="$006" name="TIMER0 OVF0">Timer/Counter0 Overflow</interrupt>
  12     <interrupt vector="8" address="$007" name="UART, RX">UART, Rx Complete</interrupt>
  13     <interrupt vector="9" address="$008" name="UART, UDRE">UART Data Register Empty</interrupt>
  14     <interrupt vector="10" address="$009" name="UART, TX">UART, Tx Complete</interrupt>
  15     <interrupt vector="11" address="$00A" name="ANA COMP">Analog Comparator</interrupt>
  16   </interrupts>
  17   <packages/>
  18   <memory>
  19     <flash size="2048"/>
  20     <iospace start="$20" stop="$5F"/>
  21     <sram size="128"/>
  22     <eram size="0"/>
  23   </memory>
  24   <ioregisters>
  25     <ioreg name="ACSR" address="$08"/>
  26     <ioreg name="UBRR" address="$09"/>
  27     <ioreg name="UCR" address="$0A"/>
  28     <ioreg name="USR" address="$0B"/>
  29     <ioreg name="UDR" address="$0C"/>
  30     <ioreg name="PIND" address="$10"/>
  31     <ioreg name="DDRD" address="$11"/>
  32     <ioreg name="PORTD" address="$12"/>
  33     <ioreg name="PINB" address="$16"/>
  34     <ioreg name="DDRB" address="$17"/>
  35     <ioreg name="PORTB" address="$18"/>
  36     <ioreg name="EECR" address="$1C"/>
  37     <ioreg name="EEDR" address="$1D"/>
  38     <ioreg name="EEAR" address="$1E"/>
  39     <ioreg name="WDTCR" address="$21"/>
  40     <ioreg name="ICR1L" address="$24"/>
  41     <ioreg name="ICR1H" address="$25"/>
  42     <ioreg name="OCR1AL" address="$2A"/>
  43     <ioreg name="OCR1AH" address="$2B"/>
  44     <ioreg name="TCNT1L" address="$2C"/>
  45     <ioreg name="TCNT1H" address="$2D"/>
  46     <ioreg name="TCCR1B" address="$2E"/>
  47     <ioreg name="TCCR1A" address="$2F"/>
  48     <ioreg name="TCNT0" address="$32"/>
  49     <ioreg name="TCCR0" address="$33"/>
  50     <ioreg name="MCUCR" address="$35"/>
  51     <ioreg name="TIFR" address="$38"/>
  52     <ioreg name="TIMSK" address="$39"/>
  53     <ioreg name="GIFR" address="$3A"/>
  54     <ioreg name="GIMSK" address="$3B"/>
  55     <ioreg name="SPL" address="$3D"/>
  56     <ioreg name="SREG" address="$3F"/>
  57   </ioregisters>
  58   <hardware>
  59 <!--Everything after this needs editing!!!-->
  60     <module class="FUSE">
  61       <registers name="FUSE" memspace="FUSE">
  62           <reg size="1" name="LOW" offset="0x00">
  63             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
  64             <bitfield name="FSTRT" mask="0x01" text="Short start-up time enabled" icon=""/>
  65           </reg>
  66         </registers>
  67     </module>
  68     <module class="LOCKBIT">
  69       <registers name="LOCKBIT" memspace="LOCKBIT">
  70           <reg size="1" name="LOCKBIT" offset="0x00">
  71             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
  72           </reg>
  73         </registers>
  74     </module>
  75     <module class="PORTB">
  76       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
  77           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
  78           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
  79           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
  80         </registers>
  81     </module>
  82     <module class="TIMER_COUNTER_0">
  83       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
  84           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
  85             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
  86           </reg>
  87           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
  88             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
  89           </reg>
  90           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
  91             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon="" enum="CLK_SEL_3BIT_EXT"/>
  92             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
  93             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
  94           </reg>
  95           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
  96         </registers>
  97     </module>
  98     <module class="TIMER_COUNTER_1">
  99       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 100           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 101             <bitfield name="TOIE1" mask="0x80" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 102             <bitfield name="OCIE1A" mask="0x40" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 103             <bitfield name="TICIE1" mask="0x08" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 104           </reg>
 105           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 106             <bitfield name="TOV1" mask="0x80" text="Timer/Counter1 Overflow Flag" icon=""/>
 107             <bitfield name="OCF1A" mask="0x40" text="Output Compare Flag 1A" icon=""/>
 108             <bitfield name="ICF1" mask="0x08" text="Input Capture Flag 1" icon=""/>
 109           </reg>
 110           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 111             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 112             <bitfield name="PWM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon="" enum="PULSE_WIDTH_MODU"/>
 113           </reg>
 114           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 115             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 116             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 117             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 118             <bitfield name="CS1" mask="0x07" text="Clock Select1 bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 119           </reg>
 120           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 121           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 122           <reg size="2" name="ICR1" offset="0x44" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 123         </registers>
 124     </module>
 125     <module class="WATCHDOG">
 126       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 127           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 128             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 129             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 130             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 131           </reg>
 132         </registers>
 133     </module>
 134     <module class="EXTERNAL_INTERRUPT">
 135       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 136           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 137             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 138           </reg>
 139           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 140             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 141           </reg>
 142         </registers>
 143     </module>
 144     <module class="UART">
 145       <registers name="UART" memspace="DATAMEM" text="" icon="io_com.bmp">
 146           <reg size="1" name="UDR" offset="0x2C" text="UART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 147           <reg size="1" name="USR" offset="0x2B" text="UART Status Register" icon="io_flag.bmp">
 148             <bitfield name="RXC" mask="0x80" text="UART Receive Complete" icon=""/>
 149             <bitfield name="TXC" mask="0x40" text="UART Transmit Complete" icon=""/>
 150             <bitfield name="UDRE" mask="0x20" text="UART Data Register Empty" icon=""/>
 151             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 152             <bitfield name="OR" mask="0x08" text="Overrun" icon=""/>
 153           </reg>
 154           <reg size="1" name="UCR" offset="0x2A" text="UART Control Register" icon="io_flag.bmp">
 155             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 156             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 157             <bitfield name="UDRIE" mask="0x20" text="UART Data Register Empty Interrupt Enable" icon=""/>
 158             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 159             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 160             <bitfield name="CHR9" mask="0x04" text="9-bit Characters" icon=""/>
 161             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 162             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 163           </reg>
 164           <reg size="1" name="UBRR" offset="0x29" text="UART BAUD Rate Register" icon="io_com.bmp" mask="0xFF"/>
 165         </registers>
 166     </module>
 167     <module class="ANALOG_COMPARATOR">
 168       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 169           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 170             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 171             <bitfield name="ACO" mask="0x20" text="Analog Comparator Output" icon=""/>
 172             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 173             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 174             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 175             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 176           </reg>
 177         </registers>
 178     </module>
 179     <module class="CPU">
 180       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 181           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 182             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 183             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 184             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 185             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 186             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 187             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 188             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 189             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 190           </reg>
 191           <reg size="1" name="SPL" offset="0x5D" text="Stack Pointer Low" icon="io_sph.bmp" mask="0xFF"/>
 192           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 193             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 194             <bitfield name="SM" mask="0x10" text="Sleep Mode" icon=""/>
 195             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 196             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon=""/>
 197           </reg>
 198         </registers>
 199     </module>
 200     <module class="PORTD">
 201       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 202           <reg size="1" name="PORTD" offset="0x32" text="Data Register, Port D" icon="io_port.bmp" mask="0x7F"/>
 203           <reg size="1" name="DDRD" offset="0x31" text="Data Direction Register, Port D" icon="io_flag.bmp" mask="0x7F"/>
 204           <reg size="1" name="PIND" offset="0x30" text="Input Pins, Port D" icon="io_port.bmp" mask="0x7F"/>
 205         </registers>
 206     </module>
 207     <module class="EEPROM">
 208       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 209           <reg size="1" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x7F"/>
 210           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 211           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 212             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 213             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 214             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 215           </reg>
 216         </registers>
 217     </module>
 218   </hardware>
 219 </device>