devices/at90can32

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <packages>
   5     <package name="TQFP" pins="64">
   6       <pin id="1" name="['PEN]"/>
   7       <pin id="2" name="[PE0:RXD0:PDI]">PDI, Serial Programming Data Input. During Serial Program Downloading, this pin is used as data input line for the ATmega104. RXD0, USART0 Receive Pin. Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDRE0. When the USART0 forces this pin to be an input, a logical one in PORTE0 will turn on the internal pull-up.</pin>
   8       <pin id="3" name="[PE1:TXD0:PDO]">PDO, Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the ATmega104. TXD0, UART0 Transmit Pin.</pin>
   9       <pin id="4" name="[PE2:XCK0:AIN0]">AIN0 - Analog Comparator Positive Input. This pin is directly connected to the positive input of the analog comparator. XCK0, USART0 external clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK0 pin is active only when the USART0 operates in synchronous mode.</pin>
  10       <pin id="5" name="[PE3:OC3A:AIN1]">AIN1 - Analog Comparator Negative Input. This pin is directly connected to the negative input of the analog comparator. OC3A, Output Compare matchA output: The PE3 pin can serve as an external output for the Timer/Counter3 output com-pareA. The pin has to be configured as an output (DDE3 set (one)) to serve this function. The OC3A pin is also the output pin for the PWM mode timer function.</pin>
  11       <pin id="6" name="[PE4:OC3B:INT4]">INT4, External Interrupt source 4: The PE4 pin can serve as an external interrupt source. OC3B, Output Compare matchB output: The PE4 pin can serve as an external output for the Timer/Counter3 output com-pareB. The pin has to be configured as an output (DDE4 set (one)) to serve this function. The OC3B pin is also the output pin for the PWM mode timer function.</pin>
  12       <pin id="7" name="[PE5:OC3C:INT5]">INT5, External Interrupt source 5: The PE5 pin can serve as an external interrupt source. OC3C, Output Compare matchC output: The PE5 pin can serve as an external output for the Timer/Counter3 output com-pareC. The pin has to be configured as an output (DDE5 set (one)) to serve this function. The OC3C pin is also the output pin for the PWM mode timer function.</pin>
  13       <pin id="8" name="[PE6:T3:INT6]">INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. T3, Timer/Counter3 counter source.</pin>
  14       <pin id="9" name="[PE7:IC3:INT7]">INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. IC3 - Input Capture Pin3: The PE7 pin can act as an input capture pin for Timer/Counter3.</pin>
  15       <pin id="10" name="[PB0:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.</pin>
  16       <pin id="11" name="[PB1:SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.</pin>
  17       <pin id="12" name="[PB2:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.</pin>
  18       <pin id="13" name="[PB3:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB3. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB3 bit.</pin>
  19       <pin id="14" name="[PB4:OC0:PWM0]">OC0, Output Compare match output: The PB4 pin can serve as an external output for the Timer/Counter0 output compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function.</pin>
  20       <pin id="15" name="[PB5:OC1A:PWM1A]">OC1A, Output Compare matchA output: The PB5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDB5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
  21       <pin id="16" name="[PB6:OC1B:PWM1B]">OC1B, Output Compare matchB output: The PB6 pin can serve as an external output for the Timer/Counter1 output compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
  22       <pin id="17" name="[PB7:OC2:PWM2:OC1C]">OC2, Output Compare match output: The PB7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDB7 set (one)) to serve this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
  23       <pin id="18" name="[PG3:TOSC2]">TOSC2, Timer Oscillator pin 2: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG3 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.</pin>
  24       <pin id="19" name="[PG4:TOSC1]">TOSC1, Timer Oscillator pin 1: When the AS0 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter0, pin PG4 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.</pin>
  25       <pin id="20" name="['RESET]"/>
  26       <pin id="21" name="[VCC]"/>
  27       <pin id="22" name="[GND]"/>
  28       <pin id="23" name="[XTAL2]"/>
  29       <pin id="24" name="[XTAL1]"/>
  30       <pin id="25" name="[PD0:SCL:INT0]">INT0, External Interrupt source 0. The PD0 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation</pin>
  31       <pin id="26" name="[PD1:SDA:INT1]">INT1, External Interrupt source 1. The PD1 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is aspike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitati</pin>
  32       <pin id="27" name="[PD2:RXD1:INT2]">INT2, External Interrupt source 2. The PD2 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bi</pin>
  33       <pin id="28" name="[PD3:TXD1:INT3]">INT3, External Interrupt source 3. The PD3 pin can serve as external active low interrupt source to the MCU. The internal pull up MOS resistors can be activated as described above. See the interrupt description for further details, and how to enable the source. TXD1, Transmit Data (Data output pin for the USART1). When the USART1 transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.</pin>
  34       <pin id="29" name="[PD4:IC1]">IC1 - Input Capture Pin1: The PD4 pin can act as an input capture pin for Timer/Counter1.</pin>
  35       <pin id="30" name="[PD5:XCK1]">XCK1, USART1 external clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK1 pin is active only when the USART1 operates in synchronous mode.</pin>
  36       <pin id="31" name="[PD6:T1]">T1, Timer/Counter1 counter source.</pin>
  37       <pin id="32" name="[PD7:T2]">T2, Timer/Counter2 counter source.</pin>
  38       <pin id="33" name="[PG0:'WR]">WR is the external data memory write control strobe.</pin>
  39       <pin id="34" name="[PG1:'RD]">RD is the external data memory read control strobe.</pin>
  40       <pin id="35" name="[PC0:A8]"/>
  41       <pin id="36" name="[PC1:A9]"/>
  42       <pin id="37" name="[PC2:A10]"/>
  43       <pin id="38" name="[PC3:A11]"/>
  44       <pin id="39" name="[PC4:A12]"/>
  45       <pin id="40" name="[PC5:A13]"/>
  46       <pin id="41" name="[PC6:A14]"/>
  47       <pin id="42" name="[PC7:A15]"/>
  48       <pin id="43" name="[PG2:ALE]">ALE is the external data memory Address Latch Enable signal.</pin>
  49       <pin id="44" name="[PA7:AD7]"/>
  50       <pin id="45" name="[PA6:AD6]"/>
  51       <pin id="46" name="[PA5:AD5]"/>
  52       <pin id="47" name="[PA4:AD4]"/>
  53       <pin id="48" name="[PA3:AD3]"/>
  54       <pin id="49" name="[PA2:AD2]"/>
  55       <pin id="50" name="[PA1:AD1]"/>
  56       <pin id="51" name="[PA0:AD0]"/>
  57       <pin id="52" name="[VCC]"/>
  58       <pin id="53" name="[GND]"/>
  59       <pin id="54" name="[PF7:ADC7:TDI]">ADC7, Analog to Digital Converter, channel 7. TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.</pin>
  60       <pin id="55" name="[PF6:ADC6:TD0]">ADC6, Analog to Digital Converter, channel 6. TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.</pin>
  61       <pin id="56" name="[PF5:ADC5:TMS]">ADC5, Analog to Digital Converter, channel 5. TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.</pin>
  62       <pin id="57" name="[PF4:ADC4:TCK]">ADC4, Analog to Digital Converter, channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.</pin>
  63       <pin id="58" name="[PF3:ADC3]">Analog to Digital Converter, Channel 3</pin>
  64       <pin id="59" name="[PF2:ADC2]">Analog to Digital Converter, Channel 2</pin>
  65       <pin id="60" name="[PF1:ADC1]">Analog to Digital Converter, Channel 1</pin>
  66       <pin id="61" name="[PF0:ADC0]">Analog to Digital Converter, Channel 0</pin>
  67       <pin id="62" name="[AREF]"/>
  68       <pin id="63" name="[GND]"/>
  69       <pin id="64" name="[AVCC]"/>
  70     </package>
  71   </packages>
  72   <interrupts num="37">
  73     <interrupt vector="1" address="$0000" name="RESET">External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</interrupt>
  74     <interrupt vector="2" address="$0002" name="INT0">External Interrupt Request 0</interrupt>
  75     <interrupt vector="3" address="$0004" name="INT1">External Interrupt Request 1</interrupt>
  76     <interrupt vector="4" address="$0006" name="INT2">External Interrupt Request 2</interrupt>
  77     <interrupt vector="5" address="$0008" name="INT3">External Interrupt Request 3</interrupt>
  78     <interrupt vector="6" address="$000A" name="INT4">External Interrupt Request 4</interrupt>
  79     <interrupt vector="7" address="$000C" name="INT5">External Interrupt Request 5</interrupt>
  80     <interrupt vector="8" address="$000E" name="INT6">External Interrupt Request 6</interrupt>
  81     <interrupt vector="9" address="$0010" name="INT7">External Interrupt Request 7</interrupt>
  82     <interrupt vector="10" address="$0012" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
  83     <interrupt vector="11" address="$0014" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  84     <interrupt vector="12" address="$0016" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  85     <interrupt vector="13" address="$0018" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  86     <interrupt vector="14" address="$001A" name="TIMER1 COMPB">Timer/Counter Compare Match B</interrupt>
  87     <interrupt vector="15" address="$001C" name="TIMER1 COMPC">Timer/Counter1 Compare Match C</interrupt>
  88     <interrupt vector="16" address="$001E" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  89     <interrupt vector="17" address="$0020" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
  90     <interrupt vector="18" address="$0022" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  91     <interrupt vector="19" address="$0024" name="CANIT">CAN Transfer Complete or Error</interrupt>
  92     <interrupt vector="20" address="$0026" name="OVRIT">CAN Timer Overrun</interrupt>
  93     <interrupt vector="21" address="$0028" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
  94     <interrupt vector="22" address="$002A" name="USART0, RX">USART0, Rx Complete</interrupt>
  95     <interrupt vector="23" address="$002C" name="USART0, UDRE">USART0 Data Register Empty</interrupt>
  96     <interrupt vector="24" address="$002E" name="USART0, TX">USART0, Tx Complete</interrupt>
  97     <interrupt vector="25" address="$0030" name="ANALOG COMP">Analog Comparator</interrupt>
  98     <interrupt vector="26" address="$0032" name="ADC">ADC Conversion Complete</interrupt>
  99     <interrupt vector="27" address="$0034" name="EE READY">EEPROM Ready</interrupt>
 100     <interrupt vector="28" address="$0036" name="TIMER3 CAPT">Timer/Counter3 Capture Event</interrupt>
 101     <interrupt vector="29" address="$0038" name="TIMER3 COMPA">Timer/Counter3 Compare Match A</interrupt>
 102     <interrupt vector="30" address="$003A" name="TIMER3 COMPB">Timer/Counter3 Compare Match B</interrupt>
 103     <interrupt vector="31" address="$003C" name="TIMER3 COMPC">Timer/Counter3 Compare Match C</interrupt>
 104     <interrupt vector="32" address="$003E" name="TIMER3 OVF">Timer/Counter3 Overflow</interrupt>
 105     <interrupt vector="33" address="$0040" name="USART1, RX">USART1, Rx Complete</interrupt>
 106     <interrupt vector="34" address="$0042" name="USART1, UDRE">USART1, Data Register Empty</interrupt>
 107     <interrupt vector="35" address="$0044" name="USART1, TX">USART1, Tx Complete</interrupt>
 108     <interrupt vector="36" address="$0046" name="TWI">2-wire Serial Interface</interrupt>
 109     <interrupt vector="37" address="$0048" name="SPM READY">Store Program Memory Read</interrupt>
 110   </interrupts>
 111   <memory>
 112     <flash size="32768"/>
 113     <iospace start="$0020" stop="$00FF"/>
 114     <sram size="2048"/>
 115     <eram size="65536"/>
 116   </memory>
 117   <ioregisters>
 118     <ioreg name="PINA" address="$00"/>
 119     <ioreg name="DDRA" address="$01"/>
 120     <ioreg name="PORTA" address="$02"/>
 121     <ioreg name="PINB" address="$03"/>
 122     <ioreg name="DDRB" address="$04"/>
 123     <ioreg name="PORTB" address="$05"/>
 124     <ioreg name="PINC" address="$06"/>
 125     <ioreg name="DDRC" address="$07"/>
 126     <ioreg name="PORTC" address="$08"/>
 127     <ioreg name="PIND" address="$09"/>
 128     <ioreg name="DDRD" address="$0A"/>
 129     <ioreg name="PORTD" address="$0B"/>
 130     <ioreg name="PINE" address="$0C"/>
 131     <ioreg name="DDRE" address="$0D"/>
 132     <ioreg name="PORTE" address="$0E"/>
 133     <ioreg name="PINF" address="$0F"/>
 134     <ioreg name="DDRF" address="$10"/>
 135     <ioreg name="PORTF" address="$11"/>
 136     <ioreg name="PING" address="$12"/>
 137     <ioreg name="DDRG" address="$13"/>
 138     <ioreg name="PORTG" address="$14"/>
 139     <ioreg name="TIFR0" address="$15"/>
 140     <ioreg name="TIFR1" address="$16"/>
 141     <ioreg name="TIFR2" address="$17"/>
 142     <ioreg name="TIFR3" address="$18"/>
 143     <ioreg name="EIFR" address="$1C"/>
 144     <ioreg name="EIMSK" address="$1D"/>
 145     <ioreg name="GPIOR0" address="$1E"/>
 146     <ioreg name="EECR" address="$1F"/>
 147     <ioreg name="EEDR" address="$20"/>
 148     <ioreg name="EEARL" address="$21"/>
 149     <ioreg name="EEARH" address="$22"/>
 150     <ioreg name="GTCCR" address="$23"/>
 151     <ioreg name="TCCR0A" address="$24"/>
 152     <ioreg name="TCNT0" address="$26"/>
 153     <ioreg name="OCR0A" address="$27"/>
 154     <ioreg name="GPIOR1" address="$2A"/>
 155     <ioreg name="GPIOR2" address="$2B"/>
 156     <ioreg name="SPCR" address="$2C"/>
 157     <ioreg name="SPSR" address="$2D"/>
 158     <ioreg name="SPDR" address="$2E"/>
 159     <ioreg name="ACSR" address="$30"/>
 160     <ioreg name="OCDR" address="$31"/>
 161     <ioreg name="SMCR" address="$33"/>
 162     <ioreg name="MCUSR" address="$34"/>
 163     <ioreg name="MCUCR" address="$35"/>
 164     <ioreg name="SPMCSR" address="$37"/>
 165     <ioreg name="SPL" address="$3D"/>
 166     <ioreg name="SPH" address="$3E"/>
 167     <ioreg name="SREG" address="$3F"/>
 168     <ioreg name="WDTCR" address="$60"/>
 169     <ioreg name="CLKPR" address="$61"/>
 170     <ioreg name="PRR" address="$64"/>
 171     <ioreg name="OSCCAL" address="$66"/>
 172     <ioreg name="EICRA" address="$69"/>
 173     <ioreg name="EICRB" address="$6A"/>
 174     <ioreg name="TIMSK0" address="$6E"/>
 175     <ioreg name="TIMSK1" address="$6F"/>
 176     <ioreg name="TIMSK2" address="$70"/>
 177     <ioreg name="TIMSK3" address="$71"/>
 178     <ioreg name="ADCL" address="$78"/>
 179     <ioreg name="ADCH" address="$79"/>
 180     <ioreg name="ADCSRA" address="$7A"/>
 181     <ioreg name="ADCSRB" address="$7B"/>
 182     <ioreg name="ADMUX" address="$7C"/>
 183     <ioreg name="DIDR0" address="$7E"/>
 184     <ioreg name="DIDR1" address="$7F"/>
 185     <ioreg name="TCCR1A" address="$80"/>
 186     <ioreg name="TCCR1B" address="$81"/>
 187     <ioreg name="TCCR1C" address="$82"/>
 188     <ioreg name="TCNT1L" address="$84"/>
 189     <ioreg name="TCNT1H" address="$85"/>
 190     <ioreg name="ICR1L" address="$86"/>
 191     <ioreg name="ICR1H" address="$87"/>
 192     <ioreg name="OCR1AL" address="$88"/>
 193     <ioreg name="OCR1AH" address="$89"/>
 194     <ioreg name="OCR1BL" address="$8A"/>
 195     <ioreg name="OCR1BH" address="$8B"/>
 196     <ioreg name="OCR1CL" address="$8C"/>
 197     <ioreg name="OCR1CH" address="$8D"/>
 198     <ioreg name="TCCR3A" address="$90"/>
 199     <ioreg name="TCCR3B" address="$91"/>
 200     <ioreg name="TCCR3C" address="$92"/>
 201     <ioreg name="TCNT3L" address="$94"/>
 202     <ioreg name="TCNT3H" address="$95"/>
 203     <ioreg name="ICR3L" address="$96"/>
 204     <ioreg name="ICR3H" address="$97"/>
 205     <ioreg name="OCR3AL" address="$98"/>
 206     <ioreg name="OCR3AH" address="$99"/>
 207     <ioreg name="OCR3BL" address="$9A"/>
 208     <ioreg name="OCR3BH" address="$9B"/>
 209     <ioreg name="OCR3CL" address="$9C"/>
 210     <ioreg name="OCR3CH" address="$9D"/>
 211     <ioreg name="TCCR2A" address="$B0"/>
 212     <ioreg name="TCNT2" address="$B2"/>
 213     <ioreg name="OCR2A" address="$B3"/>
 214     <ioreg name="ASSR" address="$B6"/>
 215     <ioreg name="RAMPZ" address="0x3B"/>
 216     <ioreg name="XMCRA" address="0x74"/>
 217     <ioreg name="XMCRB" address="0x75"/>
 218     <ioreg name="TWBR" address="0xB8"/>
 219     <ioreg name="TWSR" address="0xB9"/>
 220     <ioreg name="TWAR" address="0xBA"/>
 221     <ioreg name="TWDR" address="0xBB"/>
 222     <ioreg name="TWCR" address="0xBC"/>
 223     <ioreg name="UCSR0A" address="0xC0"/>
 224     <ioreg name="UCSR0B" address="0xC1"/>
 225     <ioreg name="UCSR0C" address="0xC2"/>
 226     <ioreg name="UBRR0L" address="0xC4"/>
 227     <ioreg name="UBRR0H" address="0xC5"/>
 228     <ioreg name="UDR0" address="0xC6"/>
 229     <ioreg name="UCSR1A" address="0xC8"/>
 230     <ioreg name="UCSR1B" address="0xC9"/>
 231     <ioreg name="UCSR1C" address="0xCA"/>
 232     <ioreg name="UBRR1L" address="0xCC"/>
 233     <ioreg name="UBRR1H" address="0xCD"/>
 234     <ioreg name="UDR1" address="0xCE"/>
 235     <ioreg name="CANGCON" address="0xD8"/>
 236     <ioreg name="CANGSTA" address="0xD9"/>
 237     <ioreg name="CANGIT" address="0xDA"/>
 238     <ioreg name="CANGIE" address="0xDB"/>
 239     <ioreg name="CANEN2" address="0xDC"/>
 240     <ioreg name="CANEN1" address="0xDD"/>
 241     <ioreg name="CANIE2" address="0xDE"/>
 242     <ioreg name="CANIE1" address="0xDF"/>
 243     <ioreg name="CANSIT2" address="0xE0"/>
 244     <ioreg name="CANSIT1" address="0xE1"/>
 245     <ioreg name="CANBT1" address="0xE2"/>
 246     <ioreg name="CANBT2" address="0xE3"/>
 247     <ioreg name="CANBT3" address="0xE4"/>
 248     <ioreg name="CANTCON" address="0xE5"/>
 249     <ioreg name="CANTIML" address="0xE6"/>
 250     <ioreg name="CANTIMH" address="0xE7"/>
 251     <ioreg name="CANTTCL" address="0xE8"/>
 252     <ioreg name="CANTTCH" address="0xE9"/>
 253     <ioreg name="CANTEC" address="0xEA"/>
 254     <ioreg name="CANREC" address="0xEB"/>
 255     <ioreg name="CANHPMOB" address="0xEC"/>
 256     <ioreg name="CANPAGE" address="0xED"/>
 257     <ioreg name="CANSTMOB" address="0xEE"/>
 258     <ioreg name="CANCDMOB" address="0xEF"/>
 259     <ioreg name="CANIDT4" address="0xF0"/>
 260     <ioreg name="CANIDT3" address="0xF1"/>
 261     <ioreg name="CANIDT2" address="0xF2"/>
 262     <ioreg name="CANIDT1" address="0xF3"/>
 263     <ioreg name="CANIDM4" address="0xF4"/>
 264     <ioreg name="CANIDM3" address="0xF5"/>
 265     <ioreg name="CANIDM2" address="0xF6"/>
 266     <ioreg name="CANIDM1" address="0xF7"/>
 267     <ioreg name="CANSTML" address="0xF8"/>
 268     <ioreg name="CANSTMH" address="0xF9"/>
 269     <ioreg name="CANMSG" address="0xFA"/>
 270   </ioregisters>
 271   <hardware>
 272 <!--Everything after this needs editing!!!-->
 273     <module class="FUSE">
 274       <registers name="FUSE" memspace="FUSE">
 275           <reg size="1" name="EXTENDED" offset="0x02">
 276             <bitfield name="BODLEVEL" mask="0x0E" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 277             <bitfield name="TA0SEL" mask="0x01" text="Reserved for factory tests" icon=""/>
 278           </reg>
 279           <reg size="1" name="HIGH" offset="0x01">
 280             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 281             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 282             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 283             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 284             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 285             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 286             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 287           </reg>
 288           <reg size="1" name="LOW" offset="0x00">
 289             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 290             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTC7" icon=""/>
 291             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 292           </reg>
 293         </registers>
 294     </module>
 295     <module class="LOCKBIT">
 296       <registers name="LOCKBIT" memspace="LOCKBIT">
 297           <reg size="1" name="LOCKBIT" offset="0x00">
 298             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 299             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 300             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 301           </reg>
 302         </registers>
 303     </module>
 304     <module class="PORTA">
 305       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 306           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 307           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 308           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 309         </registers>
 310     </module>
 311     <module class="PORTB">
 312       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 313           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 314           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 315           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 316         </registers>
 317     </module>
 318     <module class="PORTC">
 319       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 320           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 321           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 322           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 323         </registers>
 324     </module>
 325     <module class="PORTD">
 326       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 327           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 328           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 329           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 330         </registers>
 331     </module>
 332     <module class="PORTE">
 333       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 334           <reg size="1" name="PORTE" offset="0x2E" text="Data Register, Port E" icon="io_port.bmp" mask="0xFF"/>
 335           <reg size="1" name="DDRE" offset="0x2D" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0xFF"/>
 336           <reg size="1" name="PINE" offset="0x2C" text="Input Pins, Port E" icon="io_port.bmp" mask="0xFF"/>
 337         </registers>
 338     </module>
 339     <module class="PORTF">
 340       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 341           <reg size="1" name="PORTF" offset="0x31" text="Data Register, Port F" icon="io_port.bmp" mask="0xFF"/>
 342           <reg size="1" name="DDRF" offset="0x30" text="Data Direction Register, Port F" icon="io_flag.bmp" mask="0xFF"/>
 343           <reg size="1" name="PINF" offset="0x2F" text="Input Pins, Port F" icon="io_port.bmp" mask="0xFF"/>
 344         </registers>
 345     </module>
 346     <module class="PORTG">
 347       <registers name="PORTG" memspace="DATAMEM" text="" icon="io_port.bmp">
 348           <reg size="1" name="PORTG" offset="0x34" text="Data Register, Port G" icon="io_port.bmp" mask="0x1F"/>
 349           <reg size="1" name="DDRG" offset="0x33" text="Data Direction Register, Port G" icon="io_flag.bmp" mask="0x1F"/>
 350           <reg size="1" name="PING" offset="0x32" text="Input Pins, Port G" icon="io_port.bmp" mask="0x1F"/>
 351         </registers>
 352     </module>
 353     <module class="JTAG">
 354       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 355           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp" mask="0xFF"/>
 356           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 357             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 358           </reg>
 359           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 360             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 361           </reg>
 362         </registers>
 363     </module>
 364     <module class="SPI">
 365       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 366           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 367             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 368             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 369             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 370             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 371             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 372             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 373             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 374           </reg>
 375           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 376             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 377             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 378             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 379           </reg>
 380           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 381         </registers>
 382     </module>
 383     <module class="TWI">
 384       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 385           <reg size="1" name="TWBR" offset="0xB8" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 386           <reg size="1" name="TWCR" offset="0xBC" text="TWI Control Register" icon="io_flag.bmp">
 387             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 388             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 389             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 390             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 391             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 392             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 393             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 394           </reg>
 395           <reg size="1" name="TWSR" offset="0xB9" text="TWI Status Register" icon="io_flag.bmp">
 396             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 397             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 398           </reg>
 399           <reg size="1" name="TWDR" offset="0xBB" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 400           <reg size="1" name="TWAR" offset="0xBA" text="TWI (Slave) Address register" icon="io_com.bmp">
 401             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 402             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 403           </reg>
 404         </registers>
 405     </module>
 406     <module class="USART0">
 407       <registers name="USART0" memspace="DATAMEM" text="" icon="io_com.bmp">
 408           <reg size="1" name="UDR0" offset="0xC6" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 409           <reg size="1" name="UCSR0A" offset="0xC0" text="USART Control and Status Register A" icon="io_flag.bmp">
 410             <bitfield name="RXC0" mask="0x80" text="USART Receive Complete" icon=""/>
 411             <bitfield name="TXC0" mask="0x40" text="USART Transmitt Complete" icon=""/>
 412             <bitfield name="UDRE0" mask="0x20" text="USART Data Register Empty" icon=""/>
 413             <bitfield name="FE0" mask="0x10" text="Framing Error" icon=""/>
 414             <bitfield name="DOR0" mask="0x08" text="Data overRun" icon=""/>
 415             <bitfield name="UPE0" mask="0x04" text="Parity Error" icon=""/>
 416             <bitfield name="U2X0" mask="0x02" text="Double the USART transmission speed" icon=""/>
 417             <bitfield name="MPCM0" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 418           </reg>
 419           <reg size="1" name="UCSR0B" offset="0xC1" text="USART Control and Status Register B" icon="io_flag.bmp">
 420             <bitfield name="RXCIE0" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 421             <bitfield name="TXCIE0" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 422             <bitfield name="UDRIE0" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 423             <bitfield name="RXEN0" mask="0x10" text="Receiver Enable" icon=""/>
 424             <bitfield name="TXEN0" mask="0x08" text="Transmitter Enable" icon=""/>
 425             <bitfield name="UCSZ02" mask="0x04" text="Character Size" icon=""/>
 426             <bitfield name="RXB80" mask="0x02" text="Receive Data Bit 8" icon=""/>
 427             <bitfield name="TXB80" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 428           </reg>
 429           <reg size="1" name="UCSR0C" offset="0xC2" text="USART Control and Status Register C" icon="io_flag.bmp">
 430             <bitfield name="UMSEL0" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 431             <bitfield name="UPM0" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 432             <bitfield name="USBS0" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 433             <bitfield name="UCSZ0" mask="0x06" text="Character Size" icon=""/>
 434             <bitfield name="UCPOL0" mask="0x01" text="Clock Polarity" icon=""/>
 435           </reg>
 436           <reg size="2" name="UBRR0" offset="0xC4" text="USART Baud Rate Register t Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 437         </registers>
 438     </module>
 439     <module class="USART1">
 440       <registers name="USART1" memspace="DATAMEM" text="" icon="io_com.bmp">
 441           <reg size="1" name="UDR1" offset="0xCE" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 442           <reg size="1" name="UCSR1A" offset="0xC8" text="USART Control and Status Register A" icon="io_flag.bmp">
 443             <bitfield name="RXC1" mask="0x80" text="USART Receive Complete" icon=""/>
 444             <bitfield name="TXC1" mask="0x40" text="USART Transmitt Complete" icon=""/>
 445             <bitfield name="UDRE1" mask="0x20" text="USART Data Register Empty" icon=""/>
 446             <bitfield name="FE1" mask="0x10" text="Framing Error" icon=""/>
 447             <bitfield name="DOR1" mask="0x08" text="Data overRun" icon=""/>
 448             <bitfield name="UPE1" mask="0x04" text="Parity Error" icon=""/>
 449             <bitfield name="U2X1" mask="0x02" text="Double the USART transmission speed" icon=""/>
 450             <bitfield name="MPCM1" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 451           </reg>
 452           <reg size="1" name="UCSR1B" offset="0xC9" text="USART Control and Status Register B" icon="io_flag.bmp">
 453             <bitfield name="RXCIE1" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 454             <bitfield name="TXCIE1" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 455             <bitfield name="UDRIE1" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 456             <bitfield name="RXEN1" mask="0x10" text="Receiver Enable" icon=""/>
 457             <bitfield name="TXEN1" mask="0x08" text="Transmitter Enable" icon=""/>
 458             <bitfield name="UCSZ12" mask="0x04" text="Character Size" icon=""/>
 459             <bitfield name="RXB81" mask="0x02" text="Receive Data Bit 8" icon=""/>
 460             <bitfield name="TXB81" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 461           </reg>
 462           <reg size="1" name="UCSR1C" offset="0xCA" text="USART Control and Status Register C" icon="io_flag.bmp">
 463             <bitfield name="UMSEL1" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 464             <bitfield name="UPM1" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 465             <bitfield name="USBS1" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 466             <bitfield name="UCSZ1" mask="0x06" text="Character Size" icon=""/>
 467             <bitfield name="UCPOL1" mask="0x01" text="Clock Polarity" icon=""/>
 468           </reg>
 469           <reg size="2" name="UBRR1" offset="0xCC" text="USART Baud Rate Register t Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 470         </registers>
 471     </module>
 472     <module class="CPU">
 473       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 474           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 475             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 476             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 477             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 478             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 479             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 480             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 481             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 482             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 483           </reg>
 484           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 485           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 486             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 487             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 488             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 489           </reg>
 490           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 491             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 492             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 493             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 494             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 495             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 496           </reg>
 497           <reg size="1" name="XMCRA" offset="0x74" text="External Memory Control Register A" icon="io_cpu.bmp">
 498             <bitfield name="SRE" mask="0x80" text="External SRAM Enable" icon=""/>
 499             <bitfield name="SRL" mask="0x70" text="Wait state page limit" icon="" enum="CPU_SECTOR_LIMITS_XMEM"/>
 500             <bitfield name="SRW1" mask="0x0C" text="Wait state select bit upper page" icon="" enum="CPU_WAIT_STATES"/>
 501             <bitfield name="SRW0" mask="0x03" text="Wait state select bit lower page" icon="" enum="CPU_WAIT_STATES"/>
 502           </reg>
 503           <reg size="1" name="XMCRB" offset="0x75" text="External Memory Control Register B" icon="io_cpu.bmp">
 504             <bitfield name="XMBK" mask="0x80" text="External Memory Bus Keeper Enable" icon=""/>
 505             <bitfield name="XMM" mask="0x07" text="External Memory High Mask" icon=""/>
 506           </reg>
 507           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0x7F"/>
 508           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_cpu.bmp">
 509             <bitfield name="CLKPCE" mask="0x80" text="" icon=""/>
 510             <bitfield name="CLKPS" mask="0x0F" text="" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 511           </reg>
 512           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 513             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS2"/>
 514             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 515           </reg>
 516           <reg size="1" name="RAMPZ" offset="0x5B" text="RAM Page Z Select Register - Not used." icon="io_cpu.bmp">
 517             <bitfield name="RAMPZ0" mask="0x01" text="RAM Page Z Select Register Bit 0" icon=""/>
 518           </reg>
 519           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp">
 520             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 2 bis" icon="" lsb="20"/>
 521           </reg>
 522           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp">
 523             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 1 bis" icon="" lsb="10"/>
 524           </reg>
 525           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp">
 526             <bitfield name="GPIOR07" mask="0x80" text="General Purpose IO Register 0 bit 7" icon=""/>
 527             <bitfield name="GPIOR06" mask="0x40" text="General Purpose IO Register 0 bit 6" icon=""/>
 528             <bitfield name="GPIOR05" mask="0x20" text="General Purpose IO Register 0 bit 5" icon=""/>
 529             <bitfield name="GPIOR04" mask="0x10" text="General Purpose IO Register 0 bit 4" icon=""/>
 530             <bitfield name="GPIOR03" mask="0x08" text="General Purpose IO Register 0 bit 3" icon=""/>
 531             <bitfield name="GPIOR02" mask="0x04" text="General Purpose IO Register 0 bit 2" icon=""/>
 532             <bitfield name="GPIOR01" mask="0x02" text="General Purpose IO Register 0 bit 1" icon=""/>
 533             <bitfield name="GPIOR00" mask="0x01" text="General Purpose IO Register 0 bit 0" icon=""/>
 534           </reg>
 535         </registers>
 536     </module>
 537     <module class="BOOT_LOAD">
 538       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 539           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 540             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 541             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 542             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 543             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 544             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 545             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 546             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 547           </reg>
 548         </registers>
 549     </module>
 550     <module class="EXTERNAL_INTERRUPT">
 551       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 552           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 553             <bitfield name="ISC3" mask="0xC0" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 554             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 555             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 556             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 557           </reg>
 558           <reg size="1" name="EICRB" offset="0x6A" text="External Interrupt Control Register B" icon="io_flag.bmp">
 559             <bitfield name="ISC7" mask="0xC0" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 560             <bitfield name="ISC6" mask="0x30" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 561             <bitfield name="ISC5" mask="0x0C" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 562             <bitfield name="ISC4" mask="0x03" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 563           </reg>
 564           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 565             <bitfield name="INT" mask="0xFF" text="External Interrupt Request 7 Enable" icon=""/>
 566           </reg>
 567           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 568             <bitfield name="INTF" mask="0xFF" text="External Interrupt Flags" icon=""/>
 569           </reg>
 570         </registers>
 571     </module>
 572     <module class="EEPROM">
 573       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 574           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x0FFF"/>
 575           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 576           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 577             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 578             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 579             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 580             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 581           </reg>
 582         </registers>
 583     </module>
 584     <module class="TIMER_COUNTER_0">
 585       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 586           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 587             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare" icon=""/>
 588             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 589             <bitfield name="COM0A" mask="0x30" text="Compare Match Output Modes" icon=""/>
 590             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 591             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 592           </reg>
 593           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 594           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 595           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 596             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt Enable" icon=""/>
 597             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 598           </reg>
 599           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 600             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0" icon=""/>
 601             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 602           </reg>
 603           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Control Register" icon="io_cpu.bmp">
 604             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 605             <bitfield name="PSR310" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 606           </reg>
 607         </registers>
 608     </module>
 609     <module class="TIMER_COUNTER_2">
 610       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 611           <reg size="1" name="TCCR2" offset="0xB0" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 612             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare" icon=""/>
 613             <bitfield name="WGM20" mask="0x40" text="Waveform Genration Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 614             <bitfield name="COM2A" mask="0x30" text="Compare Output Mode bits" icon=""/>
 615             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 616             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 617           </reg>
 618           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 619           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 620           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 621             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 622             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 623           </reg>
 624           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 625             <bitfield name="OCF2A" mask="0x02" text="Output Compare Flag 2" icon=""/>
 626             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 627           </reg>
 628           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_cpu.bmp">
 629             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 630           </reg>
 631           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.io">
 632             <bitfield name="EXCLK" mask="0x10" text="Enable External Clock Interrupt" icon=""/>
 633             <bitfield name="AS2" mask="0x08" text="AS2: Asynchronous Timer/Counter2" icon=""/>
 634             <bitfield name="TCN2UB" mask="0x04" text="TCN2UB: Timer/Counter2 Update Busy" icon=""/>
 635             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 636             <bitfield name="TCR2UB" mask="0x01" text="TCR2UB: Timer/Counter Control Register2 Update Busy" icon=""/>
 637           </reg>
 638         </registers>
 639     </module>
 640     <module class="TIMER_COUNTER_1">
 641       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 642           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 643             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 644             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 645             <bitfield name="COM1C" mask="0x0C" text="Compare Output Mode 1C, bits" icon=""/>
 646             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 647           </reg>
 648           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 649             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 650             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 651             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 652             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 653           </reg>
 654           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter 1 Control Register C" icon="io.flag.bmp">
 655             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare 1A" icon=""/>
 656             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare 1B" icon=""/>
 657             <bitfield name="FOC1C" mask="0x20" text="Force Output Compare 1C" icon=""/>
 658           </reg>
 659           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 660           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 661           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 662           <reg size="2" name="OCR1C" offset="0x8C" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 663           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 664           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 665             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 666             <bitfield name="OCIE1C" mask="0x08" text="Timer/Counter1 Output CompareC Match Interrupt Enable" icon=""/>
 667             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 668             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 669             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 670           </reg>
 671           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 672             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 673             <bitfield name="OCF1C" mask="0x08" text="Output Compare Flag 1C" icon=""/>
 674             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 675             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 676             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 677           </reg>
 678         </registers>
 679     </module>
 680     <module class="TIMER_COUNTER_3">
 681       <registers name="TIMER_COUNTER_3" memspace="DATAMEM" text="" icon="io_timer.bmp">
 682           <reg size="1" name="TCCR3A" offset="0x90" text="Timer/Counter3 Control Register A" icon="io_flag.bmp">
 683             <bitfield name="COM3A" mask="0xC0" text="Compare Output Mode 3A, bits" icon=""/>
 684             <bitfield name="COM3B" mask="0x30" text="Compare Output Mode 3B, bits" icon=""/>
 685             <bitfield name="COM3C" mask="0x0C" text="Compare Output Mode 3C, bits" icon=""/>
 686             <bitfield name="WGM3" mask="0x03" text="Waveform Generation Mode" icon=""/>
 687           </reg>
 688           <reg size="1" name="TCCR3B" offset="0x91" text="Timer/Counter3 Control Register B" icon="io_flag.bmp">
 689             <bitfield name="ICNC3" mask="0x80" text="Input Capture 3 Noise Canceler" icon=""/>
 690             <bitfield name="ICES3" mask="0x40" text="Input Capture 3 Edge Select" icon=""/>
 691             <bitfield name="WGM3" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 692             <bitfield name="CS3" mask="0x07" text="Prescaler source of Timer/Counter 3" icon="" enum="CLK_SEL_3BIT_EXT"/>
 693           </reg>
 694           <reg size="1" name="TCCR3C" offset="0x92" text="Timer/Counter 3 Control Register C" icon="io.flag.bmp">
 695             <bitfield name="FOC3A" mask="0x80" text="Force Output Compare 3A" icon=""/>
 696             <bitfield name="FOC3B" mask="0x40" text="Force Output Compare 3B" icon=""/>
 697             <bitfield name="FOC3C" mask="0x20" text="Force Output Compare 3C" icon=""/>
 698           </reg>
 699           <reg size="2" name="TCNT3" offset="0x94" text="Timer/Counter3  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 700           <reg size="2" name="OCR3A" offset="0x98" text="Timer/Counter3 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 701           <reg size="2" name="OCR3B" offset="0x9A" text="Timer/Counter3 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 702           <reg size="2" name="OCR3C" offset="0x9C" text="Timer/Counter3 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 703           <reg size="2" name="ICR3" offset="0x96" text="Timer/Counter3 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 704           <reg size="1" name="TIMSK3" offset="0x71" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 705             <bitfield name="ICIE3" mask="0x20" text="Timer/Counter3 Input Capture Interrupt Enable" icon=""/>
 706             <bitfield name="OCIE3C" mask="0x08" text="Timer/Counter3 Output CompareC Match Interrupt Enable" icon=""/>
 707             <bitfield name="OCIE3B" mask="0x04" text="Timer/Counter3 Output CompareB Match Interrupt Enable" icon=""/>
 708             <bitfield name="OCIE3A" mask="0x02" text="Timer/Counter3 Output CompareA Match Interrupt Enable" icon=""/>
 709             <bitfield name="TOIE3" mask="0x01" text="Timer/Counter3 Overflow Interrupt Enable" icon=""/>
 710           </reg>
 711           <reg size="1" name="TIFR3" offset="0x38" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 712             <bitfield name="ICF3" mask="0x20" text="Input Capture Flag 3" icon=""/>
 713             <bitfield name="OCF3C" mask="0x08" text="Output Compare Flag 3C" icon=""/>
 714             <bitfield name="OCF3B" mask="0x04" text="Output Compare Flag 3B" icon=""/>
 715             <bitfield name="OCF3A" mask="0x02" text="Output Compare Flag 3A" icon=""/>
 716             <bitfield name="TOV3" mask="0x01" text="Timer/Counter3 Overflow Flag" icon=""/>
 717           </reg>
 718         </registers>
 719     </module>
 720     <module class="WATCHDOG">
 721       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 722           <reg size="1" name="WDTCR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 723             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 724             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 725             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 726           </reg>
 727         </registers>
 728     </module>
 729     <module class="AD_CONVERTER">
 730       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 731           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 732             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 733             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 734             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 735           </reg>
 736           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 737             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 738             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 739             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 740             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 741             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 742             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 743           </reg>
 744           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 745           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp">
 746             <bitfield name="ADHSM" mask="0x80" text="ADC High Speed Mode" icon=""/>
 747             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon="" enum="ANALIG_ADC_AUTO_TRIGGER2"/>
 748           </reg>
 749           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 750             <bitfield name="ADC7D" mask="0x80" text="ADC7 Digital input Disable" icon=""/>
 751             <bitfield name="ADC6D" mask="0x40" text="ADC6 Digital input Disable" icon=""/>
 752             <bitfield name="ADC5D" mask="0x20" text="ADC5 Digital input Disable" icon=""/>
 753             <bitfield name="ADC4D" mask="0x10" text="ADC4 Digital input Disable" icon=""/>
 754             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 755             <bitfield name="ADC2D" mask="0x04" text="ADC2 Digital input Disable" icon=""/>
 756             <bitfield name="ADC1D" mask="0x02" text="ADC1 Digital input Disable" icon=""/>
 757             <bitfield name="ADC0D" mask="0x01" text="ADC0 Digital input Disable" icon=""/>
 758           </reg>
 759         </registers>
 760     </module>
 761     <module class="ANALOG_COMPARATOR">
 762       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 763           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_flag.bmp">
 764             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 765           </reg>
 766           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 767             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 768             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 769             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 770             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 771             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 772             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 773             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 774           </reg>
 775           <reg size="1" name="DIDR1" offset="0x7F" text="" icon="io_analo.bmp">
 776             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 777             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 778           </reg>
 779         </registers>
 780     </module>
 781     <module class="CAN">
 782       <registers name="CAN" memspace="DATAMEM" text="" icon="io_com.bmp">
 783           <reg size="1" name="CANGCON" offset="0xD8" text="CAN General Control Register" icon="register.bmp">
 784             <bitfield name="ABRQ" mask="0x80" text="Abort Request" icon=""/>
 785             <bitfield name="OVRQ" mask="0x40" text="Overload Frame Request" icon=""/>
 786             <bitfield name="TTC" mask="0x20" text="Time Trigger Communication" icon=""/>
 787             <bitfield name="SYNTTC" mask="0x10" text="Synchronization of TTC" icon=""/>
 788             <bitfield name="LISTEN" mask="0x08" text="Listening Mode" icon=""/>
 789             <bitfield name="TEST" mask="0x04" text="Test Mode" icon=""/>
 790             <bitfield name="ENASTB" mask="0x02" text="Enable / Standby" icon=""/>
 791             <bitfield name="SWRES" mask="0x01" text="Software Reset Request" icon=""/>
 792           </reg>
 793           <reg size="1" name="CANGSTA" offset="0xD9" text="CAN General Status Register" icon="io_flag.bmp">
 794             <bitfield name="OVRG" mask="0x40" text="Overload Frame Flag" icon=""/>
 795             <bitfield name="TXBSY" mask="0x10" text="Transmitter Busy" icon=""/>
 796             <bitfield name="RXBSY" mask="0x08" text="Receiver Busy" icon=""/>
 797             <bitfield name="ENFG" mask="0x04" text="Enable Flag" icon=""/>
 798             <bitfield name="BOFF" mask="0x02" text="Bus Off Mode" icon=""/>
 799             <bitfield name="ERRP" mask="0x01" text="Error Passive Mode" icon=""/>
 800           </reg>
 801           <reg size="1" name="CANGIT" offset="0xDA" text="CAN General Interrupt Register" icon="io_flag.bmp">
 802             <bitfield name="CANIT" mask="0x80" text="General Interrupt Flag" icon=""/>
 803             <bitfield name="BOFFIT" mask="0x40" text="Bus Off Interrupt Flag" icon=""/>
 804             <bitfield name="OVRTIM" mask="0x20" text="Overrun CAN Timer" icon=""/>
 805             <bitfield name="BXOK" mask="0x10" text="Burst Receive Interrupt" icon=""/>
 806             <bitfield name="SERG" mask="0x08" text="Stuff Error General" icon=""/>
 807             <bitfield name="CERG" mask="0x04" text="CRC Error General" icon=""/>
 808             <bitfield name="FERG" mask="0x02" text="Form Error General" icon=""/>
 809             <bitfield name="AERG" mask="0x01" text="Ackknowledgement Error General" icon=""/>
 810           </reg>
 811           <reg size="1" name="CANGIE" offset="0xDB" text="CAN General Interrupt Enable Register" icon="register.bmp">
 812             <bitfield name="ENIT" mask="0x80" text="Enable all Interrupts" icon=""/>
 813             <bitfield name="ENBOFF" mask="0x40" text="Enable Bus Off INterrupt" icon=""/>
 814             <bitfield name="ENRX" mask="0x20" text="Enable Receive Interrupt" icon=""/>
 815             <bitfield name="ENTX" mask="0x10" text="Enable Transmitt Interrupt" icon=""/>
 816             <bitfield name="ENERR" mask="0x08" text="Enable MOb Error Interrupt" icon=""/>
 817             <bitfield name="ENBX" mask="0x04" text="Enable Burst Receive Interrupt" icon=""/>
 818             <bitfield name="ENERG" mask="0x02" text="Enable General Error Interrupt" icon=""/>
 819             <bitfield name="ENOVRT" mask="0x01" text="Enable CAN Timer Overrun Interrupt" icon=""/>
 820           </reg>
 821           <reg size="1" name="CANEN2" offset="0xDC" text="Enable MOb Register" icon="register.bmp" mask="0xFF"/>
 822           <reg size="1" name="CANEN1" offset="0xDD" text="Enable MOb Register" icon="register.bmp" mask="0x7F"/>
 823           <reg size="1" name="CANIE2" offset="0xDE" text="Enable Interrupt MOb Register" icon="register.bmp" mask="0xFF"/>
 824           <reg size="1" name="CANIE1" offset="0xDF" text="Enable Interrupt MOb Register" icon="register.bmp" mask="0x7F"/>
 825           <reg size="1" name="CANSIT2" offset="0xE0" text="CAN Status Interrupt MOb Register" icon="io_flag.bmp" mask="0xFF"/>
 826           <reg size="1" name="CANSIT1" offset="0xE1" text="CAN Status Interrupt MOb Register" icon="io_flag.bmp" mask="0x7F"/>
 827           <reg size="1" name="CANBT1" offset="0xE2" text="Bit Timing Register 1" icon="register.bmp">
 828             <bitfield name="BRP" mask="0x7E" text="Baud Rate Prescaler bits" icon=""/>
 829           </reg>
 830           <reg size="1" name="CANBT2" offset="0xE3" text="Bit Timing Register 2" icon="register.bmp">
 831             <bitfield name="SJW" mask="0x60" text="Re-Sync Jump Width" icon=""/>
 832             <bitfield name="PRS" mask="0x0E" text="Propagation Time Segment" icon=""/>
 833           </reg>
 834           <reg size="1" name="CANBT3" offset="0xE4" text="Bit Timing Register 3" icon="register.bmp">
 835             <bitfield name="PHS2" mask="0x70" text="Phase Segments" icon=""/>
 836             <bitfield name="PHS1" mask="0x0E" text="Phase Segment 1" icon=""/>
 837             <bitfield name="SMP" mask="0x01" text="Sample Type" icon=""/>
 838           </reg>
 839           <reg size="1" name="CANTCON" offset="0xE5" text="Timer Control Register" icon="register.bmp" mask="0x00"/>
 840           <reg size="1" name="CANTIML" offset="0xE6" text="Timer Register Low" icon="register.bmp" mask="0x00"/>
 841           <reg size="1" name="CANTIMH" offset="0xE7" text="Timer Register High" icon="register.bmp" mask="0x00"/>
 842           <reg size="1" name="CANTTCL" offset="0xE8" text="TTC Timer Register Low" icon="register.bmp" mask="0x00"/>
 843           <reg size="1" name="CANTTCH" offset="0xE9" text="TTC Timer Register High" icon="register.bmp" mask="0x00"/>
 844           <reg size="1" name="CANTEC" offset="0xEA" text="Transmit Error Counter Register" icon="register.bmp" mask="0x00"/>
 845           <reg size="1" name="CANREC" offset="0xEB" text="Receive Error Counter Register" icon="register.bmp" mask="0x00"/>
 846           <reg size="1" name="CANHPMOB" offset="0xEC" text="Highest Priority MOb Register" icon="register.bmp" mask="0xFF"/>
 847           <reg size="1" name="CANPAGE" offset="0xED" text="Page MOb Register" icon="register.bmp">
 848             <bitfield name="MOBNB" mask="0xF0" text="MOb Number Bits" icon=""/>
 849             <bitfield name="AINC" mask="0x08" text="MOb Data Buffer Auto Increment" icon=""/>
 850             <bitfield name="INDX" mask="0x07" text="Data Buffer Index Bits" icon=""/>
 851           </reg>
 852           <reg size="1" name="CANSTMOB" offset="0xEE" text="MOb Status Register" icon="io_flag.bmp">
 853             <bitfield name="DLCW" mask="0x80" text="Data Length Code Warning" icon=""/>
 854             <bitfield name="TXOK" mask="0x40" text="Transmit OK" icon=""/>
 855             <bitfield name="RXOK" mask="0x20" text="Receive OK" icon=""/>
 856             <bitfield name="BERR" mask="0x10" text="Bit Error" icon=""/>
 857             <bitfield name="SERR" mask="0x08" text="Stuff Error" icon=""/>
 858             <bitfield name="CERR" mask="0x04" text="CRC Error" icon=""/>
 859             <bitfield name="FERR" mask="0x02" text="Form Error" icon=""/>
 860             <bitfield name="AERR" mask="0x01" text="Ackknowledgement Error" icon=""/>
 861           </reg>
 862           <reg size="1" name="CANCDMOB" offset="0xEF" text="MOb Control and DLC Register" icon="register.bmp">
 863             <bitfield name="CONMOB" mask="0xC0" text="MOb Config Bits" icon=""/>
 864             <bitfield name="RPLV" mask="0x20" text="Reply Valid" icon=""/>
 865             <bitfield name="IDE" mask="0x10" text="Identifier Extension" icon=""/>
 866             <bitfield name="DLC" mask="0x0F" text="Data Length Code Bits" icon=""/>
 867           </reg>
 868           <reg size="1" name="CANIDT4" offset="0xF0" text="Identifier Tag Register 4" icon="register.bmp" mask="0xFF"/>
 869           <reg size="1" name="CANIDT3" offset="0xF1" text="Identifier Tag Register 3" icon="register.bmp" mask="0xFF"/>
 870           <reg size="1" name="CANIDT2" offset="0xF2" text="Identifier Tag Register 2" icon="register.bmp" mask="0xFF"/>
 871           <reg size="1" name="CANIDT1" offset="0xF3" text="Identifier Tag Register 1" icon="register.bmp" mask="0xFF"/>
 872           <reg size="1" name="CANIDM4" offset="0xF4" text="Identifier Mask Register 4" icon="register.bmp" mask="0xFD"/>
 873           <reg size="1" name="CANIDM3" offset="0xF5" text="Identifier Mask Register 3" icon="register.bmp" mask="0xFF"/>
 874           <reg size="1" name="CANIDM2" offset="0xF6" text="Identifier Mask Register 2" icon="register.bmp" mask="0xFF"/>
 875           <reg size="1" name="CANIDM1" offset="0xF7" text="Identifier Mask Register 1" icon="register.bmp" mask="0xFF"/>
 876           <reg size="1" name="CANSTML" offset="0xF8" text="Time Stamp Register Low" icon="register.bmp" mask="0x00"/>
 877           <reg size="1" name="CANSTMH" offset="0xF9" text="Time Stamp Register High" icon="register.bmp" mask="0x00"/>
 878           <reg size="1" name="CANMSG" offset="0xFA" text="Message Data Register" icon="register.bmp" mask="0x00"/>
 879         </registers>
 880     </module>
 881   </hardware>
 882 </device>