devices/at86rf401

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="3">
   5     <interrupt vector="1" address="$000" name="RESETB">Hardware pin, Watchdog or Button Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="TXDONE">Transmission Done, Bit Timer Flag 2 Interrupt</interrupt>
   7     <interrupt vector="3" address="$004" name="TXEMPTY">Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt</interrupt>
   8   </interrupts>
   9   <memory>
  10     <flash size="2048"/>
  11     <iospace start="$20" stop="$5F"/>
  12     <sram size="128"/>
  13     <eram size="0"/>
  14   </memory>
  15   <ioregisters>
  16     <ioreg name="MCUCR" address=""/>
  17     <ioreg name="LOCKDET1" address="$10"/>
  18     <ioreg name="TX_CNTL" address="$12"/>
  19     <ioreg name="PWR_ATTEN" address="$14"/>
  20     <ioreg name="VCOTUNE" address="$16"/>
  21     <ioreg name="LOCKDET2" address="$17"/>
  22     <ioreg name="DEECR" address="$1C"/>
  23     <ioreg name="DEEDR" address="$1D"/>
  24     <ioreg name="DEEAR" address="$1E"/>
  25     <ioreg name="BTCNT" address="$20"/>
  26     <ioreg name="BTCR" address="$21"/>
  27     <ioreg name="WDTCR" address="$22"/>
  28     <ioreg name="IO_ENAB" address="$30"/>
  29     <ioreg name="IO_DATOUT" address="$31"/>
  30     <ioreg name="IO_DATIN" address="$32"/>
  31     <ioreg name="AVR_CONFIG" address="$33"/>
  32     <ioreg name="B_DET" address="$34"/>
  33     <ioreg name="BL_CONFIG" address="$35"/>
  34     <ioreg name="SPL" address="$3D"/>
  35     <ioreg name="SPH" address="$3E"/>
  36     <ioreg name="SREG" address="$3F"/>
  37   </ioregisters>
  38   <packages>
  39     <package name="TQFP" pins="20">
  40       <pin id="1" name="[ANTB]"/>
  41       <pin id="2" name="[LOOPFIL]"/>
  42       <pin id="3" name="[L1]"/>
  43       <pin id="4" name="[L2]"/>
  44       <pin id="5" name="[RESETB]"/>
  45       <pin id="6" name="[N/C]"/>
  46       <pin id="7" name="[IO0:SDI]"/>
  47       <pin id="8" name="[IO1:SDO]"/>
  48       <pin id="9" name="[IO2:SCK]"/>
  49       <pin id="10" name="[XTAL:CLK]"/>
  50       <pin id="11" name="[XTALB]"/>
  51       <pin id="12" name="[IO3]"/>
  52       <pin id="13" name="[IO4]"/>
  53       <pin id="14" name="[IO5]"/>
  54       <pin id="15" name="[DGND]"/>
  55       <pin id="16" name="[AGND]"/>
  56       <pin id="17" name="[DVDD]"/>
  57       <pin id="18" name="[AVDD]"/>
  58       <pin id="19" name="[CFIL]"/>
  59       <pin id="20" name="[ANT]"/>
  60     </package>
  61   </packages>
  62   <hardware>
  63 <!--Everything after this needs editing!!!-->
  64     <module class="LOCKBIT">
  65       <registers name="LOCKBIT" memspace="LOCKBIT">
  66           <reg size="1" name="LOCKBIT" offset="0x00">
  67             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
  68           </reg>
  69         </registers>
  70     </module>
  71     <module class="RF_CONTROL">
  72       <registers name="RF_CONTROL" memspace="DATAMEM" text="" icon="io_cpu.bmp">
  73           <reg size="1" name="LOCKDET1" offset="0x30" text="Lock Detector Configuration Register 1" icon="io_flag.bmp">
  74             <bitfield name="UPOK" mask="0x10" text="Unlock Conuter Control" icon=""/>
  75             <bitfield name="ENKO" mask="0x08" text="Enable Key On Bit" icon=""/>
  76             <bitfield name="BOD" mask="0x04" text="Black Out Disable" icon=""/>
  77             <bitfield name="CS" mask="0x03" text="Cycle Slip Counter bits" icon=""/>
  78           </reg>
  79           <reg size="1" name="LOCKDET1" offset="0x37" text="Lock Detector Configuration register 2" icon="io_flag.bmp">
  80             <bitfield name="EUD" mask="0x80" text="Enable Unlock Detect" icon=""/>
  81             <bitfield name="LAT" mask="0x40" text="Lock Always True" icon=""/>
  82             <bitfield name="ULC" mask="0x38" text="Unlock Count bits" icon=""/>
  83             <bitfield name="LC" mask="0x07" text="Lock Count bits" icon=""/>
  84           </reg>
  85           <reg size="1" name="TX_CNTL" offset="0x32" text="Transmit Control Register" icon="io_flag.bmp">
  86             <bitfield name="FSK" mask="0x40" text="FSK Mode" icon=""/>
  87             <bitfield name="TXE" mask="0x20" text="Transmitter Enable" icon=""/>
  88             <bitfield name="TXK" mask="0x10" text="Transmitter Key" icon=""/>
  89             <bitfield name="LOC" mask="0x04" text="PLL Lock" icon=""/>
  90           </reg>
  91           <reg size="1" name="PWR_ATTEN" offset="0x34" text="Power Attenuation Control Register" icon="io_flag.bmp">
  92             <bitfield name="PCC" mask="0x38" text="Power Control Coarse bits" icon=""/>
  93             <bitfield name="PCF" mask="0x07" text="Power Control Fine bits" icon=""/>
  94           </reg>
  95           <reg size="1" name="VCOTUNE" offset="0x36" text="VCO Tuning Register" icon="io_flag.bmp">
  96             <bitfield name="VCOVDET" mask="0xC0" text="VCO Voltage Detector bits" icon=""/>
  97             <bitfield name="VCOTUNE" mask="0x1F" text="VCO Tuning Register bits" icon=""/>
  98           </reg>
  99         </registers>
 100     </module>
 101     <module class="EEPROM">
 102       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 103           <reg size="1" name="DEEAR" offset="0x3E" text="EERPOM Address Register" icon="io_cpu.bmp" mask="0x7F"/>
 104           <reg size="1" name="DEEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 105           <reg size="1" name="DEECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 106             <bitfield name="BSY" mask="0x08" text="EERPOM Busy Bit" icon=""/>
 107             <bitfield name="EEU" mask="0x04" text="EEPROM Unlock Bit" icon=""/>
 108             <bitfield name="EEL" mask="0x02" text="EEPROM Load Bit" icon=""/>
 109             <bitfield name="EER" mask="0x01" text="EEPROM Read Bit" icon=""/>
 110           </reg>
 111         </registers>
 112     </module>
 113     <module class="WATCHDOG">
 114       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 115           <reg size="1" name="WDTCR" offset="0x42" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 116             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 117             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 118             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 119           </reg>
 120         </registers>
 121     </module>
 122     <module class="TIMER_COUNTER_0">
 123       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 124           <reg size="1" name="BTCNT" offset="0x40" text="Timer Count register" icon="io_timer.bmp" mask="0xFF"/>
 125           <reg size="1" name="BTCR" offset="0x41" text="Bit Timer Counter Control Register" icon="io_timer.bmp">
 126             <bitfield name="C" mask="0xC0" text="Timer Count Register bits" icon="" lsb="8"/>
 127             <bitfield name="M" mask="0x30" text="Bit Timer Mode bits" icon=""/>
 128             <bitfield name="IE" mask="0x08" text="Interrupt Enable" icon=""/>
 129             <bitfield name="F2" mask="0x04" text="Flag 2" icon=""/>
 130             <bitfield name="DATA" mask="0x02" text="Data Bit" icon=""/>
 131             <bitfield name="F0" mask="0x01" text="Flag 0" icon=""/>
 132           </reg>
 133         </registers>
 134     </module>
 135     <module class="PORT">
 136       <registers name="PORT" memspace="DATAMEM" text="" icon="io_port.bmp">
 137           <reg size="1" name="IO_ENAB" offset="0x50" text="I/O Enable Register" icon="io_port.bmp" mask="0x3F"/>
 138           <reg size="1" name="IO_DATOUT" offset="0x51" text="I/O Data Out Register" icon="io_port.bmp" mask="0x3F"/>
 139           <reg size="1" name="IO_DATIN" offset="0x52" text="I/O Data In register" icon="io_port.bmp" mask="0x3F"/>
 140         </registers>
 141     </module>
 142     <module class="CPU">
 143       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 144           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 145             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 146             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 147             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 148             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 149             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 150             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 151             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 152             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 153           </reg>
 154           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x07FF"/>
 155           <reg size="1" name="AVR_CONFIG" offset="0x53" text="AVR Configuration Register" icon="io_flag.bmp" mask="0x7F"/>
 156           <reg size="1" name="B_DET" offset="0x54" text="Button Detect Register" icon="io_sph.bmp" mask="0x3F"/>
 157           <reg size="1" name="BL_CONFIG" offset="0x55" text="Battery Low Configuration Register" icon="io_sph.bmp" mask="0xFF"/>
 158         </registers>
 159     </module>
 160   </hardware>
 161 </device>