devices/atmega16

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="21">
   5     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt Request 1</interrupt>
   8     <interrupt vector="4" address="$006" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="SPI,STC">Serial Transfer Complete</interrupt>
  16     <interrupt vector="12" address="$016" name="USART,RXC">USART, Rx Complete</interrupt>
  17     <interrupt vector="13" address="$018" name="USART,UDRE">USART Data Register Empty</interrupt>
  18     <interrupt vector="14" address="$01A" name="USART,TXC">USART, Tx Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="ADC">ADC Conversion Complete</interrupt>
  20     <interrupt vector="16" address="$01E" name="EE_RDY">EEPROM Ready</interrupt>
  21     <interrupt vector="17" address="$020" name="ANA_COMP">Analog Comparator</interrupt>
  22     <interrupt vector="18" address="$022" name="TWI">2-wire Serial Interface</interrupt>
  23     <interrupt vector="19" address="$024" name="INT2">External Interrupt Request 2</interrupt>
  24     <interrupt vector="20" address="$026" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
  25     <interrupt vector="21" address="$028" name="SPM_RDY">Store Program Memory Ready</interrupt>
  26   </interrupts>
  27   <memory>
  28     <flash size="16384"/>
  29     <iospace start="$20" stop="$5F"/>
  30     <sram size="1024"/>
  31     <eram size="0"/>
  32   </memory>
  33   <ioregisters>
  34     <ioreg name="TWBR" address="0x00"/>
  35     <ioreg name="TWSR" address="0x01"/>
  36     <ioreg name="TWAR" address="0x02"/>
  37     <ioreg name="TWDR" address="0x03"/>
  38     <ioreg name="ADCL" address="0x04"/>
  39     <ioreg name="ADCH" address="0x05"/>
  40     <ioreg name="ADCSRA" address="0x06"/>
  41     <ioreg name="ADMUX" address="0x07"/>
  42     <ioreg name="ACSR" address="0x08"/>
  43     <ioreg name="UBRRL" address="0x09"/>
  44     <ioreg name="UCSRB" address="0x0A"/>
  45     <ioreg name="UCSRA" address="0x0B"/>
  46     <ioreg name="UDR" address="0x0C"/>
  47     <ioreg name="SPCR" address="0x0D"/>
  48     <ioreg name="SPSR" address="0x0E"/>
  49     <ioreg name="SPDR" address="0x0F"/>
  50     <ioreg name="PIND" address="0x10"/>
  51     <ioreg name="DDRD" address="0x11"/>
  52     <ioreg name="PORTD" address="0x12"/>
  53     <ioreg name="PINC" address="0x13"/>
  54     <ioreg name="DDRC" address="0x14"/>
  55     <ioreg name="PORTC" address="0x15"/>
  56     <ioreg name="PINB" address="0x16"/>
  57     <ioreg name="DDRB" address="0x17"/>
  58     <ioreg name="PORTB" address="0x18"/>
  59     <ioreg name="PINA" address="0x19"/>
  60     <ioreg name="DDRA" address="0x1A"/>
  61     <ioreg name="PORTA" address="0x1B"/>
  62     <ioreg name="EECR" address="0x1C"/>
  63     <ioreg name="EEDR" address="0x1D"/>
  64     <ioreg name="EEARL" address="0x1E"/>
  65     <ioreg name="EEARH" address="0x1F"/>
  66     <ioreg name="UBRRH" address="0x20"/>
  67     <ioreg name="UCSRC" address="0x20"/>
  68     <ioreg name="WDTCR" address="0x21"/>
  69     <ioreg name="ASSR" address="0x22"/>
  70     <ioreg name="OCR2" address="0x23"/>
  71     <ioreg name="TCNT2" address="0x24"/>
  72     <ioreg name="TCCR2" address="0x25"/>
  73     <ioreg name="ICR1L" address="0x26"/>
  74     <ioreg name="ICR1H" address="0x27"/>
  75     <ioreg name="OCR1BL" address="0x28"/>
  76     <ioreg name="OCR1BH" address="0x29"/>
  77     <ioreg name="OCR1AL" address="0x2A"/>
  78     <ioreg name="OCR1AH" address="0x2B"/>
  79     <ioreg name="TCNT1L" address="0x2C"/>
  80     <ioreg name="TCNT1H" address="0x2D"/>
  81     <ioreg name="TCCR1B" address="0x2E"/>
  82     <ioreg name="TCCR1A" address="0x2F"/>
  83     <ioreg name="SFIOR" address="0x30"/>
  84     <ioreg name="OSCCAL" address="0x31"/>
  85     <ioreg name="OCDR" address="0x31"/>
  86     <ioreg name="TCNT0" address="0x32"/>
  87     <ioreg name="TCCR0" address="0x33"/>
  88     <ioreg name="MCUCSR" address="0x34"/>
  89     <ioreg name="MCUCR" address="0x35"/>
  90     <ioreg name="TWCR" address="0x36"/>
  91     <ioreg name="SPMCSR" address="0x37"/>
  92     <ioreg name="TIFR" address="0x38"/>
  93     <ioreg name="TIMSK" address="0x39"/>
  94     <ioreg name="GIFR" address="0x3A"/>
  95     <ioreg name="GICR" address="0x3B"/>
  96     <ioreg name="OCR0" address="0x3C"/>
  97     <ioreg name="SPL" address="0x3D"/>
  98     <ioreg name="SPH" address="0x3E"/>
  99     <ioreg name="SREG" address="0x3F"/>
 100   </ioregisters>
 101   <packages>
 102     <package name="TQFP" pins="44">
 103       <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
 104       <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
 105       <pin id="3" name="[PB7_SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
 106       <pin id="4" name="['RESET]"/>
 107       <pin id="5" name="[VCC]"/>
 108       <pin id="6" name="[GND]"/>
 109       <pin id="7" name="[XTAL2]"/>
 110       <pin id="8" name="[XTAL1]"/>
 111       <pin id="9" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
 112       <pin id="10" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
 113       <pin id="11" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 114       <pin id="12" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 115       <pin id="13" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
 116       <pin id="14" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 117       <pin id="15" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
 118       <pin id="16" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
 119       <pin id="17" name="[VCC]"/>
 120       <pin id="18" name="[GND]"/>
 121       <pin id="19" name="[PC0:SCL]">SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal.</pin>
 122       <pin id="20" name="[PC1:SDA]">SDA, 2-wire Serial Bus Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is dis-connected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal, and the pin is driven by an open collector driver with slew rate limitation.</pin>
 123       <pin id="21" name="[PC2:TMS]"/>
 124       <pin id="22" name="[PC3]"/>
 125       <pin id="23" name="[PC4]"/>
 126       <pin id="24" name="[PC5]"/>
 127       <pin id="25" name="[PC6:TOSC1]"/>
 128       <pin id="26" name="[PC7:TOSC2]"/>
 129       <pin id="27" name="[AVCC]"/>
 130       <pin id="28" name="[AGND]"/>
 131       <pin id="29" name="[AREF]"/>
 132       <pin id="30" name="[PA7:ADC7]"/>
 133       <pin id="31" name="[PA6:ADC6]"/>
 134       <pin id="32" name="[PA5:ADc5]"/>
 135       <pin id="33" name="[PA4:ADC4]"/>
 136       <pin id="34" name="[PA3:ADC3]"/>
 137       <pin id="35" name="[PA2:ADC2]"/>
 138       <pin id="36" name="[PA1:ADC1]"/>
 139       <pin id="37" name="[PA0:ADC0]"/>
 140       <pin id="38" name="[VCC]"/>
 141       <pin id="39" name="[GND]"/>
 142       <pin id="40" name="[PB0:T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
 143       <pin id="41" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
 144       <pin id="42" name="[PB2:AIN0]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
 145       <pin id="43" name="[PB3:AIN1]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
 146       <pin id="44" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
 147     </package>
 148   </packages>
 149   <hardware>
 150 <!--Everything after this needs editing!!!-->
 151     <module class="FUSE">
 152       <registers name="FUSE" memspace="FUSE">
 153           <reg size="1" name="HIGH" offset="0x01">
 154             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 155             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 156             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 157             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 158             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 159             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 160             <bitfield name="CKOPT" mask="0x10" text="CKOPT fuse (operation dependent of CKSEL fuses)" icon=""/>
 161           </reg>
 162           <reg size="1" name="LOW" offset="0x00">
 163             <bitfield name="BODLEVEL" mask="0x80" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 164             <bitfield name="BODEN" mask="0x40" text="Brown-out detection enabled" icon=""/>
 165             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 166           </reg>
 167         </registers>
 168     </module>
 169     <module class="LOCKBIT">
 170       <registers name="LOCKBIT" memspace="LOCKBIT">
 171           <reg size="1" name="LOCKBIT" offset="0x00">
 172             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 173             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 174             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 175           </reg>
 176         </registers>
 177     </module>
 178     <module class="TIMER_COUNTER_0">
 179       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 180           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter Control Register" icon="io_flag.bmp">
 181             <bitfield name="FOC0" mask="0x80" text="Force Output Compare" icon=""/>
 182             <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
 183             <bitfield name="COM0" mask="0x30" text="Compare Match Output Modes" icon=""/>
 184             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 185             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 186           </reg>
 187           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 188           <reg size="1" name="OCR0" offset="0x5C" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 189           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 190             <bitfield name="OCIE0" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt register" icon=""/>
 191             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 192           </reg>
 193           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 194             <bitfield name="OCF0" mask="0x02" text="Output Compare Flag 0" icon=""/>
 195             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 196           </reg>
 197           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 198             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 199           </reg>
 200         </registers>
 201     </module>
 202     <module class="TIMER_COUNTER_1">
 203       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 204           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 205             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 206             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 207             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 208             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 209           </reg>
 210           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 211             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 212             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 213             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 214             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 215           </reg>
 216           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 217             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 218             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 219             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
 220             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
 221             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 222           </reg>
 223           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 224             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 225             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 226             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 227             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 228           </reg>
 229           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 230           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 231           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 232           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 233         </registers>
 234     </module>
 235     <module class="EXTERNAL_INTERRUPT">
 236       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 237           <reg size="1" name="GICR" offset="0x5B" text="General Interrupt Control Register" icon="io_flag.bmp">
 238             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 239             <bitfield name="INT2" mask="0x20" text="External Interrupt Request 2 Enable" icon=""/>
 240             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 241             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 242           </reg>
 243           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_flag.bmp">
 244             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 245             <bitfield name="INTF2" mask="0x20" text="External Interrupt Flag 2" icon=""/>
 246           </reg>
 247           <reg size="1" name="MCUCR" offset="0x55" text="General Interrupt Control Register" icon="io_flag.bmp">
 248             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 249             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 250           </reg>
 251           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 252             <bitfield name="ISC2" mask="0x40" text="Interrupt Sense Control 2" icon=""/>
 253           </reg>
 254         </registers>
 255     </module>
 256     <module class="EEPROM">
 257       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 258           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 259           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 260           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 261             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 262             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 263             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 264             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 265           </reg>
 266         </registers>
 267     </module>
 268     <module class="CPU">
 269       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 270           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 271             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 272             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 273             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 274             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 275             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 276             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 277             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 278             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 279           </reg>
 280           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 281           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 282             <bitfield name="SM" mask="0xB0" text="Sleep Mode Select" icon="" enum="CPU_SLEEP_MODE_3BITS"/>
 283             <bitfield name="SE" mask="0x40" text="Sleep Enable" icon=""/>
 284             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 285             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 286           </reg>
 287           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 288             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 289             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 290             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 291             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 292             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 293             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 294           </reg>
 295           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 296           <reg size="1" name="SFIOR" offset="0x50" text="Special function I/O register" icon="io_cpu.bmp">
 297             <bitfield name="PUD" mask="0x04" text="Pull-up Disable" icon=""/>
 298             <bitfield name="PSR2" mask="0x02" text="Prescaler reset" icon=""/>
 299             <bitfield name="PSR10" mask="0x01" text="Prescaler reset" icon=""/>
 300           </reg>
 301         </registers>
 302     </module>
 303     <module class="TIMER_COUNTER_2">
 304       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 305           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 306             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 307             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 308           </reg>
 309           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 310             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 311             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 312           </reg>
 313           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 314             <bitfield name="FOC2" mask="0x80" text="Force Output Compare" icon=""/>
 315             <bitfield name="WGM20" mask="0x40" text="Waveform Genration Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
 316             <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon=""/>
 317             <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
 318             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 319           </reg>
 320           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 321           <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 322           <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
 323             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer/counter2" icon=""/>
 324             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 325             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 326             <bitfield name="TCR2UB" mask="0x01" text="Timer/counter Control Register2 Update Busy" icon=""/>
 327           </reg>
 328           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 329             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 330           </reg>
 331         </registers>
 332     </module>
 333     <module class="SPI">
 334       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 335           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 336           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 337             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 338             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 339             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 340           </reg>
 341           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 342             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 343             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 344             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 345             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 346             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 347             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 348             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 349           </reg>
 350         </registers>
 351     </module>
 352     <module class="USART">
 353       <registers name="USART" memspace="DATAMEM" text="" icon="io_com.bmp">
 354           <reg size="1" name="UDR" offset="0x2C" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 355           <reg size="1" name="UCSRA" offset="0x2B" text="USART Control and Status Register A" icon="io_flag.bmp">
 356             <bitfield name="RXC" mask="0x80" text="USART Receive Complete" icon=""/>
 357             <bitfield name="TXC" mask="0x40" text="USART Transmitt Complete" icon=""/>
 358             <bitfield name="UDRE" mask="0x20" text="USART Data Register Empty" icon=""/>
 359             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 360             <bitfield name="DOR" mask="0x08" text="Data overRun" icon=""/>
 361             <bitfield name="UPE" mask="0x04" text="Parity Error" icon=""/>
 362             <bitfield name="U2X" mask="0x02" text="Double the USART transmission speed" icon=""/>
 363             <bitfield name="MPCM" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 364           </reg>
 365           <reg size="1" name="UCSRB" offset="0x2A" text="USART Control and Status Register B" icon="io_flag.bmp">
 366             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 367             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 368             <bitfield name="UDRIE" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 369             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 370             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 371             <bitfield name="UCSZ2" mask="0x04" text="Character Size" icon=""/>
 372             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 373             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 374           </reg>
 375           <reg size="1" name="UCSRC" offset="0x40" text="USART Control and Status Register C" icon="io_flag.bmp">
 376             <bitfield name="URSEL" mask="0x80" text="Register Select" icon=""/>
 377             <bitfield name="UMSEL" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 378             <bitfield name="UPM" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 379             <bitfield name="USBS" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 380             <bitfield name="UCSZ" mask="0x06" text="Character Size" icon=""/>
 381             <bitfield name="UCPOL" mask="0x01" text="Clock Polarity" icon=""/>
 382           </reg>
 383           <reg size="1" name="UBRRH" offset="0x40" text="USART Baud Rate Register Hight Byte" icon="io_com.bmp" mask="0x0F"/>
 384           <reg size="1" name="UBRRL" offset="0x29" text="USART Baud Rate Register Low Byte" icon="io_com.bmp" mask="0xFF"/>
 385         </registers>
 386     </module>
 387     <module class="TWI">
 388       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 389           <reg size="1" name="TWBR" offset="0x20" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 390           <reg size="1" name="TWCR" offset="0x56" text="TWI Control Register" icon="io_flag.bmp">
 391             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 392             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 393             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 394             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 395             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 396             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 397             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 398           </reg>
 399           <reg size="1" name="TWSR" offset="0x21" text="TWI Status Register" icon="io_flag.bmp">
 400             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 401             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 402           </reg>
 403           <reg size="1" name="TWDR" offset="0x23" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 404           <reg size="1" name="TWAR" offset="0x22" text="TWI (Slave) Address register" icon="io_com.bmp">
 405             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 406             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 407           </reg>
 408         </registers>
 409     </module>
 410     <module class="ANALOG_COMPARATOR">
 411       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 412           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_flag.bmp">
 413             <bitfield name="ACME" mask="0x08" text="Analog Comparator Multiplexer Enable" icon=""/>
 414           </reg>
 415           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 416             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 417             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 418             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 419             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 420             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 421             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 422             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 423           </reg>
 424         </registers>
 425     </module>
 426     <module class="AD_CONVERTER">
 427       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 428           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 429             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 430             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 431             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 432           </reg>
 433           <reg size="1" name="ADCSRA" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 434             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 435             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 436             <bitfield name="ADATE" mask="0x20" text="When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset." icon=""/>
 437             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 438             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 439             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 440           </reg>
 441           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 442           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 443             <bitfield name="ADTS" mask="0xE0" text="ADC Auto Trigger Sources" icon=""/>
 444           </reg>
 445         </registers>
 446     </module>
 447     <module class="JTAG">
 448       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 449           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp">
 450             <bitfield name="OCDR" mask="0xFF" text="On-Chip Debug Register Bits" icon=""/>
 451           </reg>
 452           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 453             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 454             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 455           </reg>
 456         </registers>
 457     </module>
 458     <module class="BOOT_LOAD">
 459       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 460           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 461             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 462             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 463             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 464             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 465             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 466             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 467             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 468           </reg>
 469         </registers>
 470     </module>
 471     <module class="PORTA">
 472       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 473           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 474           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 475           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 476         </registers>
 477     </module>
 478     <module class="PORTB">
 479       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 480           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 481           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 482           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 483         </registers>
 484     </module>
 485     <module class="PORTC">
 486       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 487           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 488           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 489           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 490         </registers>
 491     </module>
 492     <module class="PORTD">
 493       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 494           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 495           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 496           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 497         </registers>
 498     </module>
 499     <module class="WATCHDOG">
 500       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 501           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 502             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 503             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 504             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 505           </reg>
 506         </registers>
 507     </module>
 508   </hardware>
 509 </device>