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Fixed problem in DeviceSettings::strParam, returned wrong string
[avr-sim.git] / src / Instructions.h
blob112c4a6a0107a7ebdd77d945d09468f23a563f12
1 #ifndef AVR_INSTRUCTIONS_H
2 #define AVR_INSTRUCTIONS_H
3
4 #include "Instruction.h"
5 #include "Types.h"
6
7 #include <iostream>
8
9 namespace avr {
10
11 class Register;
12 class Core;
13
14 namespace op {
15
16 class ADC : public Instruction {
17 /*
18 * Add with Carry.
19 *
20 * Opcode : 0001 11rd dddd rrrr
21 * Usage : ADC Rd, Rr
22 * Operation : Rd <- Rd + Rr + C
23 * Flags : Z,C,N,V,S,H
24 * Num Clocks : 1
25 */
26
27 public:
28 ADC(word opcode);
29
30 public:
31 int operator()(Core *core) const;
32 int trace(Core *core, std::ostream & ostr) const;
33
34 protected:
35 unsigned char Rd;
36 unsigned char Rr;
37
38 };
39
40 class ADD : public Instruction {
41 /*
42 * Add without Carry.
43 *
44 * Opcode : 0000 11rd dddd rrrr
45 * Usage : ADD Rd, Rr
46 * Operation : Rd <- Rd + Rr
47 * Flags : Z,C,N,V,S,H
48 * Num Clocks : 1
49 */
50
51 public:
52 ADD(word opcode);
53
54 public:
55 int operator()(Core *core) const;
56 int trace(Core *core, std::ostream & ostr) const;
57
58 protected:
59 unsigned char Rd;
60 unsigned char Rr;
61 };
62
63 class ADIW : public Instruction {
64 /*
65 * Add Immediate to Word.
66 *
67 * Opcode : 1001 0110 KKdd KKKK
68 * Usage : ADIW Rd, K
69 * Operation : Rd+1:Rd <- Rd+1:Rd + K
70 * Flags : Z,C,N,V,S
71 * Num Clocks : 2
72 */
73
74 public:
75 ADIW(word opcode);
76
77 public:
78 int operator()(Core *core) const;
79 int trace(Core *core, std::ostream & ostr) const;
80
81 protected:
82 unsigned char Rl;
83 unsigned char Rh;
84 unsigned char K;
85 };
86
87 class AND : public Instruction {
88 /*
89 * Logical AND.
90 *
91 * Opcode : 0010 00rd dddd rrrr
92 * Usage : AND Rd, Rr
93 * Operation : Rd <- Rd & Rr
94 * Flags : Z,N,V,S
95 * Num Clocks : 1
96 */
97
98 public:
99 AND(word opcode);
100
101 public:
102 int operator()(Core *core) const;
103 int trace(Core *core, std::ostream & ostr) const;
104
105 protected:
106 unsigned char Rd;
107 unsigned char Rr;
108 };
109
110 class ANDI : public Instruction {
111 /*
112 * Logical AND with Immed.
113 *
114 * Opcode : 0111 KKKK dddd KKKK
115 * Usage : ANDI Rd, K
116 * Operation : Rd <- Rd & K
117 * Flags : Z,N,V,S
118 * Num Clocks : 1
119 */
120
121 public:
122 ANDI(word opcode);
123
124 public:
125 int operator()(Core *core) const;
126 int trace(Core *core, std::ostream & ostr) const;
127
128 protected:
129 unsigned char Rd;
130 unsigned char K;
131
132 };
133
134 class ASR : public Instruction {
135 /*
136 * Arithmetic Shift Right.
137 *
138 * Opcode : 1001 010d dddd 0101
139 * Usage : ASR Rd
140 * Operation : Rd(n) <- Rd(n+1), n=0..6
141 * Flags : Z,C,N,V,S
142 * Num Clocks : 1
143 */
144
145 public:
146 ASR(word opcode);
147
148 public:
149 int operator()(Core *core) const;
150 int trace(Core *core, std::ostream & ostr) const;
151
152 protected:
153 unsigned char Rd;
154 };
155
156 class BCLR : public Instruction {
157 /*
158 * Clear a single flag or bit in SREG.
159 *
160 * Opcode : 1001 0100 1sss 1000
161 * Usage : BCLR
162 * Operation : SREG(s) <- 0
163 * Flags : SREG(s)
164 * Num Clocks : 1
165 */
166
167 public:
168 BCLR(word opcode);
169
170 public:
171 int operator()(Core *core) const;
172 int trace(Core *core, std::ostream & ostr) const;
173
174 protected:
175 unsigned char K;
176 };
177
178 class BLD : public Instruction {
179 /* Bit load from T to Register.
180 *
181 * Opcode : 1111 100d dddd 0bbb
182 * Usage : BLD Rd, b
183 * Operation : Rd(b) <- T
184 * Flags : None
185 * Num Clocks : 1
186 */
187
188 public:
189 BLD(word opcode);
190
191 public:
192 int operator()(Core *core) const;
193 int trace(Core *core, std::ostream & ostr) const;
194
195 protected:
196 unsigned char Rd;
197 unsigned char Kadd, Kremove;
198 };
199
200 class BRBC : public Instruction {
201 /*
202 * Branch if Status Flag Cleared.
203 *
204 * Pass control directly to the specific bit operation.
205 *
206 * Opcode : 1111 01kk kkkk ksss
207 * Usage : BRBC s, k
208 * Operation : if (SREG(s) = 0) then PC <- PC + k + 1
209 * Flags : None
210 * Num Clocks : 1 / 2
211 *
212 * k is an relative address represented in two's complements.
213 * (64 < k <= 64)
214 */
215
216 public:
217 BRBC(word opcode);
218
219 public:
220 int operator()(Core *core) const;
221 int trace(Core *core, std::ostream & ostr) const;
222
223 protected:
224 unsigned char bitmask;
225 signed char offset;
226 };
227
228 class BRBS : public Instruction {
229 /*
230 * Branch if Status Flag Set.
231 *
232 * Pass control directly to the specific bit operation.
233 *
234 * Opcode : 1111 00kk kkkk ksss
235 * Usage : BRBS s, k
236 * Operation : if (SREG(s) = 1) then PC <- PC + k + 1
237 * Flags : None
238 * Num Clocks : 1 / 2
239 *
240 * k is an relative address represented in two's complements.
241 * (64 < k <= 64)
242 */
243
244 public:
245 BRBS(word opcode);
246
247 public:
248 int operator()(Core *core) const;
249 int trace(Core *core, std::ostream & ostr) const;
250
251 protected:
252 unsigned char bitmask;
253 signed char offset;
254 };
255
256 class BSET : public Instruction {
257 /*
258 * Set a single flag or bit in SREG.
259 *
260 * Opcode : 1001 0100 0sss 1000
261 * Usage : BSET
262 * Operation : SREG(s) <- 1
263 * Flags : SREG(s)
264 * Num Clocks : 1
265 */
266
267 public:
268 BSET(word opcode);
269
270 public:
271 int operator()(Core *core) const;
272 int trace(Core *core, std::ostream & ostr) const;
273
274 protected:
275 unsigned char K;
276 };
277
278 class BST:public Instruction
279 {
280 /*
281 * Bit Store from Register to T.
282 *
283 * Opcode : 1111 101d dddd 0bbb
284 * Usage : BST Rd, b
285 * Operation : T <- Rd(b)
286 * Flags : T
287 * Num Clocks : 1
288 */
289
290 public:
291 BST(word opcode);
292
293 public:
294 int operator()(Core *core) const;
295 int trace(Core *core, std::ostream & ostr) const;
296
297 protected:
298 unsigned char Rd;
299 unsigned char K;
300
301 };
302
303 class CALL : public Instruction {
304 /*
305 * Call Subroutine.
306 *
307 * Opcode : 1001 010k kkkk 111k kkkk kkkk kkkk kkkk
308 * Usage : CALL k
309 * Operation : PC <- k
310 * Flags : None
311 * Num Clocks : 4 / 5
312 */
313
314 public:
315 CALL(word opcode);
316
317 public:
318 int operator()(Core *core) const;
319 int trace(Core *core, std::ostream & ostr) const;
320 bool is2Word() const { return true; }
321
322 protected:
323 unsigned char KH;
324 };
325
326 class CBI : public Instruction {
327 /*
328 * Clear Bit in I/O Register.
329 *
330 * Opcode : 1001 1000 AAAA Abbb
331 * Usage : CBI A, b
332 * Operation : I/O(A, b) <- 0
333 * Flags : None
334 * Num Clocks : 2
335 */
336
337 public:
338 CBI (word opcode);
339 int operator()(Core *core) const;
340 int trace(Core *core, std::ostream & ostr) const;
341
342 protected:
343 unsigned char ioreg;
344 unsigned char K;
345 };
346
347 class COM : public Instruction {
348 /*
349 * One's Complement.
350 *
351 * Opcode : 1001 010d dddd 0000
352 * Usage : COM Rd
353 * Operation : Rd <- $FF - Rd
354 * Flags : Z,C,N,V,S
355 * Num Clocks : 1
356 */
357
358 public:
359 COM (word opcode);
360
361 public:
362 int operator()(Core *core) const;
363 int trace(Core *core, std::ostream & ostr) const;
364
365 protected:
366 unsigned char Rd;
367 };
368
369 class CP : public Instruction {
370 /*
371 * Compare.
372 *
373 * Opcode : 0001 01rd dddd rrrr
374 * Usage : CP Rd, Rr
375 * Operation : Rd - Rr
376 * Flags : Z,C,N,V,S,H
377 * Num Clocks : 1
378 */
379
380 public:
381 CP (word opcode);
382
383 public:
384 int operator()(Core *core) const;
385 int trace(Core *core, std::ostream & ostr) const;
386
387 protected:
388 unsigned char Rd;
389 unsigned char Rr;
390 };
391
392 class CPC : public Instruction {
393 /*
394 * Compare with Carry.
395 *
396 * Opcode : 0000 01rd dddd rrrr
397 * Usage : CPC Rd, Rr
398 * Operation : Rd - Rr - C
399 * Flags : Z,C,N,V,S,H
400 * Num Clocks : 1
401 */
402
403 public:
404 CPC (word opcode);
405 int operator()(Core *core) const;
406 int trace(Core *core, std::ostream & ostr) const;
407
408 protected:
409 unsigned char Rd;
410 unsigned char Rr;
411 };
412
413 class CPI : public Instruction {
414 /*
415 * Compare with Immediate.
416 *
417 * Opcode : 0011 KKKK dddd KKKK
418 * Usage : CPI Rd, K
419 * Operation : Rd - K
420 * Flags : Z,C,N,V,S,H
421 * Num Clocks : 1
422 */
423
424 public:
425 CPI (word opcode);
426
427 public:
428 int operator()(Core *core) const;
429 int trace(Core *core, std::ostream & ostr) const;
430
431
432 protected:
433 unsigned char Rd;
434 unsigned char K;
435 };
436
437 class CPSE : public Instruction {
438 /*
439 * Compare, Skip if Equal.
440 *
441 * Opcode : 0001 00rd dddd rrrr
442 * Usage : CPSE Rd, Rr
443 * Operation : if (Rd = Rr) PC <- PC + 2 or 3
444 * Flags : None
445 * Num Clocks : 1 / 2 / 3
446 */
447
448 public:
449 CPSE (word opcode);
450
451 public:
452 int operator()(Core *core) const;
453 int trace(Core *core, std::ostream & ostr) const;
454
455 protected:
456 unsigned char Rd;
457 unsigned char Rr;
458 };
459
460 class DEC : public Instruction {
461 /*
462 * Decrement.
463 *
464 * Opcode : 1001 010d dddd 1010
465 * Usage : DEC Rd
466 * Operation : Rd <- Rd - 1
467 * Flags : Z,N,V,S
468 * Num Clocks : 1
469 */
470
471 public:
472 DEC (word opcode);
473 int operator()(Core *core) const;
474 int trace(Core *core, std::ostream & ostr) const;
475
476 protected:
477 unsigned char Rd;
478 };
479
480 class EICALL : public Instruction {
481 /*
482 * Extended Indirect Call to (Z).
483 *
484 * Opcode : 1001 0101 0001 1001
485 * Usage : EICALL
486 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
487 * Flags : None
488 * Num Clocks : 4
489 */
490
491 public:
492 EICALL(word opcode);
493
494 public:
495 int operator()(Core *core) const;
496 int trace(Core *core, std::ostream & ostr) const;
497
498 protected:
499 unsigned char eind;
500 };
501
502 class EIJMP : public Instruction {
503 /*
504 * Extended Indirect Jmp to (Z).
505 *
506 * Opcode : 1001 0100 0001 1001
507 * Usage : EIJMP
508 * Operation : PC(15:0) <- Z, PC(21:16) <- EIND
509 * Flags : None
510 * Num Clocks : 2
511 */
512
513 public:
514 EIJMP (word opcode);
515
516 public:
517 int operator()(Core *core) const;
518 int trace(Core *core, std::ostream & ostr) const;
519
520 protected:
521 unsigned char eind;
522 };
523
524 class ELPM_Z : public Instruction {
525 /*
526 * Extended Load Program Memory.
527 *
528 * Opcode : 1001 000d dddd 0110
529 * Usage : ELPM Rd, Z
530 * Operation : R <- (RAMPZ:Z)
531 * Flags : None
532 * Num Clocks : 3
533 */
534
535 public:
536 ELPM_Z (word opcode);
537
538 public:
539 int operator()(Core *core) const;
540 int trace(Core *core, std::ostream & ostr) const;
541
542 protected:
543 unsigned char Rd;
544 };
545
546 class ELPM_Z_incr:public Instruction {
547 /*
548 * Extended Ld Prg Mem and Post-Incr.
549 *
550 * Opcode : 1001 000d dddd 0111
551 * Usage : ELPM Rd, Z+
552 * Operation : Rd <- (RAMPZ:Z), Z <- Z + 1
553 * Flags : None
554 * Num Clocks : 3
555 */
556
557 public:
558 ELPM_Z_incr(word opcode);
559
560 public:
561 int operator()(Core *core) const;
562 int trace(Core *core, std::ostream & ostr) const;
563
564 protected:
565 unsigned char Rd;
566 };
567
568 class ELPM : public Instruction {
569 /*
570 * Extended Load Program Memory.
571 *
572 *
573 * Opcode : 1001 0101 1101 1000
574 * Usage : ELPM
575 * Operation : R0 <- (RAMPZ:Z)
576 * Flags : None
577 * Num Clocks : 3
578 */
579
580 public:
581 ELPM(word opcode);
582
583 public:
584 int operator()(Core *core) const;
585 int trace(Core *core, std::ostream & ostr) const;
586 };
587
588 class EOR:public Instruction {
589 /*
590 * Exclusive OR.
591 *
592 * Opcode : 0010 01rd dddd rrrr
593 * Usage : EOR Rd, Rr
594 * Operation : Rd <- Rd ^ Rr
595 * Flags : Z,N,V,S
596 * Num Clocks : 1
597 */
598
599 public:
600 EOR(word opcode);
601
602 public:
603 int operator()(Core *core) const;
604 int trace(Core *core, std::ostream & ostr) const;
605
606 protected:
607 unsigned char Rd;
608 unsigned char Rr;
609 };
610
611 class ESPM : public Instruction {
612 /*
613 * Extended Store Program Memory.
614 *
615 * Opcode : 1001 0101 1111 1000
616 * Usage : ESPM
617 * Operation : Z <- R1:R0
618 * Flags : None
619 * Num Clocks : -
620 */
621
622 public:
623 ESPM(word opcode);
624
625 public:
626 int operator()(Core *core) const;
627 int trace(Core *core, std::ostream & ostr) const;
628 };
629
630 class FMUL:public Instruction {
631 /*
632 * Fractional Mult Unsigned.
633 *
634 * Opcode : 0000 0011 0ddd 1rrr
635 * Usage : FMUL Rd, Rr
636 * Operation : R1:R0 <- (Rd * Rr)<<1 (UU)
637 * Flags : Z,C
638 * Num Clocks : 2
639 */
640
641 public:
642 FMUL(word opcode);
643
644 public:
645 int operator()(Core *core) const;
646 int trace(Core *core, std::ostream & ostr) const;
647
648 protected:
649 unsigned char Rd;
650 unsigned char Rr;
651 };
652
653 class FMULS : public Instruction {
654 /*
655 * Fractional Mult Signed.
656 *
657 * Opcode : 0000 0011 1ddd 0rrr
658 * Usage : FMULS Rd, Rr
659 * Operation : R1:R0 <- (Rd * Rr)<<1 (SS)
660 * Flags : Z,C
661 * Num Clocks : 2
662 */
663
664 public:
665 FMULS(word opcode);
666
667 public:
668 int operator()(Core *core) const;
669 int trace(Core *core, std::ostream & ostr) const;
670
671 protected:
672 unsigned char Rd;
673 unsigned char Rr;
674 };
675
676 class FMULSU : public Instruction {
677 /*
678 * Fract Mult Signed w/ Unsigned.
679 *
680 * Opcode : 0000 0011 1ddd 1rrr
681 * Usage : FMULSU Rd, Rr
682 * Operation : R1:R0 <- (Rd * Rr)<<1 (SU)
683 * Flags : Z,C
684 * Num Clocks : 2
685 */
686
687 public:
688 FMULSU (word opcode);
689
690 public:
691 int operator()(Core *core) const;
692 int trace(Core *core, std::ostream & ostr) const;
693
694 protected:
695 unsigned char Rd;
696 unsigned char Rr;
697 };
698
699 class ICALL : public Instruction {
700 /*
701 * Indirect Call to (Z).
702 *
703 * Opcode : 1001 0101 0000 1001
704 * Usage : ICALL
705 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
706 * Flags : None
707 * Num Clocks : 3 / 4
708 */
709
710 public:
711 ICALL(word opcode);
712
713 public:
714 int operator()(Core *core) const;
715 int trace(Core *core, std::ostream & ostr) const;
716 };
717
718 class IJMP : public Instruction {
719 /*
720 * Indirect Jump to (Z).
721 *
722 * Opcode : 1001 0100 0000 1001
723 * Usage : IJMP
724 * Operation : PC(15:0) <- Z, PC(21:16) <- 0
725 * Flags : None
726 * Num Clocks : 2
727 */
728
729 public:
730 IJMP(word opcode);
731
732 public:
733 int operator()(Core *core) const;
734 int trace(Core *core, std::ostream & ostr) const;
735 };
736
737 class IN : public Instruction {
738 /*
739 * In From I/O Location.
740 *
741 * Opcode : 1011 0AAd dddd AAAA
742 * Usage : IN Rd, A
743 * Operation : Rd <- I/O(A)
744 * Flags : None
745 * Num Clocks : 1
746 */
747
748 public:
749 IN (word opcode);
750
751 public:
752 int operator()(Core *core) const;
753 int trace(Core *core, std::ostream & ostr) const;
754
755 protected:
756 unsigned char Rd;
757 unsigned char ioreg;
758 };
759
760 class INC : public Instruction {
761 /*
762 * Increment.
763 *
764 * Opcode : 1001 010d dddd 0011
765 * Usage : INC Rd
766 * Operation : Rd <- Rd + 1
767 * Flags : Z,N,V,S
768 * Num Clocks : 1
769 */
770
771 public:
772 INC (word opcode);
773
774 public:
775 int operator()(Core *core) const;
776 int trace(Core *core, std::ostream & ostr) const;
777
778 protected:
779 unsigned char Rd;
780 };
781
782 class JMP : public Instruction {
783 /*
784 * Jump.
785 *
786 * Opcode : 1001 010k kkkk 110k kkkk kkkk kkkk kkkk
787 * Usage : JMP k
788 * Operation : PC <- k
789 * Flags : None
790 * Num Clocks : 3
791 */
792
793 public:
794 JMP(word opcode);
795
796 public:
797 int operator()(Core *core) const;
798 int trace(Core *core, std::ostream & ostr) const;
799 bool is2Word() const { return true; }
800
801 protected:
802 unsigned int K;
803 };
804
805 class LDD_Y : public Instruction {
806 /*
807 * Load Indirect with Displacement using index Y.
808 *
809 * Opcode : 10q0 qq0d dddd 1qqq
810 * Usage : LDD Rd, Y+q
811 * Operation : Rd <- (Y + q)
812 * Flags : None
813 * Num Clocks : 2
814 */
815
816 public:
817 LDD_Y(word opcode);
818
819 public:
820 int operator()(Core *core) const;
821 int trace(Core *core, std::ostream & ostr) const;
822
823 protected:
824 unsigned char Rd;
825 unsigned char K;
826 };
827
828 class LDD_Z : public Instruction {
829 /*
830 * Load Indirect with Displacement using index Z.
831 *
832 * Opcode : 10q0 qq0d dddd 0qqq
833 * Usage : LDD Rd, Z+q
834 * Operation : Rd <- (Z + q)
835 * Flags : None
836 * Num Clocks : 2
837 */
838
839 public:
840 LDD_Z(word opcode);
841
842 public:
843 int operator()(Core *core) const;
844 int trace(Core *core, std::ostream & ostr) const;
845
846 protected:
847 unsigned char Rd;
848 unsigned char K;
849 };
850
851 class LDI : public Instruction {
852 /*
853 * Load Immediate.
854 *
855 * Opcode : 1110 KKKK dddd KKKK
856 * Usage : LDI Rd, K
857 * Operation : Rd <- K
858 * Flags : None
859 * Num Clocks : 1
860 */
861
862 public:
863 LDI(word opcode);
864
865 public:
866 int operator()(Core *core) const;
867 int trace(Core *core, std::ostream & ostr) const;
868
869 protected:
870 unsigned char Rd;
871 unsigned char K;
872 };
873
874 class LDS : public Instruction {
875 /*
876 * Load Direct from data space.
877 *
878 * Opcode : 1001 000d dddd 0000 kkkk kkkk kkkk kkkk
879 * Usage : LDS Rd, k
880 * Operation : Rd <- (k)
881 * Flags : None
882 * Num Clocks : 2
883 */
884
885 public:
886 LDS(word opcode);
887
888 public:
889 int operator()(Core *core) const;
890 int trace(Core *core, std::ostream & ostr) const;
891 bool is2Word() const { return true; }
892
893 protected:
894 unsigned char Rd;
895 };
896
897 class LD_X : public Instruction {
898 /*
899 * Load Indirect using index X.
900 *
901 * Opcode : 1001 000d dddd 1100
902 * Usage : LD Rd, X
903 * Operation : Rd <- (X)
904 * Flags : None
905 * Num Clocks : 2
906 */
907
908 public:
909 LD_X(word opcode);
910
911 public:
912 int operator()(Core *core) const;
913 int trace(Core *core, std::ostream & ostr) const;
914
915 protected:
916 unsigned char Rd;
917 };
918
919 class LD_X_decr : public LD_X {
920 /*
921 * Load Indirect and Pre-Decrement using index X.
922 *
923 * Opcode : 1001 000d dddd 1110
924 * Usage : LD Rd, -X
925 * Operation : X <- X - 1, Rd <- (X)
926 * Flags : None
927 * Num Clocks : 2
928 */
929
930 public:
931 LD_X_decr(word opcode);
932
933 public:
934 int operator()(Core *core) const;
935 int trace(Core *core, std::ostream & ostr) const;
936 };
937
938 class LD_X_incr : public LD_X {
939 /*
940 * Load Indirect and Post-Increment using index X.
941 *
942 * Opcode : 1001 000d dddd 1101
943 * Usage : LD Rd, X+
944 * Operation : Rd <- (X), X <- X + 1
945 * Flags : None
946 * Num Clocks : 2
947 */
948
949 public:
950 LD_X_incr(word opcode);
951
952 public:
953 int operator()(Core *core) const;
954 int trace(Core *core, std::ostream & ostr) const;
955 };
956
957 class LD_Y_decr : public Instruction {
958 /*
959 * Load Indirect and PreDecrement using index Y.
960 *
961 * Opcode : 1001 000d dddd 1010
962 * Usage : LD Rd, -Y
963 * Operation : Y <- Y - 1, Rd <- (Y)
964 * Flags : None
965 * Num Clocks : 2
966 */
967
968 public:
969 LD_Y_decr(word opcode);
970
971 public:
972 int operator()(Core *core) const;
973 int trace(Core *core, std::ostream & ostr) const;
974
975 protected:
976 unsigned char Rd;
977 };
978
979 class LD_Y_incr : public Instruction {
980 /*
981 * Load Indirect and Post-Increment using index Y.
982 *
983 * Opcode : 1001 000d dddd 1001
984 * Usage : LD Rd, Y+
985 * Operation : Rd <- (Y), Y <- Y + 1
986 * Flags : None
987 * Num Clocks : 2
988 */
989
990 public:
991 LD_Y_incr(word opcode);
992
993 public:
994 int operator()(Core *core) const;
995 int trace(Core *core, std::ostream & ostr) const;
996
997 protected:
998 unsigned char Rd;
999 };
1000
1001 class LD_Z_incr : public Instruction {
1002 /*
1003 * Load Indirect and Post-Increment using index Z.
1004 *
1005 * Opcode : 1001 000d dddd 0001
1006 * Usage : LD Rd, Z+
1007 * Operation : Rd <- (Z), Z <- Z+1
1008 * Flags : None
1009 * Num Clocks : 2
1010 */
1011
1012 public:
1013 LD_Z_incr(word opcode);
1014
1015 public:
1016 int operator()(Core *core) const;
1017 int trace(Core *core, std::ostream & ostr) const;
1018
1019 protected:
1020 unsigned char Rd;
1021 };
1022
1023 class LD_Z_decr : public Instruction {
1024 /*
1025 * Load Indirect and Pre-Decrement using index Z.
1026 *
1027 * Opcode : 1001 000d dddd 0010
1028 * Usage : LD Rd, -Z
1029 * Operation : Z <- Z - 1, Rd <- (Z)
1030 * Flags : None
1031 * Num Clocks : 2
1032 */
1033
1034 public:
1035 LD_Z_decr(word opcode);
1036
1037 public:
1038 int operator()(Core *core) const;
1039 int trace(Core *core, std::ostream & ostr) const;
1040
1041 protected:
1042 unsigned char Rd;
1043 };
1044
1045 class LPM_Z : public Instruction {
1046 /*
1047 * Load Program Memory.
1048 *
1049 * Opcode : 1001 000d dddd 0100
1050 * Usage : LPM Rd, Z
1051 * Operation : Rd <- (Z)
1052 * Flags : None
1053 * Num Clocks : 3
1054 */
1055
1056 public:
1057 LPM_Z(word opcode);
1058
1059 public:
1060 int operator()(Core *core) const;
1061 int trace(Core *core, std::ostream & ostr) const;
1062
1063 protected:
1064 unsigned char Rd;
1065 };
1066
1067 class LPM : public Instruction {
1068 /* Load Program Memory.
1069 *
1070 * This the same as LPM_Z:public Instruction
1071 *
1072 * Opcode : 1001 0101 1100 1000
1073 * Usage : LPM
1074 * Operation : R0 <- (Z)
1075 * Flags : None
1076 * Num Clocks : 3
1077 */
1078
1079 public:
1080 LPM(word opcode);
1081
1082 public:
1083 int operator()(Core *core) const;
1084 int trace(Core *core, std::ostream & ostr) const;
1085 };
1086
1087 class LPM_Z_incr : public Instruction {
1088 /*
1089 * Load Program Memory and Post-Incr.
1090 *
1091 * Opcode : 1001 000d dddd 0101
1092 * Usage : LPM Rd, Z+
1093 * Operation : Rd <- (Z), Z <- Z + 1
1094 * Flags : None
1095 * Num Clocks : 3
1096 */
1097
1098 public:
1099 LPM_Z_incr(word opcode);
1100
1101 public:
1102 int operator()(Core *core) const;
1103 int trace(Core *core, std::ostream & ostr) const;
1104
1105 protected:
1106 unsigned char Rd;
1107 };
1108
1109 class LSR : public Instruction {
1110 /*
1111 * Logical Shift Right.
1112 *
1113 * Opcode : 1001 010d dddd 0110
1114 * Usage : LSR Rd
1115 * Operation : Rd(n) <- Rd(n+1), Rd(7) <- 0, C <- Rd(0)
1116 * Flags : Z,C,N,V,S
1117 * Num Clocks : 1
1118 */
1119
1120 public:
1121 LSR(word opcode);
1122
1123 public:
1124 int operator()(Core *core) const;
1125 int trace(Core *core, std::ostream & ostr) const;
1126
1127 protected:
1128 unsigned char Rd;
1129 };
1130
1131 class MOV:public Instruction {
1132 /* Copy Register.
1133 *
1134 * Opcode : 0010 11rd dddd rrrr
1135 * Usage : MOV Rd, Rr
1136 * Operation : Rd <- Rr
1137 * Flags : None
1138 * Num Clocks : 1
1139 */
1140
1141 public:
1142 MOV(word opcode);
1143
1144 public:
1145 int operator()(Core *core) const;
1146 int trace(Core *core, std::ostream & ostr) const;
1147
1148 protected:
1149 unsigned char Rd;
1150 unsigned char Rr;
1151 };
1152
1153 class MOVW:public Instruction {
1154 /*
1155 *Copy Register Pair.
1156 *
1157 * Opcode : 0000 0001 dddd rrrr
1158 * Usage : MOVW Rd, Rr
1159 * Operation : Rd+1:Rd <- Rr+1:Rr
1160 * Flags : None
1161 * Num Clocks : 1
1162 */
1163
1164 public:
1165 MOVW(word opcode);
1166
1167 public:
1168 int operator()(Core *core) const;
1169 int trace(Core *core, std::ostream & ostr) const;
1170
1171 protected:
1172 unsigned char Rdl;
1173 unsigned char Rdh;
1174 unsigned char Rrl;
1175 unsigned char Rrh;
1176 };
1177
1178 class MUL : public Instruction {
1179 /*
1180 * Mult Unsigned.
1181 *
1182 * Opcode : 1001 11rd dddd rrrr
1183 * Usage : MUL Rd, Rr
1184 * Operation : R1:R0 <- Rd * Rr (UU)
1185 * Flags : Z,C
1186 * Num Clocks : 2
1187 */
1188
1189 public:
1190 MUL(word opcode);
1191
1192 public:
1193 int operator()(Core *core) const;
1194 int trace(Core *core, std::ostream & ostr) const;
1195
1196 protected:
1197 unsigned char Rd;
1198 unsigned char Rr;
1199 };
1200
1201 class MULS : public Instruction {
1202 /*
1203 * Mult Signed.
1204 *
1205 * Opcode : 0000 0010 dddd rrrr
1206 * Usage : MULS Rd, Rr
1207 * Operation : R1:R0 <- Rd * Rr (SS)
1208 * Flags : Z,C
1209 * Num Clocks : 2
1210 */
1211
1212 public:
1213 MULS(word opcode);
1214
1215 public:
1216 int operator()(Core *core) const;
1217 int trace(Core *core, std::ostream & ostr) const;
1218
1219 protected:
1220 unsigned char Rd;
1221 unsigned char Rr;
1222 };
1223
1224 class MULSU:public Instruction {
1225 /*
1226 * Mult Signed with Unsigned.
1227 *
1228 * Rd(unsigned),Rr(signed), result (signed)
1229 *
1230 * Opcode : 0000 0011 0ddd 0rrr
1231 * Usage : MULSU Rd, Rr
1232 * Operation : R1:R0 <- Rd * Rr (SU)
1233 * Flags : Z,C
1234 * Num Clocks : 2
1235 */
1236
1237 public:
1238 MULSU(word opcode);
1239
1240 public:
1241 int operator()(Core *core) const;
1242 int trace(Core *core, std::ostream & ostr) const;
1243
1244 protected:
1245 unsigned char Rd;
1246 unsigned char Rr;
1247 };
1248
1249 class NEG : public Instruction {
1250 /*
1251 * Two's Complement.
1252 *
1253 * Opcode : 1001 010d dddd 0001
1254 * Usage : NEG Rd
1255 * Operation : Rd <- $00 - Rd
1256 * Flags : Z,C,N,V,S,H
1257 * Num Clocks : 1
1258 */
1259
1260 public:
1261 NEG (word opcode);
1262
1263 public:
1264 int operator()(Core *core) const;
1265 int trace(Core *core, std::ostream & ostr) const;
1266
1267 protected:
1268 unsigned char Rd;
1269 };
1270
1271 class NOP : public Instruction {
1272 /*
1273 * No Operation.
1274 *
1275 * Opcode : 0000 0000 0000 0000
1276 * Usage : NOP
1277 * Operation : None
1278 * Flags : None
1279 * Num Clocks : 1
1280 */
1281
1282 public:
1283 NOP(word opcode);
1284
1285 public:
1286 int operator()(Core *core) const;
1287 int trace(Core *core, std::ostream & ostr) const;
1288 };
1289
1290 class OR:public Instruction {
1291 /*
1292 * Logical OR.
1293 *
1294 * Opcode : 0010 10rd dddd rrrr
1295 * Usage : OR Rd, Rr
1296 * Operation : Rd <- Rd or Rr
1297 * Flags : Z,N,V,S
1298 * Num Clocks : 1
1299 */
1300
1301 public:
1302 OR(word opcode);
1303
1304 public:
1305 int operator()(Core *core) const;
1306 int trace(Core *core, std::ostream & ostr) const;
1307
1308 protected:
1309 unsigned char Rd;
1310 unsigned char Rr;
1311 };
1312
1313 class ORI : public Instruction {
1314 /*
1315 * Logical OR with Immed.
1316 *
1317 * Opcode : 0110 KKKK dddd KKKK
1318 * Usage : ORI Rd, K
1319 * Operation : Rd <- Rd or K
1320 * Flags : Z,N,V,S
1321 * Num Clocks : 1
1322 */
1323
1324 public:
1325 ORI (word opcode);
1326
1327 public:
1328 int operator()(Core *core) const;
1329 int trace(Core *core, std::ostream & ostr) const;
1330
1331 protected:
1332 unsigned char Rd;
1333 unsigned char K;
1334 };
1335
1336 class OUT : public Instruction {
1337 /*
1338 * Out To I/O Location.
1339 *
1340 * Opcode : 1011 1AAd dddd AAAA
1341 * Usage : OUT A Rd
1342 * Operation : I/O(A) <- Rd
1343 * Flags : None
1344 * Num Clocks : 1
1345 */
1346
1347 public:
1348 OUT(word opcode);
1349
1350 public:
1351 int operator()(Core *core) const;
1352 int trace(Core *core, std::ostream & ostr) const;
1353
1354 protected:
1355 unsigned char Rd;
1356 unsigned char ioreg;
1357 };
1358
1359 class POP : public Instruction {
1360 /*
1361 * Pop Register from Stack.
1362 *
1363 * Opcode : 1001 000d dddd 1111
1364 * Usage : POP Rd
1365 * Operation : Rd <- STACK
1366 * Flags : None
1367 * Num Clocks : 2
1368 */
1369
1370 public:
1371 POP(word opcode);
1372
1373 public:
1374 int operator()(Core *core) const;
1375 int trace(Core *core, std::ostream & ostr) const;
1376
1377 protected:
1378 unsigned char Rd;
1379 };
1380
1381 class PUSH : public Instruction {
1382 /*
1383 * Push Register on Stack.
1384 *
1385 * Opcode : 1001 001d dddd 1111
1386 * Usage : PUSH Rd
1387 * Operation : STACK <- Rd
1388 * Flags : None
1389 * Num Clocks : 2
1390 */
1391
1392 public:
1393 PUSH(word opcode);
1394
1395 public:
1396 int operator()(Core *core) const;
1397 int trace(Core *core, std::ostream & ostr) const;
1398
1399 protected:
1400 unsigned char Rd;
1401 };
1402
1403 class RCALL : public Instruction {
1404 /*
1405 * Relative Call Subroutine.
1406 *
1407 * Opcode : 1101 kkkk kkkk kkkk
1408 * Usage : RCALL k
1409 * Operation : PC <- PC + k + 1
1410 * Flags : None
1411 * Num Clocks : 3 / 4
1412 */
1413
1414 public:
1415 RCALL(word opcode);
1416
1417 public:
1418 int operator()(Core *core) const;
1419 int trace(Core *core, std::ostream & ostr) const;
1420
1421 protected:
1422 signed int K;
1423 };
1424
1425 class RET : public Instruction {
1426 /*
1427 * Subroutine Return.
1428 *
1429 * Opcode : 1001 0101 0000 1000
1430 * Usage : RET
1431 * Operation : PC <- STACK
1432 * Flags : None
1433 * Num Clocks : 4 / 5
1434 */
1435
1436 public:
1437 RET(word opcode);
1438
1439 public:
1440 int operator()(Core *core) const;
1441 int trace(Core *core, std::ostream & ostr) const;
1442 };
1443
1444 class RETI : public Instruction {
1445 /*
1446 * Interrupt Return.
1447 *
1448 * Opcode : 1001 0101 0001 1000
1449 * Usage : RETI
1450 * Operation : PC <- STACK
1451 * Flags : I
1452 * Num Clocks : 4 / 5
1453 */
1454
1455 public:
1456 RETI(word opcode);
1457
1458 public:
1459 int operator()(Core *core) const;
1460 int trace(Core *core, std::ostream & ostr) const;
1461 };
1462
1463 class RJMP : public Instruction {
1464 /*
1465 * Relative Jump.
1466 *
1467 * Opcode : 1100 kkkk kkkk kkkk
1468 * Usage : RJMP k
1469 * Operation : PC <- PC + k + 1
1470 * Flags : None
1471 * Num Clocks : 2
1472 */
1473
1474 public:
1475 RJMP(word opcode);
1476
1477 public:
1478 int operator()(Core *core) const;
1479 int trace(Core *core, std::ostream & ostr) const;
1480
1481 protected:
1482 signed int K;
1483 };
1484
1485 class ROR : public Instruction {
1486 /*
1487 * Rotate Right Though Carry.
1488 *
1489 * Opcode : 1001 010d dddd 0111
1490 * Usage : ROR Rd
1491 * Operation : Rd(7) <- C, Rd(n) <- Rd(n+1), C <- Rd(0)
1492 * Flags : Z,C,N,V,S
1493 * Num Clocks : 1
1494 */
1495
1496 public:
1497 ROR(word opcode);
1498
1499 public:
1500 int operator()(Core *core) const;
1501 int trace(Core *core, std::ostream & ostr) const;
1502
1503 protected:
1504 unsigned char Rd;
1505 };
1506
1507 class SBC : public Instruction {
1508 /*
1509 * Subtract with Carry.
1510 *
1511 * Opcode : 0000 10rd dddd rrrr
1512 * Usage : SBC Rd, Rr
1513 * Operation : Rd <- Rd - Rr - C
1514 * Flags : Z,C,N,V,S,H
1515 * Num Clocks : 1
1516 */
1517
1518 public:
1519 SBC(word opcode);
1520
1521 public:
1522 int operator()(Core *core) const;
1523 int trace(Core *core, std::ostream & ostr) const;
1524
1525 protected:
1526 unsigned char Rd;
1527 unsigned char Rr;
1528 };
1529
1530 class SBCI : public Instruction {
1531 /*
1532 * Subtract Immediate with Carry.
1533 *
1534 * Opcode : 0100 KKKK dddd KKKK
1535 * Usage : SBCI Rd, K
1536 * Operation : Rd <- Rd - K - C
1537 * Flags : Z,C,N,V,S,H
1538 * Num Clocks : 1
1539 */
1540
1541 public:
1542 SBCI(word opcode);
1543
1544 public:
1545 int operator()(Core *core) const;
1546 int trace(Core *core, std::ostream & ostr) const;
1547
1548 protected:
1549 unsigned char Rd;
1550 unsigned char K;
1551 };
1552
1553 class SBI : public Instruction {
1554 /*
1555 * Set Bit in I/O Register.
1556 *
1557 * Opcode : 1001 1010 AAAA Abbb
1558 * Usage : SBI A, b
1559 * Operation : I/O(A, b) <- 1
1560 * Flags : None
1561 * Num Clocks : 2
1562 */
1563
1564 public:
1565 SBI(word opcode);
1566
1567 public:
1568 int operator()(Core *core) const;
1569 int trace(Core *core, std::ostream & ostr) const;
1570
1571 protected:
1572 unsigned char ioreg;
1573 unsigned char K;
1574 };
1575
1576 class SBIC : public Instruction {
1577 /*
1578 * Skip if Bit in I/O Reg Cleared.
1579 *
1580 * Opcode : 1001 1001 AAAA Abbb
1581 * Usage : SBIC A, b
1582 * Operation : if (I/O(A,b) = 0) PC <- PC + 2 or 3
1583 * Flags : None
1584 * Num Clocks : 1 / 2 / 3
1585 */
1586
1587 public:
1588 SBIC(word opcode);
1589
1590 public:
1591 int operator()(Core *core) const;
1592 int trace(Core *core, std::ostream & ostr) const;
1593
1594 protected:
1595 unsigned char ioreg;
1596 unsigned char K;
1597 };
1598
1599 class SBIS : public Instruction {
1600 /*
1601 * Skip if Bit in I/O Reg Set.
1602 *
1603 * Opcode : 1001 1011 AAAA Abbb
1604 * Usage : SBIS A, b
1605 * Operation : if (I/O(A,b) = 1) PC <- PC + 2 or 3
1606 * Flags : None
1607 * Num Clocks : 1 / 2 / 3
1608 */
1609
1610 public:
1611 SBIS(word opcode);
1612
1613 public:
1614 int operator()(Core *core) const;
1615 int trace(Core *core, std::ostream & ostr) const;
1616
1617 protected:
1618 unsigned char ioreg;
1619 unsigned char K;
1620 };
1621
1622 class SBIW : public Instruction {
1623 /*
1624 * Subtract Immed from Word.
1625 *
1626 * Opcode : 1001 0111 KKdd KKKK
1627 * Usage : SBIW Rd, K
1628 * Operation : Rd+1:Rd <- Rd+1:Rd - K
1629 * Flags : Z,C,N,V,S
1630 * Num Clocks : 2
1631 */
1632
1633 public:
1634 SBIW (word opcode);
1635
1636 public:
1637 int operator()(Core *core) const;
1638 int trace(Core *core, std::ostream & ostr) const;
1639
1640 protected:
1641 unsigned char Rl;
1642 unsigned char Rh;
1643 unsigned char K;
1644 };
1645
1646 class SBRC : public Instruction {
1647 /*
1648 * Skip if Bit in Reg Cleared.
1649 *
1650 * Opcode : 1111 110d dddd 0bbb
1651 * Usage : SBRC Rd, b
1652 * Operation : if (Rd(b) = 0) PC <- PC + 2 or 3
1653 * Flags : None
1654 * Num Clocks : 1 / 2 / 3
1655 */
1656
1657 public:
1658 SBRC (word opcode);
1659
1660 public:
1661 int operator()(Core *core) const;
1662 int trace(Core *core, std::ostream & ostr) const;
1663
1664 protected:
1665 unsigned char Rd;
1666 unsigned char K;
1667 };
1668
1669 class SBRS : public Instruction {
1670 /*
1671 * Skip if Bit in Reg Set.
1672 *
1673 * Opcode : 1111 111d dddd 0bbb
1674 * Usage : SBRS Rd, b
1675 * Operation : if (Rd(b) = 1) PC <- PC + 2 or 3
1676 * Flags : None
1677 * Num Clocks : 1 / 2 / 3
1678 */
1679
1680 public:
1681 SBRS (word opcode);
1682
1683 public:
1684 int operator()(Core *core) const;
1685 int trace(Core *core, std::ostream & ostr) const;
1686
1687 protected:
1688 unsigned char Rd;
1689 unsigned char K;
1690 };
1691
1692 class SLEEP : public Instruction {
1693 /*
1694 * Sleep.
1695 *
1696 * This is device specific and should be overridden by sub-class.
1697 *
1698 * Opcode : 1001 0101 1000 1000
1699 * Usage : SLEEP
1700 * Operation : (see specific hardware specification for Sleep)
1701 * Flags : None
1702 * Num Clocks : 1
1703 */
1704
1705
1706 public:
1707 SLEEP(word opcode);
1708
1709 public:
1710 int operator()(Core *core) const;
1711 int trace(Core *core, std::ostream & ostr) const;
1712 };
1713
1714 class SPM : public Instruction {
1715 /*
1716 * Store Program Memory.
1717 *
1718 * Opcode : 1001 0101 1110 1000
1719 * Usage : SPM
1720 * Operation : (Z) <- R1:R0
1721 * Flags : None
1722 * Num Clocks : -
1723 */
1724
1725 public:
1726 SPM(word opcode);
1727
1728 public:
1729 int operator()(Core *core) const;
1730 int trace(Core *core, std::ostream & ostr) const;
1731 };
1732
1733 class STD_Y : public Instruction {
1734 /*
1735 * Store Indirect with Displacement.
1736 *
1737 * Opcode : 10q0 qq1d dddd 1qqq
1738 * Usage : STD Y+q, Rd
1739 * Operation : (Y + q) <- Rd
1740 * Flags : None
1741 * Num Clocks : 2
1742 */
1743
1744 public:
1745 STD_Y(word opcode);
1746
1747 public:
1748 int operator()(Core *core) const;
1749 int trace(Core *core, std::ostream & ostr) const;
1750
1751 protected:
1752 unsigned char Rd;
1753 unsigned char K;
1754 };
1755
1756 class STD_Z : public Instruction {
1757 /*
1758 * Store Indirect with Displacement.
1759 *
1760 * Opcode : 10q0 qq1d dddd 0qqq
1761 * Usage : STD Z+q, Rd
1762 * Operation : (Z + q) <- Rd
1763 * Flags : None
1764 * Num Clocks : 2
1765 */
1766
1767 public:
1768 STD_Z(word opcode);
1769
1770 public:
1771 int operator()(Core *core) const;
1772 int trace(Core *core, std::ostream & ostr) const;
1773
1774 protected:
1775 unsigned char Rd;
1776 unsigned char K;
1777 };
1778
1779 class STS : public Instruction {
1780 /*
1781 * Store Direct to data space.
1782 *
1783 * Opcode : 1001 001d dddd 0000 kkkk kkkk kkkk kkkk
1784 * Usage : STS k, Rd
1785 * Operation : (k) <- Rd
1786 * Flags : None
1787 * Num Clocks : 2
1788 */
1789
1790 public:
1791 STS(word opcode);
1792
1793 public:
1794 int operator()(Core *core) const;
1795 int trace(Core *core, std::ostream & ostr) const;
1796 bool is2Word() const { return true; }
1797
1798 protected:
1799 unsigned char Rd;
1800 };
1801
1802 class ST_X : public Instruction {
1803 /*
1804 * Store Indirect using index X.
1805 *
1806 * Opcode : 1001 001d dddd 1100
1807 * Usage : ST X, Rd
1808 * Operation : (X) <- Rd
1809 * Flags : None
1810 * Num Clocks : 2
1811 */
1812
1813 public:
1814 ST_X(word opcode);
1815
1816 public:
1817 int operator()(Core *core) const;
1818 int trace(Core *core, std::ostream & ostr) const;
1819
1820 protected:
1821 unsigned char Rd;
1822 };
1823
1824 class ST_X_decr : public ST_X {
1825 /*
1826 * Store Indirect and Pre-Decrement using index X.
1827 *
1828 * Opcode : 1001 001d dddd 1110
1829 * Usage : ST -X, Rd
1830 * Operation : X <- X - 1, (X) <- Rd
1831 * Flags : None
1832 * Num Clocks : 2
1833 */
1834
1835 public:
1836 ST_X_decr(word opcode);
1837
1838 public:
1839 int operator()(Core *core) const;
1840 int trace(Core *core, std::ostream & ostr) const;
1841 };
1842
1843 class ST_X_incr : public ST_X {
1844 /*
1845 * Store Indirect and Post-Increment using index X.
1846 *
1847 * Opcode : 1001 001d dddd 1101
1848 * Usage : ST X+, Rd
1849 * Operation : (X) <- Rd, X <- X + 1
1850 * Flags : None
1851 * Num Clocks : 2
1852 */
1853
1854 public:
1855 ST_X_incr(word opcode);
1856
1857 public:
1858 int operator()(Core *core) const;
1859 int trace(Core *core, std::ostream & ostr) const;
1860 };
1861
1862 class ST_Y_decr : public Instruction {
1863 /*
1864 * Store Indirect and Pre-Decrement using index Y.
1865 *
1866 * Opcode : 1001 001d dddd 1010
1867 * Usage : ST -Y, Rd
1868 * Operation : Y <- Y - 1, (Y) <- Rd
1869 * Flags : None
1870 * Num Clocks : 2
1871 */
1872
1873 public:
1874 ST_Y_decr (word opcode);
1875
1876 public:
1877 int operator()(Core *core) const;
1878 int trace(Core *core, std::ostream & ostr) const;
1879
1880 protected:
1881 unsigned char Rd;
1882 };
1883
1884 class ST_Y_incr : public Instruction {
1885 /*
1886 * Store Indirect and Post-Increment using index Y.
1887 *
1888 * Opcode : 1001 001d dddd 1001
1889 * Usage : ST Y+, Rd
1890 * Operation : (Y) <- Rd, Y <- Y + 1
1891 * Flags : None
1892 * Num Clocks : 2
1893 */
1894
1895 public:
1896 ST_Y_incr (word opcode);
1897
1898 public:
1899 int operator()(Core *core) const;
1900 int trace(Core *core, std::ostream & ostr) const;
1901
1902 protected:
1903 unsigned char Rd;
1904 };
1905
1906 class ST_Z_decr : public Instruction {
1907 /*
1908 * Store Indirect and Pre-Decrement using index Z.
1909 *
1910 * Opcode : 1001 001d dddd 0010
1911 * Usage : ST -Z, Rd
1912 * Operation : Z <- Z - 1, (Z) <- Rd
1913 * Flags : None
1914 * Num Clocks : 2
1915 */
1916
1917 public:
1918 ST_Z_decr (word opcode);
1919
1920 public:
1921 int operator()(Core *core) const;
1922 int trace(Core *core, std::ostream & ostr) const;
1923
1924 protected:
1925 unsigned char Rd;
1926 };
1927
1928 class ST_Z_incr : public Instruction {
1929 /*
1930 * Store Indirect and Post-Increment using index Z.
1931 *
1932 * Opcode : 1001 001d dddd 0001
1933 * Usage : ST Z+, Rd
1934 * Operation : (Z) <- Rd, Z <- Z + 1
1935 * Flags : None
1936 * Num Clocks : 2
1937 */
1938
1939 public:
1940 ST_Z_incr (word opcode);
1941
1942 public:
1943 int operator()(Core *core) const;
1944 int trace(Core *core, std::ostream & ostr) const;
1945
1946 protected:
1947 unsigned char Rd;
1948 };
1949
1950 class SUB : public Instruction {
1951 /*
1952 * Subtract without Carry.
1953 *
1954 * Opcode : 0001 10rd dddd rrrr
1955 * Usage : SUB Rd, Rr
1956 * Operation : Rd <- Rd - Rr
1957 * Flags : Z,C,N,V,S,H
1958 * Num Clocks : 1
1959 */
1960
1961 public:
1962 SUB(word opcode);
1963
1964 public:
1965 int operator()(Core *core) const;
1966 int trace(Core *core, std::ostream & ostr) const;
1967
1968 protected:
1969 unsigned char Rd;
1970 unsigned char Rr;
1971 };
1972
1973 class SUBI : public Instruction {
1974 /*
1975 * Subtract Immediate.
1976 *
1977 * Opcode : 0101 KKKK dddd KKKK
1978 * Usage : SUBI Rd, K
1979 * Operation : Rd <- Rd - K
1980 * Flags : Z,C,N,V,S,H
1981 * Num Clocks : 1
1982 */
1983
1984 public:
1985 SUBI(word opcode);
1986
1987 public:
1988 int operator()(Core *core) const;
1989 int trace(Core *core, std::ostream & ostr) const;
1990
1991 protected:
1992 unsigned char Rd;
1993 unsigned char K;
1994 };
1995
1996 class SWAP : public Instruction {
1997 /*
1998 * Swap Nibbles.
1999 *
2000 * Opcode : 1001 010d dddd 0010
2001 * Usage : SWAP Rd
2002 * Operation : Rd(3..0) <--> Rd(7..4)
2003 * Flags : None
2004 * Num Clocks : 1
2005 */
2006
2007 public:
2008 SWAP(word opcode);
2009
2010 public:
2011 int operator()(Core *core) const;
2012 int trace(Core *core, std::ostream & ostr) const;
2013
2014 protected:
2015 unsigned char Rd;
2016 };
2017
2018 class WDR : public Instruction {
2019 /*
2020 * Watchdog Reset.
2021 *
2022 * This is device specific and must be overridden by sub-class.
2023 *
2024 * Opcode : 1001 0101 1010 1000
2025 * Usage : WDR
2026 * Operation : (see specific hardware specification for WDR)
2027 * Flags : None
2028 * Num Clocks : 1
2029 */
2030
2031 public:
2032 WDR(word opcode);
2033
2034 public:
2035 int operator()(Core *core) const;
2036 int trace(Core *core, std::ostream & ostr) const;
2037 };
2038
2039 class BREAK : public Instruction {
2040 /*
2041 * On-chip Debug system break.
2042 *
2043 * Opcode : 1001 0101 1001 1000
2044 * Usage : BREAK
2045 * Operation : (see specific hardware specification for BREAK)
2046 * Flags : None
2047 * Num Clocks : 1
2048 */
2049
2050 public:
2051 BREAK(word opcode);
2052
2053 public:
2054 int operator()(Core *core) const;
2055 int trace(Core *core, std::ostream & ostr) const;
2056 };
2057
2058 class ILLEGAL : public Instruction {
2059 /*
2060 * Illegal instruction
2061 */
2062
2063 public:
2064 ILLEGAL(word opcode);
2065
2066 public:
2067 int operator()(Core *core) const;
2068 int trace(Core *core, std::ostream & ostr) const;
2069
2070 private:
2071 word opcode;
2072 };
2073
2074 }
2075
2076 }
2077
2078 #endif /*AVR_INSTRUCTIONS_H*/
Atmel AVR simulator