devices/attiny85

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="8192"/>
   6     <iospace start="$20" stop="$5F"/>
   7     <sram size="512"/>
   8     <eram size="0"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="ADCSRB" address="$03"/>
  12     <ioreg name="ADCL" address="$04"/>
  13     <ioreg name="ADCH" address="$05"/>
  14     <ioreg name="ADCSRA" address="$06"/>
  15     <ioreg name="ADMUX" address="$07"/>
  16     <ioreg name="ACSR" address="$08"/>
  17     <ioreg name="USICR" address="$0D"/>
  18     <ioreg name="USISR" address="$0E"/>
  19     <ioreg name="USIDR" address="$0F"/>
  20     <ioreg name="USIBR" address="$10"/>
  21     <ioreg name="GPIOR0" address="$11"/>
  22     <ioreg name="GPIOR1" address="$12"/>
  23     <ioreg name="GPIOR2" address="$13"/>
  24     <ioreg name="DIDR0" address="$14"/>
  25     <ioreg name="PCMSK" address="$15"/>
  26     <ioreg name="PINB" address="$16"/>
  27     <ioreg name="DDRB" address="$17"/>
  28     <ioreg name="PORTB" address="$18"/>
  29     <ioreg name="EECR" address="$1C"/>
  30     <ioreg name="EEDR" address="$1D"/>
  31     <ioreg name="EEARL" address="$1E"/>
  32     <ioreg name="EEARH" address="$1F"/>
  33     <ioreg name="PRR" address="$20"/>
  34     <ioreg name="WDTCR" address="$21"/>
  35     <ioreg name="DWDR" address="$22"/>
  36     <ioreg name="DTPS" address="$23"/>
  37     <ioreg name="DT1B" address="$24"/>
  38     <ioreg name="DT1A" address="$25"/>
  39     <ioreg name="CLKPR" address="$26"/>
  40     <ioreg name="PLLCSR" address="$27"/>
  41     <ioreg name="OCR0B" address="$28"/>
  42     <ioreg name="OCR0A" address="$29"/>
  43     <ioreg name="TCCR0A" address="$2A"/>
  44     <ioreg name="OCR1B" address="$2B"/>
  45     <ioreg name="GTCCR" address="$2C"/>
  46     <ioreg name="OCR1C" address="$2D"/>
  47     <ioreg name="OCR1A" address="$2E"/>
  48     <ioreg name="TCNT1" address="$2F"/>
  49     <ioreg name="TCCR1" address="$30"/>
  50     <ioreg name="OSCCAL" address="$31"/>
  51     <ioreg name="TCNT0" address="$32"/>
  52     <ioreg name="TCCR0B" address="$33"/>
  53     <ioreg name="MCUSR" address="$34"/>
  54     <ioreg name="MCUCR" address="$35"/>
  55     <ioreg name="SPMCSR" address="$37"/>
  56     <ioreg name="TIFR" address="$38"/>
  57     <ioreg name="TIMSK" address="$39"/>
  58     <ioreg name="GIFR" address="$3A"/>
  59     <ioreg name="GIMSK" address="$3B"/>
  60     <ioreg name="SPL" address="$3D"/>
  61     <ioreg name="SPH" address="$3E"/>
  62     <ioreg name="SREG" address="$3F"/>
  63   </ioregisters>
  64   <packages/>
  65   <interrupts num="15">
  66     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset,Watchdog Reset</interrupt>
  67     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
  68     <interrupt vector="3" address="$002" name="PCINT0">Pin change Interrupt Request 0</interrupt>
  69     <interrupt vector="4" address="$003" name="TIMER1_COMPA">Timer/Counter1 Compare Match 1A</interrupt>
  70     <interrupt vector="5" address="$004" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  71     <interrupt vector="6" address="$005" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  72     <interrupt vector="7" address="$006" name="EE_RDY">EEPROM Ready</interrupt>
  73     <interrupt vector="8" address="$007" name="ANA_COMP">Analog comparator</interrupt>
  74     <interrupt vector="9" address="$008" name="ADC">ADC Conversion ready</interrupt>
  75     <interrupt vector="10" address="$009" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  76     <interrupt vector="11" address="$00A" name="TIMER0_COMPA">Timer/Counter0 Compare Match A</interrupt>
  77     <interrupt vector="12" address="$00B" name="TIMER0_COMPB">Timer/Counter0 Compare Match B</interrupt>
  78     <interrupt vector="13" address="$00C" name="WDT">Watchdog Time-out</interrupt>
  79     <interrupt vector="14" address="$00D" name="USI_START">USI START</interrupt>
  80     <interrupt vector="15" address="$00E" name="USI_OVF">USI Overflow</interrupt>
  81   </interrupts>
  82   <hardware>
  83 <!--Everything after this needs editing!!!-->
  84     <module class="FUSE">
  85       <registers name="FUSE" memspace="FUSE">
  86           <reg size="1" name="EXTENDED" offset="0x02">
  87             <bitfield name="SELFPRGEN" mask="0x01" text="Self Programming enable" icon=""/>
  88           </reg>
  89           <reg size="1" name="HIGH" offset="0x01">
  90             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PB5 as i/o pin)" icon=""/>
  91             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
  92             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
  93             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
  94             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
  95             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
  96           </reg>
  97           <reg size="1" name="LOW" offset="0x00">
  98             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
  99             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB4" icon=""/>
 100             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock source" icon="" enum="ENUM_SUT_CKSEL"/>
 101           </reg>
 102         </registers>
 103     </module>
 104     <module class="LOCKBIT">
 105       <registers name="LOCKBIT" memspace="LOCKBIT">
 106           <reg size="1" name="LOCKBIT" offset="0x00">
 107             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 108           </reg>
 109         </registers>
 110     </module>
 111     <module class="PORTB">
 112       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 113           <reg size="1" name="PORTB" offset="0x38" text="Data Register, Port B" icon="io_port.bmp" mask="0x3F"/>
 114           <reg size="1" name="DDRB" offset="0x37" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x3F"/>
 115           <reg size="1" name="PINB" offset="0x36" text="Input Pins, Port B" icon="io_port.bmp" mask="0x3F"/>
 116         </registers>
 117     </module>
 118     <module class="ANALOG_COMPARATOR">
 119       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 120           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_flag.bmp">
 121             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 122           </reg>
 123           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 124             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 125             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 126             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 127             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 128             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 129             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 130           </reg>
 131           <reg size="1" name="DIDR0" offset="0x34" text="" icon="">
 132             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 133             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 134           </reg>
 135         </registers>
 136     </module>
 137     <module class="AD_CONVERTER">
 138       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 139           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 140             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon=""/>
 141             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 142             <bitfield name="REFS2" mask="0x10" text="Reference Selection Bit 2" icon=""/>
 143             <bitfield name="MUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 144           </reg>
 145           <reg size="1" name="ADCSRA" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 146             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 147             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 148             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 149             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 150             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 151             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 152           </reg>
 153           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 154           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_analo.bmp">
 155             <bitfield name="BIN" mask="0x80" text="Bipolar Input Mode" icon=""/>
 156             <bitfield name="IPR" mask="0x20" text="Input Polarity Mode" icon=""/>
 157             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon="" enum="ANALIG_ADC_AUTO_TRIGGER2"/>
 158           </reg>
 159           <reg size="1" name="DIDR0" offset="0x34" text="Digital Input Disable Register 0" icon="io_analo.bmp">
 160             <bitfield name="ADC0D" mask="0x20" text="ADC0 Digital input Disable" icon=""/>
 161             <bitfield name="ADC2D" mask="0x10" text="ADC2 Digital input Disable" icon=""/>
 162             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 163             <bitfield name="ADC1D" mask="0x04" text="ADC1 Digital input Disable" icon=""/>
 164           </reg>
 165         </registers>
 166     </module>
 167     <module class="USI">
 168       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 169           <reg size="1" name="USIBR" offset="0x30" text="USI Buffer Register" icon="io_com.bmp" mask="0xFF"/>
 170           <reg size="1" name="USIDR" offset="0x2F" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 171           <reg size="1" name="USISR" offset="0x2E" text="USI Status Register" icon="io_flag.bmp">
 172             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 173             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 174             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 175             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 176             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 177           </reg>
 178           <reg size="1" name="USICR" offset="0x2D" text="USI Control Register" icon="io_flag.bmp">
 179             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 180             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 181             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 182             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 183             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 184             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 185           </reg>
 186         </registers>
 187     </module>
 188     <module class="EXTERNAL_INTERRUPT">
 189       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 190           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 191             <bitfield name="ISC01" mask="0x02" text="Interrupt Sense Control 0 Bit 1" icon=""/>
 192             <bitfield name="ISC00" mask="0x01" text="Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 193           </reg>
 194           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 195             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
 196             <bitfield name="PCIE" mask="0x20" text="Pin Change Interrupt Enable" icon=""/>
 197           </reg>
 198           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 199             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
 200             <bitfield name="PCIF" mask="0x20" text="Pin Change Interrupt Flag" icon=""/>
 201           </reg>
 202           <reg size="1" name="PCMSK" offset="0x35" text="Pin Change Enable Mask" icon="io_flag.bmp" mask="0x3F"/>
 203         </registers>
 204     </module>
 205     <module class="EEPROM">
 206       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 207           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 208           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 209           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 210             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 211             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 212             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 213             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 214             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 215           </reg>
 216         </registers>
 217     </module>
 218     <module class="WATCHDOG">
 219       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 220           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 221             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 222             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 223             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 224             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 225             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 226           </reg>
 227         </registers>
 228     </module>
 229     <module class="TIMER_COUNTER_0">
 230       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 231           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 232             <bitfield name="OCIE0A" mask="0x10" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 233             <bitfield name="OCIE0B" mask="0x08" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 234             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 235           </reg>
 236           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 237             <bitfield name="OCF0A" mask="0x10" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 238             <bitfield name="OCF0B" mask="0x08" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 239             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 240           </reg>
 241           <reg size="1" name="TCCR0A" offset="0x4A" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 242             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 243             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 244             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 245           </reg>
 246           <reg size="1" name="TCCR0B" offset="0x53" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 247             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 248             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 249             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 250             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 251           </reg>
 252           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 253           <reg size="1" name="OCR0A" offset="0x49" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 254           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 255           <reg size="1" name="GTCCR" offset="0x4C" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 256             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 257             <bitfield name="PSR0" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 258           </reg>
 259         </registers>
 260     </module>
 261     <module class="TIMER_COUNTER_1">
 262       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 263           <reg size="1" name="TCCR1" offset="0x50" text="Timer/Counter Control Register" icon="io_flag.bmp">
 264             <bitfield name="CTC1" mask="0x80" text="Clear Timer/Counter on Compare Match" icon=""/>
 265             <bitfield name="PWM1A" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 266             <bitfield name="COM1A" mask="0x30" text="Compare Output Mode, Bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 267             <bitfield name="CS1" mask="0x0F" text="Clock Select Bits" icon="" enum="CLK_SEL_4BIT"/>
 268           </reg>
 269           <reg size="1" name="TCNT1" offset="0x4F" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 270           <reg size="1" name="OCR1A" offset="0x4E" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 271           <reg size="1" name="OCR1B" offset="0x4B" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 272           <reg size="1" name="OCR1C" offset="0x4D" text="Output compare register" icon="io_timer.bmp" mask="0xFF"/>
 273           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 274             <bitfield name="OCIE1A" mask="0x40" text="OCIE1A: Timer/Counter1 Output Compare Interrupt Enable" icon=""/>
 275             <bitfield name="OCIE1B" mask="0x20" text="OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable" icon=""/>
 276             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 277           </reg>
 278           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 279             <bitfield name="OCF1A" mask="0x40" text="Timer/Counter1 Output Compare Flag 1A" icon=""/>
 280             <bitfield name="OCF1B" mask="0x20" text="Timer/Counter1 Output Compare Flag 1B" icon=""/>
 281             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 282           </reg>
 283           <reg size="1" name="GTCCR" offset="0x4C" text="Timer counter control register" icon="io_flag.bmp">
 284             <bitfield name="PWM1B" mask="0x40" text="Pulse Width Modulator B Enable" icon=""/>
 285             <bitfield name="COM1B" mask="0x30" text="Comparator B Output Mode" icon=""/>
 286             <bitfield name="FOC1B" mask="0x08" text="Force Output Compare Match 1B" icon=""/>
 287             <bitfield name="FOC1A" mask="0x04" text="Force Output Compare 1A" icon=""/>
 288             <bitfield name="PSR1" mask="0x02" text="Prescaler Reset Timer/Counter1" icon=""/>
 289           </reg>
 290           <reg size="1" name="DTPS" offset="0x43" text="Dead time prescaler register" icon="io_flag.bmp">
 291             <bitfield name="DTPS" mask="0x03" text="" icon=""/>
 292           </reg>
 293           <reg size="1" name="DT1A" offset="0x45" text="Dead time value register" icon="io_flag.bmp">
 294             <bitfield name="DTVH" mask="0xF0" text="" icon=""/>
 295             <bitfield name="DTVL" mask="0x0F" text="" icon=""/>
 296           </reg>
 297           <reg size="1" name="DT1B" offset="0x44" text="Dead time value B" icon="io_flag.bmp">
 298             <bitfield name="DTVH" mask="0xF0" text="" icon=""/>
 299             <bitfield name="DTVL" mask="0x0F" text="" icon=""/>
 300           </reg>
 301         </registers>
 302     </module>
 303     <module class="BOOT_LOAD">
 304       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 305           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 306             <bitfield name="CTPB" mask="0x10" text="Clear temporary page buffer" icon=""/>
 307             <bitfield name="RFLB" mask="0x08" text="Read fuse and lock bits" icon=""/>
 308             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 309             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 310             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 311           </reg>
 312         </registers>
 313     </module>
 314     <module class="CPU">
 315       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 316           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 317             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 318             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 319             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 320             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 321             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 322             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 323             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 324             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 325           </reg>
 326           <reg size="1" name="PRR" offset="0x40" text="Power Reduction Register" icon="io_sreg.bmp">
 327             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 328             <bitfield name="PRTIM0" mask="0x04" text="Power Reduction Timer/Counter0" icon=""/>
 329             <bitfield name="PRUSI" mask="0x02" text="Power Reduction USI" icon=""/>
 330             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 331           </reg>
 332           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer  Bytes" icon="io_sreg.bmp" mask="0x03FF"/>
 333           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 334             <bitfield name="PUD" mask="0x40" text="Pull-up Disable" icon=""/>
 335             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 336             <bitfield name="SM" mask="0x18" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE2"/>
 337             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 338           </reg>
 339           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status register" icon="io_cpu.bmp">
 340             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 341             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 342             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 343             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 344           </reg>
 345           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Register" icon="io_sreg.bmp" mask="0xFF"/>
 346           <reg size="1" name="CLKPR" offset="0x46" text="Clock Prescale Register" icon="io_sreg.bmp">
 347             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 348             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 349           </reg>
 350           <reg size="1" name="PLLCSR" offset="0x47" text="PLL Control and status register" icon="io_sreg.bmp">
 351             <bitfield name="LSM" mask="0x80" text="Low speed mode" icon=""/>
 352             <bitfield name="PCKE" mask="0x04" text="PCK Enable" icon=""/>
 353             <bitfield name="PLLE" mask="0x02" text="PLL Enable" icon=""/>
 354             <bitfield name="PLOCK" mask="0x01" text="PLL Lock detector" icon=""/>
 355           </reg>
 356           <reg size="1" name="DWDR" offset="0x42" text="debugWire data register" icon="io_cpu.bmp" mask="0xFF"/>
 357           <reg size="1" name="GPIOR2" offset="0x33" text="General Purpose IO register 2" icon="io_sreg.bmp" mask="0xFF"/>
 358           <reg size="1" name="GPIOR1" offset="0x32" text="General Purpose register 1" icon="io_sreg.bmp" mask="0xFF"/>
 359           <reg size="1" name="GPIOR0" offset="0x31" text="General purpose register 0" icon="io_sreg.bmp" mask="0xFF"/>
 360         </registers>
 361     </module>
 362   </hardware>
 363 </device>