devices/attiny167

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="20">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt Request 1</interrupt>
   8     <interrupt vector="4" address="$006" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
   9     <interrupt vector="5" address="$008" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
  10     <interrupt vector="6" address="$00A" name="WDT">Watchdog Time-Out Interrupt</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1_COMPA">Timer/Counter1 Compare Match 1A</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1_COMPB">Timer/Counter1 Compare Match 1B</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER0_COMPA">Timer/Counter0 Compare Match 0A</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="LIN_TC">LIN Transfer Complete</interrupt>
  18     <interrupt vector="14" address="$01A" name="LIN_ERR">LIN Error</interrupt>
  19     <interrupt vector="15" address="$01C" name="SPI_STC">SPI Serial Transfer Complete</interrupt>
  20     <interrupt vector="16" address="$01E" name="ADC">ADC Conversion Complete</interrupt>
  21     <interrupt vector="17" address="$020" name="EE_RDY">EEPROM Ready</interrupt>
  22     <interrupt vector="18" address="$022" name="ANA_COMP">Analog Comparator</interrupt>
  23     <interrupt vector="19" address="$024" name="USI_START">USI Start</interrupt>
  24     <interrupt vector="20" address="$0026" name="USI_OVF">USI Overflow</interrupt>
  25   </interrupts>
  26   <packages>
  27     <package name="PDIP" pins="20">
  28       <pin id="1" name="[RXLIN:RXD:ADC0:PCINT0:PA0]">RXLIN (LIN Receive Pin). RXD (UART Receive Pin). ADC0 (ADC Input Channel 0). PCINT0 (Pin Change Interrupt 0). PORTA0.</pin>
  29       <pin id="2" name="[TXLIN:TXD:ADC1:PCINT1:PA1]">TXLIN (LIN Transmit Pin). RXD (UART Receive Pin). ADC0 (ADC Input Channel 0). PCINT0 (Pin Change Interrupt 0). PORTA1.</pin>
  30       <pin id="3" name="[MISO:DO:OC0A:ADC2:PCINT2:PA2]">MISO (SPI Master Input / Slave Output). DO (Three-wire Mode USI Alternate Data Output). OC0A (Output Compare and PWM Output A for Timer/Counter0). ADC2 (ADC Input Channel 2). PCINT2 (Pin Change Interrupt 2). PORTA2.</pin>
  31       <pin id="4" name="[INT1:ISRC:ADC3:PCINT3:PA3]">INT1 (External Interrupt1 Input). ISRC (Current Source Pin). ADC3 (ADC Input Channel 3). PCINT3 (Pin Change Interrupt 3). PORTA3.</pin>
  32       <pin id="5" name="[AVCC]">Analog Supply Voltage.</pin>
  33       <pin id="6" name="[AGND]">Analog Ground.</pin>
  34       <pin id="7" name="[MOSI:SDA:DI:ICP1:ADC4:PCINT4:PA4]">MOSI (SPI Master Output / Slave Input). SDA (Two-wire Mode USI Alternate Data Input / Output). DI (Three-wire Mode USI Alternate Data Input).ICP1 (Timer/Counter1 Input Capture Trigger). ADC4 (ADC Input Channel 4). PCINT4 (Pin Change Interrupt 4). PORTA4.</pin>
  35       <pin id="8" name="[SCK:SCL:USCK:T1:ADC5:PCINT5:PA5]">SCK (SPI Master Clock). SCL (Two-wire Mode USI Alternate Clock Input). USCK (Three-wire Mode USI Alternate Clock Input). T1 (Timer/Counter1 Clock Input). ADC5 (ADC Input Channel 5). PCINT5 (Pin Change Interrupt 5). PORTA5.</pin>
  36       <pin id="9" name="[SS:AIN0:ADC6:PCINT6:PA6]">SS (Active Low SPI Slave Select Input). AIN0 (Analog Comparator Negative Input). ADC6 (ADC Input Channel 6). PCINT6 (Pin Change Interrupt 6). PORTA6.</pin>
  37       <pin id="10" name="[AREF:XREF:AIN1:ADC7:PCINT7:PA7]">AREF (External Voltage Reference Input). XREF (Internal Voltage Reference Output). AIN1 (Analog Comparator Positive Input). ADC7 (ADC Input Channel 7). PCINT7 (Pin Change Interrupt 7). PORTA7.</pin>
  38       <pin id="11" name="[dW:RESET:OC1BX:ADC10:PCINT15:PB7]">dW (debugWIRE I/O). RESET (Active Low Reset pin). OC1BX (Output Compare and PWM Output B-X for Timer/Counter1). ADC10 (ADC Input Channel 10). PCINT15 (Pin Change Interrupt 15). PORTB7.</pin>
  39       <pin id="12" name="[INT0:OC1AX:ADC9:PCINT14:PB6]">INT0 (External Interrupt0 Input). OC1AX (Output Compare and PWM Output A-X for Timer/Counter1). ADC9 (ADC Input Channel 9). PCINT14 (Pin Change Interrupt 14). PORTB6.</pin>
  40       <pin id="13" name="[CLKO:XTAL2:OC1BW:ADC8:PCINT13:PB5]">CLKO (System clock output). XTAL2 (Chip clock Oscillator pin 2). OC1BW (Output Compare and PWM Output B-W for Timer/Counter1). ADC8 (ADC Input Channel 8). PCINT13 (Pin Change Interrupt 13). PORTB5.</pin>
  41       <pin id="14" name="[CLKI:XTAL1:OC1AW:PCINT12:PB4]">CLKI (External clock input). XTAL1 (Chip clock Oscillator pin 1). OC1AW (Output Compare and PWM Output A-W for Timer/Counter1). PCINT12 (Pin Change Interrupt 12). PORTB4.</pin>
  42       <pin id="15" name="[VCC]">Supply Voltage.</pin>
  43       <pin id="16" name="[GND]">Ground.</pin>
  44       <pin id="17" name="[OC1BV:PCINT11:PB3]">OC1BV (Output Compare and PWM Output B-V for Timer/Counter1). PCINT11 (Pin Change Interrupt 11). PORTB3.</pin>
  45       <pin id="18" name="[SCL:USCK:OC1AV:PCINT10:PB2]">SCL (Two-wire Mode USI Default Clock Input). USCK (Three-wire Mode USI Default Clock Input). OC1AV (Output Compare and PWM Output A-V for Timer/Counter1). PCINT10 (Pin Change Interrupt 10). PORTB2.</pin>
  46       <pin id="19" name="[DO:OC1BU:PCINT9:PB1]">DO (Three-wire Mode USI Default Data Output). OC1BU (Output Compare and PWM Output B-U for Timer/Counter1). PCINT9 (Pin Change Interrupt 9). PORTB1.</pin>
  47       <pin id="20" name="[SDA:DI:OC1AU:PCINT8:PB0]">SDA (Two-wire Mode USI Default Data Input / Output). DI (Three-wire Mode USI Default Data Input). OC1AU (Output Compare and PWM Output A-U for Timer/Counter1). PCINT8 (Pin Change Interrupt 8). PORTB0.</pin>
  48     </package>
  49   </packages>
  50   <memory>
  51     <flash size="16384"/>
  52     <iospace start="$0020" stop="$00FF"/>
  53     <sram size="512"/>
  54     <eram size="0"/>
  55   </memory>
  56   <ioregisters>
  57     <ioreg name="PINA" address="$00"/>
  58     <ioreg name="DDRA" address="$01"/>
  59     <ioreg name="PORTA" address="$02"/>
  60     <ioreg name="PINB" address="$03"/>
  61     <ioreg name="DDRB" address="$04"/>
  62     <ioreg name="PORTB" address="$05"/>
  63     <ioreg name="PORTCR" address="$12"/>
  64     <ioreg name="TIFR0" address="$15"/>
  65     <ioreg name="TIFR1" address="$16"/>
  66     <ioreg name="PCIFR" address="$1B"/>
  67     <ioreg name="EIFR" address="$1C"/>
  68     <ioreg name="EIMSK" address="$1D"/>
  69     <ioreg name="GPIOR0" address="$1E"/>
  70     <ioreg name="EECR" address="$1F"/>
  71     <ioreg name="EEDR" address="$20"/>
  72     <ioreg name="EEARL" address="$21"/>
  73     <ioreg name="EEARH" address="$22"/>
  74     <ioreg name="GTCCR" address="$23"/>
  75     <ioreg name="TCCR0A" address="$25"/>
  76     <ioreg name="TCCR0B" address="$26"/>
  77     <ioreg name="TCNT0" address="$27"/>
  78     <ioreg name="OCR0A" address="$28"/>
  79     <ioreg name="GPIOR1" address="$2A"/>
  80     <ioreg name="GPIOR2" address="$2B"/>
  81     <ioreg name="SPCR" address="$2C"/>
  82     <ioreg name="SPSR" address="$2D"/>
  83     <ioreg name="SPDR" address="$2E"/>
  84     <ioreg name="ACSR" address="$30"/>
  85     <ioreg name="DWDR" address="$31"/>
  86     <ioreg name="SMCR" address="$33"/>
  87     <ioreg name="MCUSR" address="$34"/>
  88     <ioreg name="MCUCR" address="$35"/>
  89     <ioreg name="SPMCSR" address="$37"/>
  90     <ioreg name="SPL" address="$3D"/>
  91     <ioreg name="SPH" address="$3E"/>
  92     <ioreg name="SREG" address="$3F"/>
  93     <ioreg name="WDTCR" address="$60"/>
  94     <ioreg name="CLKPR" address="$61"/>
  95     <ioreg name="CLKCSR" address="$62"/>
  96     <ioreg name="CLKSELR" address="$63"/>
  97     <ioreg name="PRR" address="$64"/>
  98     <ioreg name="OSCCAL" address="$66"/>
  99     <ioreg name="PCICR" address="$68"/>
 100     <ioreg name="EICRA" address="$69"/>
 101     <ioreg name="PCMSK0" address="$6B"/>
 102     <ioreg name="PCMSK1" address="$6C"/>
 103     <ioreg name="TIMSK0" address="$6E"/>
 104     <ioreg name="TIMSK1" address="$6F"/>
 105     <ioreg name="AMISCR" address="$77"/>
 106     <ioreg name="ADCL" address="$78"/>
 107     <ioreg name="ADCH" address="$79"/>
 108     <ioreg name="ADCSRA" address="$7A"/>
 109     <ioreg name="ADCSRB" address="$7B"/>
 110     <ioreg name="ADMUX" address="$7C"/>
 111     <ioreg name="DIDR0" address="$7E"/>
 112     <ioreg name="DIDR1" address="$7F"/>
 113     <ioreg name="TCCR1A" address="$80"/>
 114     <ioreg name="TCCR1B" address="$81"/>
 115     <ioreg name="TCCR1C" address="$82"/>
 116     <ioreg name="TCCR1D" address="$83"/>
 117     <ioreg name="TCNT1L" address="$84"/>
 118     <ioreg name="TCNT1H" address="$85"/>
 119     <ioreg name="ICR1L" address="$86"/>
 120     <ioreg name="ICR1H" address="$87"/>
 121     <ioreg name="OCR1AL" address="$88"/>
 122     <ioreg name="OCR1AH" address="$89"/>
 123     <ioreg name="OCR1BL" address="$8A"/>
 124     <ioreg name="OCR1BH" address="$8B"/>
 125     <ioreg name="ASSR" address="$B6"/>
 126     <ioreg name="USICR" address="$B8"/>
 127     <ioreg name="USISR" address="$B9"/>
 128     <ioreg name="USIDR" address="$BA"/>
 129     <ioreg name="USIBR" address="$BB"/>
 130     <ioreg name="USIPP" address="$BC"/>
 131     <ioreg name="LINCR" address="$C8"/>
 132     <ioreg name="LINSIR" address="$C9"/>
 133     <ioreg name="LINENIR" address="$CA"/>
 134     <ioreg name="LINERR" address="$CB"/>
 135     <ioreg name="LINBTR" address="$CC"/>
 136     <ioreg name="LINBRRL" address="$CD"/>
 137     <ioreg name="LINBRRH" address="$CE"/>
 138     <ioreg name="LINDLR" address="$CF"/>
 139     <ioreg name="LINIDR" address="$D0"/>
 140     <ioreg name="LINSEL" address="$D1"/>
 141     <ioreg name="LINDAT" address="$D2"/>
 142   </ioregisters>
 143   <hardware>
 144 <!--Everything after this needs editing!!!-->
 145     <module class="FUSE">
 146       <registers name="FUSE" memspace="FUSE">
 147           <reg size="1" name="EXTENDED" offset="0x02">
 148             <bitfield name="SELFPRGEN" mask="0x01" text="Self Programming enable" icon=""/>
 149           </reg>
 150           <reg size="1" name="HIGH" offset="0x01">
 151             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PB7 as i/o pin)" icon=""/>
 152             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 153             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 154             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always ON" icon=""/>
 155             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 156             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 157           </reg>
 158           <reg size="1" name="LOW" offset="0x00">
 159             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 160             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTB5" icon=""/>
 161             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock source" icon="" enum="ENUM_SUT_CKSEL"/>
 162           </reg>
 163         </registers>
 164     </module>
 165     <module class="LOCKBIT">
 166       <registers name="LOCKBIT" memspace="LOCKBIT">
 167           <reg size="1" name="LOCKBIT" offset="0x00">
 168             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 169           </reg>
 170         </registers>
 171     </module>
 172     <module class="PORTA">
 173       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 174           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 175           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 176           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 177         </registers>
 178     </module>
 179     <module class="PORTB">
 180       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 181           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 182           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 183           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 184         </registers>
 185     </module>
 186     <module class="LINUART">
 187       <registers name="LINUART" memspace="DATAMEM" text="" icon="io_com.bmp">
 188           <reg size="1" name="LINCR" offset="0xC8" text="LIN Control Register" icon="io_analo.bmp">
 189             <bitfield name="LSWRES" mask="0x80" text="Software Reset" icon=""/>
 190             <bitfield name="LIN13" mask="0x40" text="LIN Standard" icon=""/>
 191             <bitfield name="LCONF" mask="0x30" text="LIN Configuration bits" icon=""/>
 192             <bitfield name="LENA" mask="0x08" text="LIN or UART Enable" icon=""/>
 193             <bitfield name="LCMD" mask="0x07" text="LIN Command and Mode bits" icon=""/>
 194           </reg>
 195           <reg size="1" name="LINSIR" offset="0xC9" text="LIN Status and Interrupt Register" icon="io_flag.bmp">
 196             <bitfield name="LIDST" mask="0xE0" text="Identifier Status bits" icon=""/>
 197             <bitfield name="LBUSY" mask="0x10" text="Busy Signal" icon=""/>
 198             <bitfield name="LERR" mask="0x08" text="Error Interrupt" icon=""/>
 199             <bitfield name="LIDOK" mask="0x04" text="Identifier Interrupt" icon=""/>
 200             <bitfield name="LTXOK" mask="0x02" text="Transmit Performed Interrupt" icon=""/>
 201             <bitfield name="LRXOK" mask="0x01" text="Receive Performed Interrupt" icon=""/>
 202           </reg>
 203           <reg size="1" name="LINENIR" offset="0xCA" text="LIN Enable Interrupt Register" icon="io_analo.bmp">
 204             <bitfield name="LENERR" mask="0x08" text="Enable Error Interrupt" icon=""/>
 205             <bitfield name="LENIDOK" mask="0x04" text="Enable Identifier Interrupt" icon=""/>
 206             <bitfield name="LENTXOK" mask="0x02" text="Enable Transmit Performed Interrupt" icon=""/>
 207             <bitfield name="LENRXOK" mask="0x01" text="Enable Receive Performed Interrupt" icon=""/>
 208           </reg>
 209           <reg size="1" name="LINERR" offset="0xCB" text="LIN Error Register" icon="io_flag.bmp">
 210             <bitfield name="LABORT" mask="0x80" text="Abort Flag" icon=""/>
 211             <bitfield name="LTOERR" mask="0x40" text="Frame Time Out Error Flag" icon=""/>
 212             <bitfield name="LOVERR" mask="0x20" text="Overrun Error Flag" icon=""/>
 213             <bitfield name="LFERR" mask="0x10" text="Framing Error Flag" icon=""/>
 214             <bitfield name="LSERR" mask="0x08" text="Synchronization Error Flag" icon=""/>
 215             <bitfield name="LPERR" mask="0x04" text="Parity Error Flag" icon=""/>
 216             <bitfield name="LCERR" mask="0x02" text="Checksum Error Flag" icon=""/>
 217             <bitfield name="LBERR" mask="0x01" text="Bit Error Flag" icon=""/>
 218           </reg>
 219           <reg size="1" name="LINBTR" offset="0xCC" text="LIN Bit Timing Register" icon="io_flag.bmp">
 220             <bitfield name="LDISR" mask="0x80" text="Disable Bit Timing Resynchronization" icon=""/>
 221             <bitfield name="LBT" mask="0x3F" text="LIN Bit Timing bits" icon=""/>
 222           </reg>
 223           <reg size="1" name="LINBRRL" offset="0xCD" text="LIN Baud Rate Low Register" icon="io_timer.bmp">
 224             <bitfield name="LDIV" mask="0xFF" text="" icon=""/>
 225           </reg>
 226           <reg size="1" name="LINBRRH" offset="0xCE" text="LIN Baud Rate High Register" icon="io_timer.bmp">
 227             <bitfield name="LDIV" mask="0x0F" text="" icon="" lsb="8"/>
 228           </reg>
 229           <reg size="1" name="LINDLR" offset="0xCF" text="LIN Data Length Register" icon="io_com.bmp">
 230             <bitfield name="LTXDL" mask="0xF0" text="LIN Transmit Data Length bits" icon=""/>
 231             <bitfield name="LRXDL" mask="0x0F" text="LIN Receive Data Length bits" icon=""/>
 232           </reg>
 233           <reg size="1" name="LINIDR" offset="0xD0" text="LIN Identifier Register" icon="io_com.bmp">
 234             <bitfield name="LP" mask="0xC0" text="Parity bits" icon=""/>
 235             <bitfield name="LID" mask="0x3F" text="Identifier bit 5 or Data Length bits" icon=""/>
 236           </reg>
 237           <reg size="1" name="LINSEL" offset="0xD1" text="LIN Data Buffer Selection Register" icon="io_com.bmp">
 238             <bitfield name="LAINC" mask="0x08" text="Auto Increment of Data Buffer Index (Active Low)" icon=""/>
 239             <bitfield name="LINDX" mask="0x07" text="FIFO LIN Data Buffer Index bits" icon=""/>
 240           </reg>
 241           <reg size="1" name="LINDAT" offset="0xD2" text="LIN Data Register" icon="io_com.bmp">
 242             <bitfield name="LDATA" mask="0xFF" text="" icon=""/>
 243           </reg>
 244         </registers>
 245     </module>
 246     <module class="USI">
 247       <registers name="USI" memspace="DATAMEM" text="" icon="io_com.bmp">
 248           <reg size="1" name="USIPP" offset="0xBC" text="USI Pin Position" icon="io_com.bmp" mask="0x01"/>
 249           <reg size="1" name="USIBR" offset="0xBB" text="USI Buffer Register" icon="io_com.bmp" mask="0xFF"/>
 250           <reg size="1" name="USIDR" offset="0xBA" text="USI Data Register" icon="io_com.bmp" mask="0xFF"/>
 251           <reg size="1" name="USISR" offset="0xB9" text="USI Status Register" icon="io_flag.bmp">
 252             <bitfield name="USISIF" mask="0x80" text="Start Condition Interrupt Flag" icon=""/>
 253             <bitfield name="USIOIF" mask="0x40" text="Counter Overflow Interrupt Flag" icon=""/>
 254             <bitfield name="USIPF" mask="0x20" text="Stop Condition Flag" icon=""/>
 255             <bitfield name="USIDC" mask="0x10" text="Data Output Collision" icon=""/>
 256             <bitfield name="USICNT" mask="0x0F" text="USI Counter Value Bits" icon=""/>
 257           </reg>
 258           <reg size="1" name="USICR" offset="0xB8" text="USI Control Register" icon="io_flag.bmp">
 259             <bitfield name="USISIE" mask="0x80" text="Start Condition Interrupt Enable" icon=""/>
 260             <bitfield name="USIOIE" mask="0x40" text="Counter Overflow Interrupt Enable" icon=""/>
 261             <bitfield name="USIWM" mask="0x30" text="USI Wire Mode Bits" icon="" enum="COMM_USI_OP"/>
 262             <bitfield name="USICS" mask="0x0C" text="USI Clock Source Select Bits" icon=""/>
 263             <bitfield name="USICLK" mask="0x02" text="Clock Strobe" icon=""/>
 264             <bitfield name="USITC" mask="0x01" text="Toggle Clock Port Pin" icon=""/>
 265           </reg>
 266         </registers>
 267     </module>
 268     <module class="TIMER_COUNTER_0">
 269       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 270           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask register" icon="io_flag.bmp">
 271             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 272             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 273           </reg>
 274           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag Register" icon="io_flag.bmp">
 275             <bitfield name="OCF0A" mask="0x02" text="Output Compare Flag 0A" icon=""/>
 276             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 277           </reg>
 278           <reg size="1" name="TCCR0A" offset="0x45" text="Timer/Counter0 Control Register A" icon="io_flag.bmp">
 279             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode bits" icon=""/>
 280             <bitfield name="WGM0" mask="0x03" text="Waveform Genration Mode bits" icon=""/>
 281           </reg>
 282           <reg size="1" name="TCCR0B" offset="0x46" text="Timer/Counter0 Control Register B" icon="io_flag.bmp">
 283             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 284             <bitfield name="CS0" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 285           </reg>
 286           <reg size="1" name="TCNT2" offset="0x47" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 287           <reg size="1" name="OCR0A" offset="0x48" text="Timer/Counter0 Output Compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 288           <reg size="1" name="ASSR" offset="0xB6" text="Asynchronous Status Register" icon="io_flag.bmp">
 289             <bitfield name="EXCLK" mask="0x40" text="Enable External Clock Input" icon=""/>
 290             <bitfield name="AS0" mask="0x20" text="Asynchronous Timer/Counter0" icon=""/>
 291             <bitfield name="TCN0UB" mask="0x10" text="Timer/Counter0 Update Busy" icon=""/>
 292             <bitfield name="OCR0AUB" mask="0x08" text="Output Compare Register 0A  Update Busy" icon=""/>
 293             <bitfield name="TCR0AUB" mask="0x02" text="Timer/Counter0 Control Register A Update Busy" icon=""/>
 294             <bitfield name="TCR0BUB" mask="0x01" text="Timer/Counter0 Control Register B Update Busy" icon=""/>
 295           </reg>
 296           <reg size="1" name="GTCCR" offset="0x43" text="General Timer Counter Control register" icon="io_flag.bmp">
 297             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 298             <bitfield name="PSR0" mask="0x02" text="Prescaler Reset Asynchronous 8-bit Timer/Counter0" icon=""/>
 299             <bitfield name="PSR1" mask="0x01" text="Prescaler Reset Synchronous 16-bit Timer/Counter1" icon=""/>
 300           </reg>
 301         </registers>
 302     </module>
 303     <module class="TIMER_COUNTER_1">
 304       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 305           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 306             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 307             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 308             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 309             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 310           </reg>
 311           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter1 Interrupt Flag register" icon="io_flag.bmp">
 312             <bitfield name="ICF1" mask="0x20" text="Timer/Counter1 Input Capture Flag" icon=""/>
 313             <bitfield name="OCF1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Flag" icon=""/>
 314             <bitfield name="OCF1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Flag" icon=""/>
 315             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 316           </reg>
 317           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 318             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 319             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 320             <bitfield name="WGM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon=""/>
 321           </reg>
 322           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 323             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 324             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 325             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode Bits" icon="" lsb="2"/>
 326             <bitfield name="CS1" mask="0x07" text="Timer/Counter1 Clock Select bits" icon="" enum="CLK_SEL_3BIT_EXT"/>
 327           </reg>
 328           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter1 Control Register C" icon="io_port.bmp">
 329             <bitfield name="FOC1A" mask="0x80" text="Timer/Counter1 Force Output Compare for Channel A" icon=""/>
 330             <bitfield name="FOC1B" mask="0x40" text="Timer/Counter1 Force Output Compare for Channel B" icon=""/>
 331           </reg>
 332           <reg size="1" name="TCCR1D" offset="0x83" text="Timer/Counter1 Control Register D" icon="io_flag.bmp">
 333             <bitfield name="OC1BX" mask="0x80" text="Timer/Counter1 Output Compare X-pin Enable for Channel B" icon=""/>
 334             <bitfield name="OC1BW" mask="0x40" text="Timer/Counter1 Output Compare W-pin Enable for Channel B" icon=""/>
 335             <bitfield name="OC1BV" mask="0x20" text="Timer/Counter1 Output Compare V-pin Enable for Channel B" icon=""/>
 336             <bitfield name="OC1BU" mask="0x10" text="Timer/Counter1 Output Compare U-pin Enable for Channel B" icon=""/>
 337             <bitfield name="OC1AX" mask="0x08" text="Timer/Counter1 Output Compare X-pin Enable for Channel A" icon=""/>
 338             <bitfield name="OC1AW" mask="0x04" text="Timer/Counter1 Output Compare W-pin Enable for Channel A" icon=""/>
 339             <bitfield name="OC1AV" mask="0x02" text="Timer/Counter1 Output Compare V-pin Enable for Channel A" icon=""/>
 340             <bitfield name="OC1AU" mask="0x01" text="Timer/Counter1 Output Compare U-pin Enable for Channel A" icon=""/>
 341           </reg>
 342           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 343           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Output Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 344           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 345           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 346         </registers>
 347     </module>
 348     <module class="WATCHDOG">
 349       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 350           <reg size="1" name="WDTCR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 351             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 352             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 353             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 354             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 355             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 356           </reg>
 357         </registers>
 358     </module>
 359     <module class="EEPROM">
 360       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 361           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 362           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 363           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 364             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 365             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 366             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 367             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 368             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 369           </reg>
 370         </registers>
 371     </module>
 372     <module class="SPI">
 373       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 374           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 375           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 376             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 377             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 378             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 379           </reg>
 380           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 381             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 382             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 383             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 384             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 385             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 386             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 387             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 388           </reg>
 389         </registers>
 390     </module>
 391     <module class="AD_CONVERTER">
 392       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 393           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 394             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF8"/>
 395             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 396             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 397           </reg>
 398           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 399           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register A" icon="io_flag.bmp">
 400             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 401             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 402             <bitfield name="ADATE" mask="0x20" text="ADC  Auto Trigger Enable" icon=""/>
 403             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 404             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 405             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 406           </reg>
 407           <reg size="1" name="ADCSRB" offset="0x7B" text="The ADC Control and Status register B (Shared with ANALOG_COMPARATOR IO_MODULE)" icon="io_flag.bmp">
 408             <bitfield name="BIN" mask="0x80" text="Bipolar Input Mode" icon=""/>
 409             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Source bits" icon="" enum="ANALIG_ADC_AUTO_TRIGGER4"/>
 410           </reg>
 411           <reg size="1" name="AMISCR" offset="0x77" text="Analog Miscellaneous Control Register (Shared with CURRENT_SOURCE IO_MODULE)" icon="io_analo.bmp">
 412             <bitfield name="AREFEN" mask="0x04" text="External Voltage Reference Input Enable" icon=""/>
 413             <bitfield name="XREFEN" mask="0x02" text="Internal Voltage Reference Output Enable" icon=""/>
 414           </reg>
 415           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 416             <bitfield name="ADC10D" mask="0x04" text="" icon=""/>
 417             <bitfield name="ADC9D" mask="0x02" text="" icon=""/>
 418             <bitfield name="ADC8D" mask="0x01" text="" icon=""/>
 419           </reg>
 420           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp">
 421             <bitfield name="ADC7D" mask="0x80" text="" icon=""/>
 422             <bitfield name="ADC6D" mask="0x40" text="" icon=""/>
 423             <bitfield name="ADC5D" mask="0x20" text="" icon=""/>
 424             <bitfield name="ADC4D" mask="0x10" text="" icon=""/>
 425             <bitfield name="ADC3D" mask="0x08" text="" icon=""/>
 426             <bitfield name="ADC2D" mask="0x04" text="" icon=""/>
 427             <bitfield name="ADC1D" mask="0x02" text="" icon=""/>
 428             <bitfield name="ADC0D" mask="0x01" text="" icon=""/>
 429           </reg>
 430         </registers>
 431     </module>
 432     <module class="CURRENT_SOURCE">
 433       <registers name="CURRENT_SOURCE" memspace="DATAMEM" text="" icon="io_analo.bmp">
 434           <reg size="1" name="AMISCR" offset="0x77" text="Analog Miscellaneous Control Register (Shared with AD_CONVERTER IO_MODULE)" icon="io_analo.bmp">
 435             <bitfield name="ISRCEN" mask="0x01" text="Current Source Enable" icon=""/>
 436           </reg>
 437         </registers>
 438     </module>
 439     <module class="ANALOG_COMPARATOR">
 440       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 441           <reg size="1" name="ADCSRB" offset="0x7B" text="Analog Comparator &amp; ADC Control and Status Register B (Shared with AD_CONVERTER IO_MODULE)" icon="io_flag.bmp">
 442             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 443             <bitfield name="ACIR" mask="0x30" text="Analog Comparator Internal Voltage Reference Select Bits" icon=""/>
 444           </reg>
 445           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 446             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 447             <bitfield name="ACIRS" mask="0x40" text="Analog Comparator Internal Reference Select" icon=""/>
 448             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 449             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 450             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 451             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 452             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 453           </reg>
 454         </registers>
 455     </module>
 456     <module class="EXTERNAL_INTERRUPT">
 457       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 458           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register" icon="io_flag.bmp">
 459             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 460             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 461           </reg>
 462           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 463             <bitfield name="INT" mask="0x03" text="External Interrupt Request 1 Enable" icon=""/>
 464           </reg>
 465           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 466             <bitfield name="INTF" mask="0x03" text="External Interrupt Flags" icon=""/>
 467           </reg>
 468           <reg size="1" name="PCICR" offset="0x68" text="Pin Change Interrupt Control Register" icon="io_cpu.bmp">
 469             <bitfield name="PCIE" mask="0x03" text="Pin Change Interrupt Enable  on any PCINT14..8 pin" icon=""/>
 470           </reg>
 471           <reg size="1" name="PCIFR" offset="0x3B" text="Pin Change Interrupt Flag Register" icon="io_flag.bmp">
 472             <bitfield name="PCIF" mask="0x03" text="Pin Change Interrupt Flags" icon=""/>
 473           </reg>
 474           <reg size="1" name="PCMSK1" offset="0x6C" text="Pin Change Mask Register 1" icon="io_flag.bmp">
 475             <bitfield name="PCINT" mask="0xFF" text="Pin Change Enable Masks" icon="" lsb="8"/>
 476           </reg>
 477           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp">
 478             <bitfield name="PCINT" mask="0xFF" text="Pin Change Enable Masks" icon=""/>
 479           </reg>
 480         </registers>
 481     </module>
 482     <module class="BOOT_LOAD">
 483       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 484           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 485             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 486             <bitfield name="SIGRD" mask="0x20" text="Signature Row Read" icon=""/>
 487             <bitfield name="CTPB" mask="0x10" text="Clear Temporary Page Buffer" icon=""/>
 488             <bitfield name="RFLB" mask="0x08" text="Read Fuse and Lock Bits" icon=""/>
 489             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 490             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 491             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 492           </reg>
 493         </registers>
 494     </module>
 495     <module class="CPU">
 496       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 497           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 498             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 499             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 500             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 501             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 502             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 503             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 504             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 505             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 506           </reg>
 507           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_sreg.bmp">
 508             <bitfield name="PRLIN" mask="0x20" text="Power Reduction LINUART" icon=""/>
 509             <bitfield name="PRSPI" mask="0x10" text="Power Reduction SPI" icon=""/>
 510             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 511             <bitfield name="PRTIM0" mask="0x04" text="Power Reduction Timer/Counter0" icon=""/>
 512             <bitfield name="PRUSI" mask="0x02" text="Power Reduction USI" icon=""/>
 513             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 514           </reg>
 515           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer  Bytes" icon="io_sreg.bmp" mask="0x07FF"/>
 516           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 517             <bitfield name="BODSE" mask="0x40" text="BOD Sleep Enable" icon=""/>
 518             <bitfield name="BODS" mask="0x20" text="BOD Sleep" icon=""/>
 519             <bitfield name="PUD" mask="0x10" text="Pull-up Disable" icon=""/>
 520           </reg>
 521           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status register" icon="io_cpu.bmp">
 522             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 523             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 524             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 525             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 526           </reg>
 527           <reg size="1" name="MCUSR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 528             <bitfield name="SM" mask="0x06" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE2"/>
 529             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 530           </reg>
 531           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Register" icon="io_sreg.bmp" mask="0xFF"/>
 532           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_sreg.bmp">
 533             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 534             <bitfield name="CLKPS" mask="0x0F" text="Clock Prescaler Select Bits" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 535           </reg>
 536           <reg size="1" name="CLKSELR" offset="0x63" text="Clock Selection Register" icon="io_sreg.bmp">
 537             <bitfield name="COUT" mask="0x40" text="Clock Out - CKOUT fuse substitution" icon=""/>
 538             <bitfield name="CSUT" mask="0x30" text="Clock Start-up Time bit 1 - SUT1 fuse substitution" icon=""/>
 539             <bitfield name="CSEL" mask="0x0F" text="Clock Source Select bit 3 - CKSEL3 fuse substitution" icon=""/>
 540           </reg>
 541           <reg size="1" name="CLKCSR" offset="0x62" text="Clock Control &amp; Status Register" icon="io_sreg.bmp">
 542             <bitfield name="CLKCCE" mask="0x80" text="Clock Control Change Enable" icon=""/>
 543             <bitfield name="CLKRDY" mask="0x10" text="Clock Ready Flag" icon=""/>
 544             <bitfield name="CLKC" mask="0x0F" text="Clock Control bits" icon="" enum="CPU_CLK_COMMAND_LIST_4_BITS"/>
 545           </reg>
 546           <reg size="1" name="DWDR" offset="0x51" text="DebugWire data register" icon="io_cpu.bmp" mask="0xFF"/>
 547           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO register 2" icon="io_sreg.bmp" mask="0xFF"/>
 548           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose register 1" icon="io_sreg.bmp" mask="0xFF"/>
 549           <reg size="1" name="GPIOR0" offset="0x3E" text="General purpose register 0" icon="io_sreg.bmp" mask="0xFF"/>
 550           <reg size="1" name="PORTCR" offset="0x32" text="General purpose register 0" icon="io_port.bmp" mask="0x35"/>
 551         </registers>
 552     </module>
 553   </hardware>
 554 </device>