devices/attiny13

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="10">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$002" name="PCINT0">External Interrupt Request 0</interrupt>
   8     <interrupt vector="4" address="$003" name="TIM0_OVF">Timer/Counter0 Overflow</interrupt>
   9     <interrupt vector="5" address="$004" name="EE_RDY">EEPROM Ready</interrupt>
  10     <interrupt vector="6" address="$005" name="ANA_COMP">Analog Comparator</interrupt>
  11     <interrupt vector="7" address="$006" name="TIM0_COMPA">Timer/Counter Compare Match A</interrupt>
  12     <interrupt vector="8" address="$007" name="TIM0_COMPB">Timer/Counter Compare Match B</interrupt>
  13     <interrupt vector="9" address="$008" name="WDT">Watchdog Time-out</interrupt>
  14     <interrupt vector="10" address="$009" name="ADC">ADC Conversion Complete</interrupt>
  15   </interrupts>
  16   <memory>
  17     <flash size="1024"/>
  18     <iospace start="$20" stop="$5f"/>
  19     <sram size="64"/>
  20     <eram size="0"/>
  21   </memory>
  22   <ioregisters>
  23     <ioreg name="ADCSRB" address="$03"/>
  24     <ioreg name="ADCL" address="$04"/>
  25     <ioreg name="ADCH" address="$05"/>
  26     <ioreg name="ADCSRA" address="$06"/>
  27     <ioreg name="ADMUX" address="$07"/>
  28     <ioreg name="ACSR" address="$08"/>
  29     <ioreg name="DIDR0" address="$14"/>
  30     <ioreg name="PCMSK" address="$15"/>
  31     <ioreg name="PINB" address="$16"/>
  32     <ioreg name="DDRB" address="$17"/>
  33     <ioreg name="PORTB" address="$18"/>
  34     <ioreg name="EECR" address="$1C"/>
  35     <ioreg name="EEDR" address="$1D"/>
  36     <ioreg name="EEAR" address="$1E"/>
  37     <ioreg name="WDTCR" address="$21"/>
  38     <ioreg name="CLKPR" address="$26"/>
  39     <ioreg name="GTCCR" address="$28"/>
  40     <ioreg name="OCR0B" address="$29"/>
  41     <ioreg name="DWDR" address="$2E"/>
  42     <ioreg name="TCCR0A" address="$2F"/>
  43     <ioreg name="BODCR" address="$30"/>
  44     <ioreg name="OSCCAL" address="$31"/>
  45     <ioreg name="TCNT0" address="$32"/>
  46     <ioreg name="TCCR0B" address="$33"/>
  47     <ioreg name="MCUSR" address="$34"/>
  48     <ioreg name="MCUCR" address="$35"/>
  49     <ioreg name="OCR0A" address="$36"/>
  50     <ioreg name="SPMCSR" address="$37"/>
  51     <ioreg name="TIFR0" address="$38"/>
  52     <ioreg name="TIMSK0" address="$39"/>
  53     <ioreg name="GIFR" address="$3A"/>
  54     <ioreg name="GIMSK" address="$3B"/>
  55     <ioreg name="PRR" address="$3C"/>
  56     <ioreg name="SPL" address="$3D"/>
  57     <ioreg name="SREG" address="$3F"/>
  58   </ioregisters>
  59   <packages>
  60     <package name="PDIP" pins="8">
  61       <pin id="1" name="[PCINT5:'RESET:ADC0:PB5]"/>
  62       <pin id="2" name="[PCINT3:XTAL1:ADC3:PB3]"/>
  63       <pin id="3" name="[PCINT4:ADC2:PB4]"/>
  64       <pin id="4" name="[GND]"/>
  65       <pin id="5" name="[PB0:MOSI:AIN0:OC0A:TXD:PCINT0]"/>
  66       <pin id="6" name="[PB1:MISO:INT0:AIN1:OC0B:INT0:RXD:PCINT1]"/>
  67       <pin id="7" name="[PB2:SCK:ADC1:T0:PCINT2]"/>
  68       <pin id="8" name="[VCC]"/>
  69     </package>
  70   </packages>
  71   <hardware>
  72 <!--Everything after this needs editing!!!-->
  73     <module class="FUSE">
  74       <registers name="FUSE" memspace="FUSE">
  75           <reg size="1" name="HIGH" offset="0x01">
  76             <bitfield name="SELFPRGEN" mask="0x10" text="Self Programming enable" icon=""/>
  77             <bitfield name="DWEN" mask="0x08" text="Debug Wire enable" icon=""/>
  78             <bitfield name="BODLEVEL" mask="0x06" text="Enable BOD and select level" icon="" enum="ENUM_BODLEVEL"/>
  79             <bitfield name="RSTDISBL" mask="0x01" text="Reset Disabled (Enable PB5 as i/o pin)" icon=""/>
  80           </reg>
  81           <reg size="1" name="LOW" offset="0x00">
  82             <bitfield name="SPIEN" mask="0x80" text="Serial program downloading (SPI) enabled" icon=""/>
  83             <bitfield name="EESAVE" mask="0x40" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
  84             <bitfield name="WDTON" mask="0x20" text="Watch-dog Timer always on" icon=""/>
  85             <bitfield name="CKDIV8" mask="0x10" text="Divide clock by 8 internally" icon=""/>
  86             <bitfield name="SUT_CKSEL" mask="0x0F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
  87           </reg>
  88         </registers>
  89     </module>
  90     <module class="LOCKBIT">
  91       <registers name="LOCKBIT" memspace="LOCKBIT">
  92           <reg size="1" name="LOCKBIT" offset="0x00">
  93             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
  94           </reg>
  95         </registers>
  96     </module>
  97     <module class="AD_CONVERTER">
  98       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
  99           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp" mask="0x63"/>
 100           <reg size="1" name="ADCSRA" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 101             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 102             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 103             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 104             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 105             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 106             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 107           </reg>
 108           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 109           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_analo.bmp">
 110             <bitfield name="ADTS" mask="0x07" text="ADC Auto Trigger Sources" icon="" enum="ANALIG_ADC_AUTO_TRIGGER2"/>
 111           </reg>
 112           <reg size="1" name="DIDR0" offset="0x34" text="Digital Input Disable Register 0" icon="io_analo.bmp" mask="0x3C"/>
 113         </registers>
 114     </module>
 115     <module class="ANALOG_COMPARATOR">
 116       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 117           <reg size="1" name="ADCSRB" offset="0x23" text="ADC Control and Status Register B" icon="io_flag.bmp">
 118             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 119           </reg>
 120           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 121             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 122             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 123             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 124             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 125             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 126             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 127           </reg>
 128           <reg size="1" name="DIDR0" offset="0x34" text="" icon="">
 129             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 130             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 131           </reg>
 132         </registers>
 133     </module>
 134     <module class="EEPROM">
 135       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 136           <reg size="1" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x3F"/>
 137           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 138           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 139             <bitfield name="EEPM" mask="0x30" text="" icon="" enum="EEP_MODE"/>
 140             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 141             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 142             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 143             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 144           </reg>
 145         </registers>
 146     </module>
 147     <module class="CPU">
 148       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.com">
 149           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 150             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 151             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 152             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 153             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 154             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 155             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 156             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 157             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 158           </reg>
 159           <reg size="1" name="SPL" offset="0x5D" text="Stack Pointer Low Byte" icon="io_sreg.bmp" mask="0xFF"/>
 160           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 161             <bitfield name="PUD" mask="0x40" text="Pull-up Disable" icon=""/>
 162             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
 163             <bitfield name="SM" mask="0x18" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE2"/>
 164             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 165           </reg>
 166           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status register" icon="io_cpu.bmp">
 167             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 168             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 169             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 170             <bitfield name="PORF" mask="0x01" text="Power-On Reset Flag" icon=""/>
 171           </reg>
 172           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Register" icon="io_sreg.bmp" mask="0x7F"/>
 173           <reg size="1" name="CLKPR" offset="0x46" text="Clock Prescale Register" icon="io_sreg.bmp" mask="0x8F"/>
 174           <reg size="1" name="DWDR" offset="0x4E" text="Debug Wire Data Register" icon="io_sreg.bmp" mask="0xFF"/>
 175           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control and Status Register" icon="io_sreg.bmp">
 176             <bitfield name="CTPB" mask="0x10" text="Clear Temporary Page Buffer" icon=""/>
 177             <bitfield name="RFLB" mask="0x08" text="Read Fuse and Lock Bits" icon=""/>
 178             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 179             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 180             <bitfield name="SPMEN" mask="0x01" text="Store program Memory Enable" icon=""/>
 181           </reg>
 182           <reg size="1" name="PRR" offset="0x5C" text="Power Reduction Register" icon="io_cpu.bmp">
 183             <bitfield name="PRTIM0" mask="0x04" text="Power Reduction Timer/Counter0" icon=""/>
 184             <bitfield name="PRSPI" mask="0x02" text="Power Reduction SPI" icon=""/>
 185             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 186           </reg>
 187           <reg size="1" name="BODCR" offset="0x50" text="BOD Control Register" icon="io_cpu.bmp">
 188             <bitfield name="BPDS" mask="0x02" text="BOD Power-Down in Power-Down Sleep" icon=""/>
 189             <bitfield name="BPDSE" mask="0x01" text="BOD Power-Down Sleep Enable" icon=""/>
 190           </reg>
 191         </registers>
 192     </module>
 193     <module class="PORTB">
 194       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 195           <reg size="1" name="PORTB" offset="0x38" text="Data Register, Port B" icon="io_port.bmp" mask="0x3F"/>
 196           <reg size="1" name="DDRB" offset="0x37" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x3F"/>
 197           <reg size="1" name="PINB" offset="0x36" text="Input Pins, Port B" icon="io_port.bmp" mask="0x3F"/>
 198         </registers>
 199     </module>
 200     <module class="EXTERNAL_INTERRUPT">
 201       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 202           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
 203             <bitfield name="ISC01" mask="0x02" text="Interrupt Sense Control 0 Bit 1" icon=""/>
 204             <bitfield name="ISC00" mask="0x01" text="Interrupt Sense Control 0 Bit 0" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 205           </reg>
 206           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 207             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
 208             <bitfield name="PCIE" mask="0x20" text="Pin Change Interrupt Enable" icon=""/>
 209           </reg>
 210           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 211             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
 212             <bitfield name="PCIF" mask="0x20" text="Pin Change Interrupt Flag" icon=""/>
 213           </reg>
 214           <reg size="1" name="PCMSK" offset="0x35" text="Pin Change Enable Mask" icon="io_flag.bmp" mask="0x3F"/>
 215         </registers>
 216     </module>
 217     <module class="TIMER_COUNTER_0">
 218       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 219           <reg size="1" name="TIMSK0" offset="0x59" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 220             <bitfield name="OCIE0B" mask="0x08" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 221             <bitfield name="OCIE0A" mask="0x04" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 222             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 223           </reg>
 224           <reg size="1" name="TIFR0" offset="0x58" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 225             <bitfield name="OCF0B" mask="0x08" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 226             <bitfield name="OCF0A" mask="0x04" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 227             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 228           </reg>
 229           <reg size="1" name="OCR0A" offset="0x56" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 230           <reg size="1" name="TCCR0A" offset="0x4F" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 231             <bitfield name="COM0A" mask="0xC0" text="Compare Match Output A Mode" icon=""/>
 232             <bitfield name="COM0B" mask="0x30" text="Compare Match Output B Mode" icon=""/>
 233             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 234           </reg>
 235           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 236           <reg size="1" name="TCCR0B" offset="0x53" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 237             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 238             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 239             <bitfield name="WGM02" mask="0x08" text="Waveform Generation Mode" icon=""/>
 240             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 241           </reg>
 242           <reg size="1" name="OCR0B" offset="0x49" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 243           <reg size="1" name="GTCCR" offset="0x48" text="General Timer Conuter Register" icon="io_timer.bmp">
 244             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 245             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter0" icon=""/>
 246           </reg>
 247         </registers>
 248     </module>
 249     <module class="WATCHDOG">
 250       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 251           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 252             <bitfield name="WDTIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 253             <bitfield name="WDTIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 254             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 255             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 256             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 257           </reg>
 258         </registers>
 259     </module>
 260   </hardware>
 261 </device>