devices/atmega32u4

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="32768"/>
   6     <iospace start="$20" stop="$FF"/>
   7     <sram size="2560"/>
   8     <eram size="65536"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="PINB" address="$03"/>
  12     <ioreg name="DDRB" address="$04"/>
  13     <ioreg name="PORTB" address="$05"/>
  14     <ioreg name="PINC" address="$06"/>
  15     <ioreg name="DDRC" address="$07"/>
  16     <ioreg name="PORTC" address="$08"/>
  17     <ioreg name="PIND" address="$09"/>
  18     <ioreg name="DDRD" address="$0A"/>
  19     <ioreg name="PORTD" address="$0B"/>
  20     <ioreg name="PINE" address="$0C"/>
  21     <ioreg name="DDRE" address="$0D"/>
  22     <ioreg name="PORTE" address="$0E"/>
  23     <ioreg name="PINF" address="$0F"/>
  24     <ioreg name="DDRF" address="$10"/>
  25     <ioreg name="PORTF" address="$11"/>
  26     <ioreg name="TIFR0" address="$15"/>
  27     <ioreg name="TIFR1" address="$16"/>
  28     <ioreg name="TIFR2" address="$17"/>
  29     <ioreg name="TIFR3" address="$18"/>
  30     <ioreg name="TIFR4" address="$19"/>
  31     <ioreg name="TIFR5" address="$1A"/>
  32     <ioreg name="PCIFR" address="$1B"/>
  33     <ioreg name="EIFR" address="$1C"/>
  34     <ioreg name="EIMSK" address="$1D"/>
  35     <ioreg name="GPIOR0" address="$1E"/>
  36     <ioreg name="EECR" address="$1F"/>
  37     <ioreg name="EEDR" address="$20"/>
  38     <ioreg name="EEARL" address="$21"/>
  39     <ioreg name="EEARH" address="$22"/>
  40     <ioreg name="GTCCR" address="$23"/>
  41     <ioreg name="TCCR0A" address="$24"/>
  42     <ioreg name="TCCR0B" address="$25"/>
  43     <ioreg name="TCNT0" address="$26"/>
  44     <ioreg name="OCR0A" address="$27"/>
  45     <ioreg name="OCR0B" address="$28"/>
  46     <ioreg name="PLLCSR" address="$29"/>
  47     <ioreg name="GPIOR1" address="$2A"/>
  48     <ioreg name="GPIOR2" address="$2B"/>
  49     <ioreg name="SPCR" address="$2C"/>
  50     <ioreg name="SPSR" address="$2D"/>
  51     <ioreg name="SPDR" address="$2E"/>
  52     <ioreg name="ACSR" address="$30"/>
  53     <ioreg name="OCDR" address="$31"/>
  54     <ioreg name="PLLFRQ" address="$32"/>
  55     <ioreg name="SMCR" address="$33"/>
  56     <ioreg name="MCUSR" address="$34"/>
  57     <ioreg name="MCUCR" address="$35"/>
  58     <ioreg name="SPMCSR" address="$37"/>
  59     <ioreg name="RAMPZ" address="$3B"/>
  60     <ioreg name="EIND" address="$3C"/>
  61     <ioreg name="SPL" address="$3D"/>
  62     <ioreg name="SPH" address="$3E"/>
  63     <ioreg name="SREG" address="$3F"/>
  64     <ioreg name="WDTCSR" address="$60"/>
  65     <ioreg name="CLKPR" address="$61"/>
  66     <ioreg name="PRR0" address="$64"/>
  67     <ioreg name="PRR1" address="$65"/>
  68     <ioreg name="OSCCAL" address="$66"/>
  69     <ioreg name="RCCTRL" address="$67"/>
  70     <ioreg name="PCICR" address="$68"/>
  71     <ioreg name="EICRA" address="$69"/>
  72     <ioreg name="EICRB" address="$6A"/>
  73     <ioreg name="PCMSK0" address="$6B"/>
  74     <ioreg name="PCMSK1" address="$6C"/>
  75     <ioreg name="PCMSK2" address="$6D"/>
  76     <ioreg name="TIMSK0" address="$6E"/>
  77     <ioreg name="TIMSK1" address="$6F"/>
  78     <ioreg name="TIMSK2" address="$70"/>
  79     <ioreg name="TIMSK3" address="$71"/>
  80     <ioreg name="TIMSK4" address="$72"/>
  81     <ioreg name="TIMSK5" address="$73"/>
  82     <ioreg name="ADCL" address="$78"/>
  83     <ioreg name="ADCH" address="$79"/>
  84     <ioreg name="ADCSRA" address="$7A"/>
  85     <ioreg name="ADCSRB" address="$7B"/>
  86     <ioreg name="ADMUX" address="$7C"/>
  87     <ioreg name="DIDR2" address="$7D"/>
  88     <ioreg name="DDIR2" address="$7D"/>
  89     <ioreg name="DIDR0" address="$7E"/>
  90     <ioreg name="DIDR1" address="$7F"/>
  91     <ioreg name="TCCR1A" address="$80"/>
  92     <ioreg name="TCCR1B" address="$81"/>
  93     <ioreg name="TCCR1C" address="$82"/>
  94     <ioreg name="TCNT1L" address="$84"/>
  95     <ioreg name="TCNT1H" address="$85"/>
  96     <ioreg name="ICR1L" address="$86"/>
  97     <ioreg name="ICR1H" address="$87"/>
  98     <ioreg name="OCR1AL" address="$88"/>
  99     <ioreg name="OCR1AH" address="$89"/>
 100     <ioreg name="OCR1BL" address="$8A"/>
 101     <ioreg name="OCR1BH" address="$8B"/>
 102     <ioreg name="OCR1CL" address="$8C"/>
 103     <ioreg name="OCR1CH" address="$8D"/>
 104     <ioreg name="TCCR3A" address="$90"/>
 105     <ioreg name="TCCR3B" address="$91"/>
 106     <ioreg name="TCCR3C" address="$92"/>
 107     <ioreg name="TCNT3L" address="$94"/>
 108     <ioreg name="TCNT3H" address="$95"/>
 109     <ioreg name="ICR3L" address="$96"/>
 110     <ioreg name="ICR3H" address="$97"/>
 111     <ioreg name="OCR3AL" address="$98"/>
 112     <ioreg name="OCR3AH" address="$99"/>
 113     <ioreg name="OCR3BL" address="$9A"/>
 114     <ioreg name="OCR3BH" address="$9B"/>
 115     <ioreg name="OCR3CL" address="$9C"/>
 116     <ioreg name="OCR3CH" address="$9D"/>
 117     <ioreg name="UHCON" address="$9E"/>
 118     <ioreg name="UHINT" address="$9F"/>
 119     <ioreg name="UHIEN" address="$A0"/>
 120     <ioreg name="UHFNUML" address="$A2"/>
 121     <ioreg name="UHFNUMH" address="$A3"/>
 122     <ioreg name="UHFLEN" address="$A4"/>
 123     <ioreg name="UPINRQX" address="$A5"/>
 124     <ioreg name="UPINTX" address="$A6"/>
 125     <ioreg name="UPNUM" address="$A7"/>
 126     <ioreg name="UPRST" address="$A8"/>
 127     <ioreg name="UPCONX" address="$A9"/>
 128     <ioreg name="UPCFG0X" address="$AA"/>
 129     <ioreg name="UPCFG1X" address="$AB"/>
 130     <ioreg name="UPSTAX" address="$AC"/>
 131     <ioreg name="UPCFG2X" address="$AD"/>
 132     <ioreg name="UPIENX" address="$AE"/>
 133     <ioreg name="UPDATX" address="$AF"/>
 134     <ioreg name="TCCR2A" address="$B0"/>
 135     <ioreg name="TCCR2B" address="$B1"/>
 136     <ioreg name="TCNT2" address="$B2"/>
 137     <ioreg name="OCR2A" address="$B3"/>
 138     <ioreg name="OCR2B" address="$B4"/>
 139     <ioreg name="TWBR" address="$B8"/>
 140     <ioreg name="TWSR" address="$B9"/>
 141     <ioreg name="TWAR" address="$BA"/>
 142     <ioreg name="TWDR" address="$BB"/>
 143     <ioreg name="TWCR" address="$BC"/>
 144     <ioreg name="TWAMR" address="$BD"/>
 145     <ioreg name="TCNT4" address="$BE"/>
 146     <ioreg name="TC4H" address="$BF"/>
 147     <ioreg name="TCCR4A" address="$C0"/>
 148     <ioreg name="TCCR4B" address="$C1"/>
 149     <ioreg name="TCCR4C" address="$C2"/>
 150     <ioreg name="TCCR4D" address="$C3"/>
 151     <ioreg name="TCCR4E" address="$C4"/>
 152     <ioreg name="CLKSEL0" address="$C5"/>
 153     <ioreg name="CLKSEL1" address="$C6"/>
 154     <ioreg name="CLKSTA" address="$C7"/>
 155     <ioreg name="UCSR1A" address="$C8"/>
 156     <ioreg name="UCSR1B" address="$C9"/>
 157     <ioreg name="UCSR1C" address="$CA"/>
 158     <ioreg name="UBRR1L" address="$CC"/>
 159     <ioreg name="UBRR1H" address="$CD"/>
 160     <ioreg name="UDR1" address="$CE"/>
 161     <ioreg name="OCR4A" address="$CF"/>
 162     <ioreg name="OCR4B" address="$D0"/>
 163     <ioreg name="OCR4C" address="$D1"/>
 164     <ioreg name="OCR4D" address="$D2"/>
 165     <ioreg name="DT4" address="$D4"/>
 166     <ioreg name="UHWCON" address="$D7"/>
 167     <ioreg name="USBCON" address="$D8"/>
 168     <ioreg name="USBSTA" address="$D9"/>
 169     <ioreg name="USBINT" address="$DA"/>
 170     <ioreg name="OTGCON" address="$DD"/>
 171     <ioreg name="OTGIEN" address="$DE"/>
 172     <ioreg name="OTGINT" address="$DF"/>
 173     <ioreg name="UDCON" address="$E0"/>
 174     <ioreg name="UDINT" address="$E1"/>
 175     <ioreg name="UDIEN" address="$E2"/>
 176     <ioreg name="UDFNUML" address="$E4"/>
 177     <ioreg name="UDFNUMH" address="$E5"/>
 178     <ioreg name="UDMFN" address="$E6"/>
 179     <ioreg name="UDTST" address="$E7"/>
 180     <ioreg name="UEINTX" address="$E8"/>
 181     <ioreg name="UENUM" address="$E9"/>
 182     <ioreg name="UERST" address="$EA"/>
 183     <ioreg name="UECONX" address="$EB"/>
 184     <ioreg name="UECFG0X" address="$EC"/>
 185     <ioreg name="UECFG1X" address="$ED"/>
 186     <ioreg name="UESTA0X" address="$EE"/>
 187     <ioreg name="UESTA1X" address="$EF"/>
 188     <ioreg name="UEIENX" address="$F0"/>
 189     <ioreg name="UEDATX" address="$F1"/>
 190     <ioreg name="UEBCLX" address="$F2"/>
 191     <ioreg name="UEBCHX" address="$F3"/>
 192     <ioreg name="UEINT" address="$F4"/>
 193     <ioreg name="UPERRX" address="$F5"/>
 194     <ioreg name="UPBCLX" address="$F6"/>
 195     <ioreg name="UPBCHX" address="$F7"/>
 196     <ioreg name="UPINT" address="$F8"/>
 197     <ioreg name="OTGTCON" address="$F9"/>
 198     <ioreg name="TESTPADSTATUS" address="$FD"/>
 199     <ioreg name="TESTPADPULL" address="$FE"/>
 200     <ioreg name="TESTPADCTRL" address="$FF"/>
 201   </ioregisters>
 202   <interrupts num="43">
 203     <interrupt vector="1" address="$000" name="RESET">External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.     </interrupt>
 204     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
 205     <interrupt vector="3" address="$004" name="INT1">External Interrupt Request 1</interrupt>
 206     <interrupt vector="4" address="$006" name="INT2">External Interrupt Request 2</interrupt>
 207     <interrupt vector="5" address="$008" name="INT3">External Interrupt Request 3</interrupt>
 208     <interrupt vector="6" address="$00A" name="Reserved1">Reserved1</interrupt>
 209     <interrupt vector="7" address="$00C" name="Reserved2">Reserved2</interrupt>
 210     <interrupt vector="8" address="$00E" name="INT6">External Interrupt Request 6</interrupt>
 211     <interrupt vector="9" address="$010" name="Reserved3">Reserved3</interrupt>
 212     <interrupt vector="10" address="$012" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
 213     <interrupt vector="11" address="$014" name="USB_GEN">USB General Interrupt Request</interrupt>
 214     <interrupt vector="12" address="$016" name="USB_COM">USB Endpoint/Pipe Interrupt Communication Request</interrupt>
 215     <interrupt vector="13" address="$018" name="WDT">Watchdog Time-out Interrupt</interrupt>
 216     <interrupt vector="14" address="$01A" name="Reserved4">Reserved4</interrupt>
 217     <interrupt vector="15" address="$01C" name="Reserved5">Reserved5</interrupt>
 218     <interrupt vector="16" address="$01E" name="Reserved6">Reserved6</interrupt>
 219     <interrupt vector="17" address="$020" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
 220     <interrupt vector="18" address="$022" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
 221     <interrupt vector="19" address="$024" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
 222     <interrupt vector="20" address="$026" name="TIMER1_COMPC">Timer/Counter1 Compare Match C</interrupt>
 223     <interrupt vector="21" address="$028" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
 224     <interrupt vector="22" address="$02A" name="TIMER0_COMPA">Timer/Counter0 Compare Match A</interrupt>
 225     <interrupt vector="23" address="$02C" name="TIMER0_COMPB">Timer/Counter0 Compare Match B</interrupt>
 226     <interrupt vector="24" address="$02E" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
 227     <interrupt vector="25" address="$030" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
 228     <interrupt vector="26" address="$032" name="USART1, RX">USART1, Rx Complete</interrupt>
 229     <interrupt vector="27" address="$034" name="USART1, UDRE">USART1 Data register Empty</interrupt>
 230     <interrupt vector="28" address="$036" name="USART1, TX">USART1, Tx Complete</interrupt>
 231     <interrupt vector="29" address="$038" name="ANALOG_COMP">Analog Comparator</interrupt>
 232     <interrupt vector="30" address="$03A" name="ADC">ADC Conversion Complete</interrupt>
 233     <interrupt vector="31" address="$03C" name="EE_READY">EEPROM Ready</interrupt>
 234     <interrupt vector="32" address="$03E" name="TIMER3_CAPT">Timer/Counter3 Capture Event</interrupt>
 235     <interrupt vector="33" address="$040" name="TIMER3_COMPA">Timer/Counter3 Compare Match A</interrupt>
 236     <interrupt vector="34" address="$042" name="TIMER3_COMPB">Timer/Counter3 Compare Match B</interrupt>
 237     <interrupt vector="35" address="$044" name="TIMER3_COMPC">Timer/Counter3 Compare Match C</interrupt>
 238     <interrupt vector="36" address="$046" name="TIMER3_OVF">Timer/Counter3 Overflow</interrupt>
 239     <interrupt vector="37" address="$048" name="TWI">2-wire Serial Interface        </interrupt>
 240     <interrupt vector="38" address="$04A" name="SPM_READY">Store Program Memory Read</interrupt>
 241     <interrupt vector="39" address="$04C" name="TIMER4_COMPA">Timer/Counter4 Compare Match A</interrupt>
 242     <interrupt vector="40" address="$04E" name="TIMER4_COMPB">Timer/Counter4 Compare Match B</interrupt>
 243     <interrupt vector="41" address="$050" name="TIMER4_COMPD">Timer/Counter4 Compare Match D</interrupt>
 244     <interrupt vector="42" address="$052" name="TIMER4_OVF">Timer/Counter4 Overflow</interrupt>
 245     <interrupt vector="43" address="$054" name="TIMER4_FPF">Timer/Counter4 Fault Protection Interrupt</interrupt>
 246   </interrupts>
 247   <hardware>
 248 <!--Everything after this needs editing!!!-->
 249     <module class="FUSE">
 250       <registers name="FUSE" memspace="FUSE">
 251           <reg size="1" name="EXTENDED" offset="0x02">
 252             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 253             <bitfield name="HWBE" mask="0x08" text="Hardware Boot Enable" icon=""/>
 254           </reg>
 255           <reg size="1" name="HIGH" offset="0x01">
 256             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 257             <bitfield name="JTAGEN" mask="0x40" text="JTAG Interface Enabled" icon=""/>
 258             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 259             <bitfield name="WDTON" mask="0x10" text="Watchdog timer always on" icon=""/>
 260             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 261             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 262             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 263           </reg>
 264           <reg size="1" name="LOW" offset="0x00">
 265             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 266             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTC7" icon=""/>
 267             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 268           </reg>
 269         </registers>
 270     </module>
 271     <module class="LOCKBIT">
 272       <registers name="LOCKBIT" memspace="LOCKBIT">
 273           <reg size="1" name="LOCKBIT" offset="0x00">
 274             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 275             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 276             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 277           </reg>
 278         </registers>
 279     </module>
 280     <module class="WATCHDOG">
 281       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 282           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 283             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 284             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 285             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 286             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 287             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 288           </reg>
 289         </registers>
 290     </module>
 291     <module class="PORTD">
 292       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 293           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 294           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 295           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 296         </registers>
 297     </module>
 298     <module class="TWI">
 299       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 300           <reg size="1" name="TWAMR" offset="0xBD" text="TWI (Slave) Address Mask Register" icon="io_com.bmp">
 301             <bitfield name="TWAM" mask="0xFE" text="" icon=""/>
 302           </reg>
 303           <reg size="1" name="TWBR" offset="0xB8" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 304           <reg size="1" name="TWCR" offset="0xBC" text="TWI Control Register" icon="io_flag.bmp">
 305             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 306             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 307             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 308             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 309             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 310             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 311             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 312           </reg>
 313           <reg size="1" name="TWSR" offset="0xB9" text="TWI Status Register" icon="io_flag.bmp">
 314             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 315             <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
 316           </reg>
 317           <reg size="1" name="TWDR" offset="0xBB" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 318           <reg size="1" name="TWAR" offset="0xBA" text="TWI (Slave) Address register" icon="io_com.bmp">
 319             <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
 320             <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
 321           </reg>
 322         </registers>
 323     </module>
 324     <module class="SPI">
 325       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 326           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 327             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 328             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 329             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 330             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 331             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 332             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 333             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 334           </reg>
 335           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 336             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 337             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 338             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 339           </reg>
 340           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 341         </registers>
 342     </module>
 343     <module class="USART1">
 344       <registers name="USART1" memspace="DATAMEM" text="" icon="io_com.bmp">
 345           <reg size="1" name="UDR1" offset="0xCE" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 346           <reg size="1" name="UCSR1A" offset="0xC8" text="USART Control and Status Register A" icon="io_flag.bmp">
 347             <bitfield name="RXC1" mask="0x80" text="USART Receive Complete" icon=""/>
 348             <bitfield name="TXC1" mask="0x40" text="USART Transmitt Complete" icon=""/>
 349             <bitfield name="UDRE1" mask="0x20" text="USART Data Register Empty" icon=""/>
 350             <bitfield name="FE1" mask="0x10" text="Framing Error" icon=""/>
 351             <bitfield name="DOR1" mask="0x08" text="Data overRun" icon=""/>
 352             <bitfield name="UPE1" mask="0x04" text="Parity Error" icon=""/>
 353             <bitfield name="U2X1" mask="0x02" text="Double the USART transmission speed" icon=""/>
 354             <bitfield name="MPCM1" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 355           </reg>
 356           <reg size="1" name="UCSR1B" offset="0xC9" text="USART Control and Status Register B" icon="io_flag.bmp">
 357             <bitfield name="RXCIE1" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 358             <bitfield name="TXCIE1" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 359             <bitfield name="UDRIE1" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 360             <bitfield name="RXEN1" mask="0x10" text="Receiver Enable" icon=""/>
 361             <bitfield name="TXEN1" mask="0x08" text="Transmitter Enable" icon=""/>
 362             <bitfield name="UCSZ12" mask="0x04" text="Character Size" icon=""/>
 363             <bitfield name="RXB81" mask="0x02" text="Receive Data Bit 8" icon=""/>
 364             <bitfield name="TXB81" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 365           </reg>
 366           <reg size="1" name="UCSR1C" offset="0xCA" text="USART Control and Status Register C" icon="io_flag.bmp">
 367             <bitfield name="UMSEL1" mask="0xC0" text="USART Mode Select" icon="" enum="COMM_USART_MODE_2BIT"/>
 368             <bitfield name="UPM1" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 369             <bitfield name="USBS1" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 370             <bitfield name="UCSZ1" mask="0x06" text="Character Size" icon=""/>
 371             <bitfield name="UCPOL1" mask="0x01" text="Clock Polarity" icon=""/>
 372           </reg>
 373           <reg size="2" name="UBRR1" offset="0xCC" text="USART Baud Rate Register  Bytes" icon="io_com.bmp" mask="0x0FFF"/>
 374         </registers>
 375     </module>
 376     <module class="BOOT_LOAD">
 377       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 378           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 379             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 380             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 381             <bitfield name="SIGRD" mask="0x20" text="Signature Row Read" icon=""/>
 382             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 383             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 384             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 385             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 386             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 387           </reg>
 388         </registers>
 389     </module>
 390     <module class="EEPROM">
 391       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 392           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Address Register Low Bytes" icon="io_cpu.bmp" mask="0x0FFF"/>
 393           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 394           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 395             <bitfield name="EEPM" mask="0x30" text="EEPROM Programming Mode Bits" icon="" enum="EEP_MODE"/>
 396             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 397             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 398             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 399             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 400           </reg>
 401         </registers>
 402     </module>
 403     <module class="TIMER_COUNTER_0">
 404       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 405           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 406           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 407           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 408           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 409             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 410             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 411             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 412             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 413           </reg>
 414           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 415             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 416             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 417             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 418           </reg>
 419           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 420             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 421             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 422             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 423           </reg>
 424           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 425             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 426             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 427             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 428           </reg>
 429           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 430             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 431             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 432           </reg>
 433         </registers>
 434     </module>
 435     <module class="TIMER_COUNTER_3">
 436       <registers name="TIMER_COUNTER_3" memspace="DATAMEM" text="" icon="io_timer.bmp">
 437           <reg size="1" name="TCCR3A" offset="0x90" text="Timer/Counter3 Control Register A" icon="io_flag.bmp">
 438             <bitfield name="COM3A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 439             <bitfield name="COM3B" mask="0x30" text="Compare Output Mode 3B, bits" icon=""/>
 440             <bitfield name="COM3C" mask="0x0C" text="Compare Output Mode 3C, bits" icon=""/>
 441             <bitfield name="WGM3" mask="0x03" text="Waveform Generation Mode" icon=""/>
 442           </reg>
 443           <reg size="1" name="TCCR3B" offset="0x91" text="Timer/Counter3 Control Register B" icon="io_flag.bmp">
 444             <bitfield name="ICNC3" mask="0x80" text="Input Capture 3 Noise Canceler" icon=""/>
 445             <bitfield name="ICES3" mask="0x40" text="Input Capture 3 Edge Select" icon=""/>
 446             <bitfield name="WGM3" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 447             <bitfield name="CS3" mask="0x07" text="Prescaler source of Timer/Counter 3" icon="" enum="CLK_SEL_3BIT_EXT"/>
 448           </reg>
 449           <reg size="1" name="TCCR3C" offset="0x92" text="Timer/Counter 3 Control Register C" icon="io_flag.bmp">
 450             <bitfield name="FOC3A" mask="0x80" text="Force Output Compare 3A" icon=""/>
 451             <bitfield name="FOC3B" mask="0x40" text="Force Output Compare 3B" icon=""/>
 452             <bitfield name="FOC3C" mask="0x20" text="Force Output Compare 3C" icon=""/>
 453           </reg>
 454           <reg size="2" name="TCNT3" offset="0x94" text="Timer/Counter3  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 455           <reg size="2" name="OCR3A" offset="0x98" text="Timer/Counter3 Outbut Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 456           <reg size="2" name="OCR3B" offset="0x9A" text="Timer/Counter3 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 457           <reg size="2" name="OCR3C" offset="0x9C" text="Timer/Counter3 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 458           <reg size="2" name="ICR3" offset="0x96" text="Timer/Counter3 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 459           <reg size="1" name="TIMSK3" offset="0x71" text="Timer/Counter3 Interrupt Mask Register" icon="io_flag.bmp">
 460             <bitfield name="ICIE3" mask="0x20" text="Timer/Counter3 Input Capture Interrupt Enable" icon=""/>
 461             <bitfield name="OCIE3C" mask="0x08" text="Timer/Counter3 Output Compare C Match Interrupt Enable" icon=""/>
 462             <bitfield name="OCIE3B" mask="0x04" text="Timer/Counter3 Output Compare B Match Interrupt Enable" icon=""/>
 463             <bitfield name="OCIE3A" mask="0x02" text="Timer/Counter3 Output Compare A Match Interrupt Enable" icon=""/>
 464             <bitfield name="TOIE3" mask="0x01" text="Timer/Counter3 Overflow Interrupt Enable" icon=""/>
 465           </reg>
 466           <reg size="1" name="TIFR3" offset="0x38" text="Timer/Counter3 Interrupt Flag register" icon="io_flag.bmp">
 467             <bitfield name="ICF3" mask="0x20" text="Input Capture Flag 3" icon=""/>
 468             <bitfield name="OCF3C" mask="0x08" text="Output Compare Flag 3C" icon=""/>
 469             <bitfield name="OCF3B" mask="0x04" text="Output Compare Flag 3B" icon=""/>
 470             <bitfield name="OCF3A" mask="0x02" text="Output Compare Flag 3A" icon=""/>
 471             <bitfield name="TOV3" mask="0x01" text="Timer/Counter3 Overflow Flag" icon=""/>
 472           </reg>
 473         </registers>
 474     </module>
 475     <module class="TIMER_COUNTER_1">
 476       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 477           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 478             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 479             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 480             <bitfield name="COM1C" mask="0x0C" text="Compare Output Mode 1C, bits" icon=""/>
 481             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 482           </reg>
 483           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 484             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 485             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 486             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 487             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 488           </reg>
 489           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter 1 Control Register C" icon="io_flag.bmp">
 490             <bitfield name="FOC1A" mask="0x80" text="Force Output Compare 1A" icon=""/>
 491             <bitfield name="FOC1B" mask="0x40" text="Force Output Compare 1B" icon=""/>
 492             <bitfield name="FOC1C" mask="0x20" text="Force Output Compare 1C" icon=""/>
 493           </reg>
 494           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 495           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Outbut Compare Register A  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 496           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register B  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 497           <reg size="2" name="OCR1C" offset="0x8C" text="Timer/Counter1 Output Compare Register C  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 498           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 499           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter1 Interrupt Mask Register" icon="io_flag.bmp">
 500             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 501             <bitfield name="OCIE1C" mask="0x08" text="Timer/Counter1 Output Compare C Match Interrupt Enable" icon=""/>
 502             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Match Interrupt Enable" icon=""/>
 503             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Match Interrupt Enable" icon=""/>
 504             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 505           </reg>
 506           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter1 Interrupt Flag register" icon="io_flag.bmp">
 507             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 508             <bitfield name="OCF1C" mask="0x08" text="Output Compare Flag 1C" icon=""/>
 509             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 510             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 511             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 512           </reg>
 513         </registers>
 514     </module>
 515     <module class="JTAG">
 516       <registers name="JTAG" memspace="DATAMEM" text="" icon="io_com.bmp">
 517           <reg size="1" name="OCDR" offset="0x51" text="On-Chip Debug Related Register in I/O Memory" icon="io_com.bmp" mask="0xFF"/>
 518           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 519             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 520           </reg>
 521           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 522             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 523           </reg>
 524         </registers>
 525     </module>
 526     <module class="EXTERNAL_INTERRUPT">
 527       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 528           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 529             <bitfield name="ISC3" mask="0xC0" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 530             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 531             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 532             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 533           </reg>
 534           <reg size="1" name="EICRB" offset="0x6A" text="External Interrupt Control Register B" icon="io_flag.bmp">
 535             <bitfield name="ISC7" mask="0xC0" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 536             <bitfield name="ISC6" mask="0x30" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 537             <bitfield name="ISC5" mask="0x0C" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 538             <bitfield name="ISC4" mask="0x03" text="External Interrupt 7-4 Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 539           </reg>
 540           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 541             <bitfield name="INT" mask="0xFF" text="External Interrupt Request 7 Enable" icon=""/>
 542           </reg>
 543           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 544             <bitfield name="INTF" mask="0xFF" text="External Interrupt Flags" icon=""/>
 545           </reg>
 546           <reg size="1" name="PCMSK0" offset="0x6B" text="Pin Change Mask Register 0" icon="io_flag.bmp" mask="0xFF"/>
 547           <reg size="1" name="PCIFR" offset="0x3B" text="Pin Change Interrupt Flag Register" icon="io_flag.bmp">
 548             <bitfield name="PCIF0" mask="0x01" text="Pin Change Interrupt Flag 0" icon=""/>
 549           </reg>
 550           <reg size="1" name="PCICR" offset="0x68" text="Pin Change Interrupt Control Register" icon="io_flag.bmp">
 551             <bitfield name="PCIE0" mask="0x01" text="Pin Change Interrupt Enable 0" icon=""/>
 552           </reg>
 553         </registers>
 554     </module>
 555     <module class="TIMER_COUNTER_4">
 556       <registers name="TIMER_COUNTER_4" memspace="DATAMEM" text="" icon="io_timer.bmp">
 557           <reg size="1" name="TCCR4A" offset="0xC0" text="Timer/Counter4 Control Register A" icon="io_flag.bmp">
 558             <bitfield name="COM4A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 559             <bitfield name="COM4B" mask="0x30" text="Compare Output Mode 4B, bits" icon=""/>
 560             <bitfield name="FOC4A" mask="0x08" text="Force Output Compare Match 4A" icon=""/>
 561             <bitfield name="FOC4B" mask="0x04" text="Force Output Compare Match 4B" icon=""/>
 562             <bitfield name="PWM4A" mask="0x02" text="" icon=""/>
 563             <bitfield name="PWM4B" mask="0x01" text="" icon=""/>
 564           </reg>
 565           <reg size="1" name="TCCR4B" offset="0xC1" text="Timer/Counter4 Control Register B" icon="io_flag.bmp">
 566             <bitfield name="PWM4X" mask="0x80" text="PWM Inversion Mode" icon=""/>
 567             <bitfield name="PSR4" mask="0x40" text="Prescaler Reset Timer/Counter 4" icon=""/>
 568             <bitfield name="DTPS4" mask="0x30" text="Dead Time Prescaler Bits" icon=""/>
 569             <bitfield name="CS4" mask="0x0F" text="Clock Select Bits" icon=""/>
 570           </reg>
 571           <reg size="1" name="TCCR4C" offset="0xC2" text="Timer/Counter 4 Control Register C" icon="io_flag.bmp">
 572             <bitfield name="COM4A1S" mask="0x80" text="Comparator A Output Mode" icon=""/>
 573             <bitfield name="COM4A0S" mask="0x40" text="Comparator A Output Mode" icon=""/>
 574             <bitfield name="COM4B1S" mask="0x20" text="Comparator B Output Mode" icon=""/>
 575             <bitfield name="COM4B0S" mask="0x10" text="Comparator B Output Mode" icon=""/>
 576             <bitfield name="COM4D" mask="0x0C" text="Comparator D Output Mode" icon=""/>
 577             <bitfield name="FOC4D" mask="0x02" text="Force Output Compare Match 4D" icon=""/>
 578             <bitfield name="PWM4D" mask="0x01" text="Pulse Width Modulator D Enable" icon=""/>
 579           </reg>
 580           <reg size="1" name="TCCR4D" offset="0xC3" text="Timer/Counter 4 Control Register D" icon="io_flag.bmp">
 581             <bitfield name="FPIE4" mask="0x80" text="Fault Protection Interrupt Enable" icon=""/>
 582             <bitfield name="FPEN4" mask="0x40" text="Fault Protection Mode Enable" icon=""/>
 583             <bitfield name="FPNC4" mask="0x20" text="Fault Protection Noise Canceler" icon=""/>
 584             <bitfield name="FPES4" mask="0x10" text="Fault Protection Edge Select" icon=""/>
 585             <bitfield name="FPAC4" mask="0x08" text="Fault Protection Analog Comparator Enable" icon=""/>
 586             <bitfield name="FPF4" mask="0x04" text="Fault Protection Interrupt Flag" icon=""/>
 587             <bitfield name="WGM4" mask="0x03" text="Waveform Generation Mode bits" icon=""/>
 588           </reg>
 589           <reg size="1" name="TCCR4E" offset="0xC4" text="Timer/Counter 4 Control Register E" icon="io_flag.bmp">
 590             <bitfield name="TLOCK4" mask="0x80" text="Register Update Lock" icon=""/>
 591             <bitfield name="ENHC4" mask="0x40" text="Enhanced Compare/PWM Mode" icon=""/>
 592             <bitfield name="OC4OE" mask="0x3F" text="Output Compare Override Enable bit" icon=""/>
 593           </reg>
 594           <reg size="1" name="TCNT4" offset="0xBE" text="Timer/Counter4 Low Bytes" icon="io_timer.bmp" mask="0xFF"/>
 595           <reg size="1" name="TC4H" offset="0xBF" text="Timer/Counter4" icon="io_timer.bmp" mask="0x07"/>
 596           <reg size="1" name="OCR4A" offset="0xCF" text="Timer/Counter4 Outbut Compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 597           <reg size="1" name="OCR4B" offset="0xD0" text="Timer/Counter4 Output Compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 598           <reg size="1" name="OCR4C" offset="0xD1" text="Timer/Counter4 Output Compare Register C" icon="io_timer.bmp" mask="0xFF"/>
 599           <reg size="1" name="OCR4D" offset="0xD2" text="Timer/Counter4 Output Compare Register D" icon="io_timer.bmp" mask="0xFF"/>
 600           <reg size="1" name="TIMSK4" offset="0x72" text="Timer/Counter4 Interrupt Mask Register" icon="io_flag.bmp">
 601             <bitfield name="OCIE4D" mask="0x80" text="Timer/Counter4 Output Compare D Match Interrupt Enable" icon=""/>
 602             <bitfield name="OCIE4A" mask="0x40" text="Timer/Counter4 Output Compare A Match Interrupt Enable" icon=""/>
 603             <bitfield name="OCIE4B" mask="0x20" text="Timer/Counter4 Output Compare B Match Interrupt Enable" icon=""/>
 604             <bitfield name="TOIE4" mask="0x04" text="Timer/Counter4 Overflow Interrupt Enable" icon=""/>
 605           </reg>
 606           <reg size="1" name="TIFR4" offset="0x39" text="Timer/Counter4 Interrupt Flag register" icon="io_flag.bmp">
 607             <bitfield name="OCF4D" mask="0x80" text="Output Compare Flag 4D" icon=""/>
 608             <bitfield name="OCF4A" mask="0x40" text="Output Compare Flag 4A" icon=""/>
 609             <bitfield name="OCF4B" mask="0x20" text="Output Compare Flag 4B" icon=""/>
 610             <bitfield name="TOV4" mask="0x04" text="Timer/Counter4 Overflow Flag" icon=""/>
 611           </reg>
 612           <reg size="1" name="DT4" offset="0xD4" text="Timer/Counter 4 Dead Time Value" icon="io_flag.bmp">
 613             <bitfield name="DT4L" mask="0xFF" text="Timer/Counter 4 Dead Time Value Bits" icon=""/>
 614           </reg>
 615         </registers>
 616     </module>
 617     <module class="PORTB">
 618       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 619           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 620           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 621           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 622         </registers>
 623     </module>
 624     <module class="PORTC">
 625       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 626           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xC0"/>
 627           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xC0"/>
 628           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xC0"/>
 629         </registers>
 630     </module>
 631     <module class="PORTE">
 632       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 633           <reg size="1" name="PORTE" offset="0x2E" text="Data Register, Port E" icon="io_port.bmp" mask="0x44"/>
 634           <reg size="1" name="DDRE" offset="0x2D" text="Data Direction Register, Port E" icon="io_flag.bmp" mask="0x44"/>
 635           <reg size="1" name="PINE" offset="0x2C" text="Input Pins, Port E" icon="io_port.bmp" mask="0x44"/>
 636         </registers>
 637     </module>
 638     <module class="PORTF">
 639       <registers name="PORTF" memspace="DATAMEM" text="" icon="io_port.bmp">
 640           <reg size="1" name="PORTF" offset="0x31" text="Data Register, Port F" icon="io_port.bmp" mask="0xF3"/>
 641           <reg size="1" name="DDRF" offset="0x30" text="Data Direction Register, Port F" icon="io_flag.bmp" mask="0xF3"/>
 642           <reg size="1" name="PINF" offset="0x2F" text="Input Pins, Port F" icon="io_port.bmp" mask="0xF3"/>
 643         </registers>
 644     </module>
 645     <module class="AD_CONVERTER">
 646       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 647           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 648             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 649             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 650             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 651           </reg>
 652           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 653             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 654             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 655             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 656             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 657             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 658             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 659           </reg>
 660           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 661           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp">
 662             <bitfield name="ADHSM" mask="0x80" text="ADC High Speed Mode" icon=""/>
 663             <bitfield name="MUX5" mask="0x20" text="Analog Channel and Gain Selection Bits" icon=""/>
 664             <bitfield name="ADTS" mask="0x17" text="ADC Auto Trigger Sources" icon="" enum="ANALIG_ADC_AUTO_TRIGGER2"/>
 665           </reg>
 666           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 667             <bitfield name="ADC7D" mask="0x80" text="ADC7 Digital input Disable" icon=""/>
 668             <bitfield name="ADC6D" mask="0x40" text="ADC6 Digital input Disable" icon=""/>
 669             <bitfield name="ADC5D" mask="0x20" text="ADC5 Digital input Disable" icon=""/>
 670             <bitfield name="ADC4D" mask="0x10" text="ADC4 Digital input Disable" icon=""/>
 671             <bitfield name="ADC3D" mask="0x08" text="ADC3 Digital input Disable" icon=""/>
 672             <bitfield name="ADC2D" mask="0x04" text="ADC2 Digital input Disable" icon=""/>
 673             <bitfield name="ADC1D" mask="0x02" text="ADC1 Digital input Disable" icon=""/>
 674             <bitfield name="ADC0D" mask="0x01" text="ADC0 Digital input Disable" icon=""/>
 675           </reg>
 676           <reg size="1" name="DIDR2" offset="0x7D" text="Digital Input Disable Register 1" icon="io_analo.bmp">
 677             <bitfield name="ADC13D" mask="0x20" text="ADC13 Digital input Disable" icon=""/>
 678             <bitfield name="ADC12D" mask="0x10" text="ADC12 Digital input Disable" icon=""/>
 679             <bitfield name="ADC11D" mask="0x08" text="ADC11 Digital input Disable" icon=""/>
 680             <bitfield name="ADC10D" mask="0x04" text="ADC10 Digital input Disable" icon=""/>
 681             <bitfield name="ADC9D" mask="0x02" text="ADC9 Digital input Disable" icon=""/>
 682             <bitfield name="ADC8D" mask="0x01" text="ADC8 Digital input Disable" icon=""/>
 683           </reg>
 684         </registers>
 685     </module>
 686     <module class="ANALOG_COMPARATOR">
 687       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 688           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_flag.bmp">
 689             <bitfield name="ACME" mask="0x40" text="Analog Comparator Multiplexer Enable" icon=""/>
 690           </reg>
 691           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 692             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 693             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 694             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 695             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 696             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 697             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 698             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 699           </reg>
 700           <reg size="1" name="DIDR1" offset="0x7F" text="" icon="io_analo.bmp">
 701             <bitfield name="AIN1D" mask="0x02" text="AIN1 Digital Input Disable" icon=""/>
 702             <bitfield name="AIN0D" mask="0x01" text="AIN0 Digital Input Disable" icon=""/>
 703           </reg>
 704         </registers>
 705     </module>
 706     <module class="CPU">
 707       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 708           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 709             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 710             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 711             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 712             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 713             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 714             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 715             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 716             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 717           </reg>
 718           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 719           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 720             <bitfield name="JTD" mask="0x80" text="JTAG Interface Disable" icon=""/>
 721             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 722             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 723             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 724           </reg>
 725           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 726             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 727             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 728             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 729             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 730             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 731           </reg>
 732           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 733           <reg size="1" name="RCCTRL" offset="0x67" text="Oscillator Control Register" icon="io_cpu.bmp">
 734             <bitfield name="RCFREQ" mask="0x01" text="" icon=""/>
 735           </reg>
 736           <reg size="1" name="CLKPR" offset="0x61" text="" icon="io_cpu.bmp">
 737             <bitfield name="CLKPCE" mask="0x80" text="" icon=""/>
 738             <bitfield name="CLKPS" mask="0x0F" text="" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 739           </reg>
 740           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 741             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS"/>
 742             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 743           </reg>
 744           <reg size="1" name="EIND" offset="0x5C" text="Extended Indirect Register" icon="io_cpu.bmp" mask="0x01"/>
 745           <reg size="1" name="RAMPZ" offset="0x5B" text="RAM Page Z Select Register" icon="io_cpu.bmp" mask="0x01"/>
 746           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp">
 747             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 2 bis" icon="" lsb="20"/>
 748           </reg>
 749           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp">
 750             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 1 bis" icon="" lsb="10"/>
 751           </reg>
 752           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp">
 753             <bitfield name="GPIOR07" mask="0x80" text="General Purpose IO Register 0 bit 7" icon=""/>
 754             <bitfield name="GPIOR06" mask="0x40" text="General Purpose IO Register 0 bit 6" icon=""/>
 755             <bitfield name="GPIOR05" mask="0x20" text="General Purpose IO Register 0 bit 5" icon=""/>
 756             <bitfield name="GPIOR04" mask="0x10" text="General Purpose IO Register 0 bit 4" icon=""/>
 757             <bitfield name="GPIOR03" mask="0x08" text="General Purpose IO Register 0 bit 3" icon=""/>
 758             <bitfield name="GPIOR02" mask="0x04" text="General Purpose IO Register 0 bit 2" icon=""/>
 759             <bitfield name="GPIOR01" mask="0x02" text="General Purpose IO Register 0 bit 1" icon=""/>
 760             <bitfield name="GPIOR00" mask="0x01" text="General Purpose IO Register 0 bit 0" icon=""/>
 761           </reg>
 762           <reg size="1" name="PRR1" offset="0x65" text="Power Reduction Register1" icon="io_cpu.bmp">
 763             <bitfield name="PRUSB" mask="0x80" text="Power Reduction USB" icon=""/>
 764             <bitfield name="PRTIM3" mask="0x08" text="Power Reduction Timer/Counter3" icon=""/>
 765             <bitfield name="PRUSART1" mask="0x01" text="Power Reduction USART1" icon=""/>
 766           </reg>
 767           <reg size="1" name="PRR0" offset="0x64" text="Power Reduction Register0" icon="io_cpu.bmp">
 768             <bitfield name="PRTWI" mask="0x80" text="Power Reduction TWI" icon=""/>
 769             <bitfield name="PRTIM2" mask="0x40" text="Power Reduction Timer/Counter2" icon=""/>
 770             <bitfield name="PRTIM0" mask="0x20" text="Power Reduction Timer/Counter0" icon=""/>
 771             <bitfield name="PRTIM1" mask="0x08" text="Power Reduction Timer/Counter1" icon=""/>
 772             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 773             <bitfield name="PRUSART0" mask="0x02" text="Power Reduction USART" icon=""/>
 774             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 775           </reg>
 776           <reg size="1" name="CLKSTA" offset="0xC7" text="" icon="io_cpu.bmp">
 777             <bitfield name="RCON" mask="0x02" text="" icon=""/>
 778             <bitfield name="EXTON" mask="0x01" text="" icon=""/>
 779           </reg>
 780           <reg size="1" name="CLKSEL1" offset="0xC6" text="" icon="io_cpu.bmp">
 781             <bitfield name="RCCKSEL" mask="0xF0" text="" icon=""/>
 782             <bitfield name="EXCKSEL" mask="0x0F" text="" icon=""/>
 783           </reg>
 784           <reg size="1" name="CLKSEL0" offset="0xC5" text="" icon="io_cpu.bmp">
 785             <bitfield name="RCSUT" mask="0xC0" text="" icon=""/>
 786             <bitfield name="EXSUT" mask="0x30" text="" icon=""/>
 787             <bitfield name="RCE" mask="0x08" text="" icon=""/>
 788             <bitfield name="EXTE" mask="0x04" text="" icon=""/>
 789             <bitfield name="CLKS" mask="0x01" text="" icon=""/>
 790           </reg>
 791         </registers>
 792     </module>
 793     <module class="TIMER_COUNTER_2">
 794       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 795           <reg size="1" name="TIMSK2" offset="0x70" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 796             <bitfield name="OCIE2B" mask="0x04" text="Timer/Counter2 Output Compare Match B Interrupt Enable" icon=""/>
 797             <bitfield name="OCIE2A" mask="0x02" text="Timer/Counter2 Output Compare Match A Interrupt Enable" icon=""/>
 798             <bitfield name="TOIE2" mask="0x01" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 799           </reg>
 800           <reg size="1" name="TIFR2" offset="0x37" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 801             <bitfield name="OCF2B" mask="0x04" text="Output Compare Flag 2B" icon=""/>
 802             <bitfield name="OCF2A" mask="0x02" text="Output Compare Flag 2A" icon=""/>
 803             <bitfield name="TOV2" mask="0x01" text="Timer/Counter2 Overflow Flag" icon=""/>
 804           </reg>
 805           <reg size="1" name="TCCR2A" offset="0xB0" text="Timer/Counter2 Control Register A" icon="io_flag.bmp">
 806             <bitfield name="COM2A" mask="0xC0" text="Compare Output Mode bits" icon=""/>
 807             <bitfield name="COM2B" mask="0x30" text="Compare Output Mode bits" icon=""/>
 808             <bitfield name="WGM2" mask="0x03" text="Waveform Genration Mode" icon=""/>
 809           </reg>
 810           <reg size="1" name="TCCR2B" offset="0xB1" text="Timer/Counter2 Control Register B" icon="io_flag.bmp">
 811             <bitfield name="FOC2A" mask="0x80" text="Force Output Compare A" icon=""/>
 812             <bitfield name="FOC2B" mask="0x40" text="Force Output Compare B" icon=""/>
 813             <bitfield name="WGM22" mask="0x08" text="Waveform Generation Mode" icon=""/>
 814             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 815           </reg>
 816           <reg size="1" name="TCNT2" offset="0xB2" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 817           <reg size="1" name="OCR2B" offset="0xB4" text="Timer/Counter2 Output Compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 818           <reg size="1" name="OCR2A" offset="0xB3" text="Timer/Counter2 Output Compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 819           <reg size="1" name="GTCCR" offset="0x43" text="General Timer Counter Control register" icon="io_flag.bmp">
 820             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 821             <bitfield name="PSRASY" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 822           </reg>
 823         </registers>
 824     </module>
 825     <module class="PLL">
 826       <registers name="PLL" memspace="DATAMEM" text="" icon="io_analo.bmp">
 827           <reg size="1" name="PLLCSR" offset="0x49" text="PLL Status and Control register" icon="io_analo.bmp">
 828             <bitfield name="PINDIV" mask="0x10" text="PLL prescaler Bit 2" icon=""/>
 829             <bitfield name="PLLE" mask="0x02" text="PLL Enable Bit" icon=""/>
 830             <bitfield name="PLOCK" mask="0x01" text="PLL Lock Status Bit" icon=""/>
 831           </reg>
 832           <reg size="1" name="PLLFRQ" offset="0x52" text="PLL Frequency Control Register" icon="io_analo.bmp">
 833             <bitfield name="PINMUX" mask="0x80" text="" icon=""/>
 834             <bitfield name="PLLUSB" mask="0x40" text="" icon=""/>
 835             <bitfield name="PLLTM" mask="0x30" text="" icon=""/>
 836             <bitfield name="PDIV" mask="0x0F" text="" icon=""/>
 837           </reg>
 838         </registers>
 839     </module>
 840     <module class="USB_DEVICE">
 841       <registers name="USB_DEVICE" memspace="DATAMEM" text="" icon="io_com.bmp">
 842           <reg size="1" name="UEINT" offset="0xF4" text="" icon="io_flag.bmp" mask="0x7F"/>
 843           <reg size="1" name="UEBCHX" offset="" text="" icon="io_flag.bmp" mask="0x07"/>
 844           <reg size="1" name="UEBCLX" offset="0xF2" text="" icon="io_flag.bmp" mask="0xFF"/>
 845           <reg size="1" name="UEDATX" offset="0xF1" text="" icon="io_flag.bmp">
 846             <bitfield name="DAT" mask="0xFF" text="" icon=""/>
 847           </reg>
 848           <reg size="1" name="UEIENX" offset="0xF0" text="" icon="io_flag.bmp">
 849             <bitfield name="FLERRE" mask="0x80" text="" icon=""/>
 850             <bitfield name="NAKINE" mask="0x40" text="" icon=""/>
 851             <bitfield name="NAKOUTE" mask="0x10" text="" icon=""/>
 852             <bitfield name="RXSTPE" mask="0x08" text="" icon=""/>
 853             <bitfield name="RXOUTE" mask="0x04" text="" icon=""/>
 854             <bitfield name="STALLEDE" mask="0x02" text="" icon=""/>
 855             <bitfield name="TXINE" mask="0x01" text="" icon=""/>
 856           </reg>
 857           <reg size="1" name="UESTA1X" offset="0xEF" text="" icon="io_flag.bmp">
 858             <bitfield name="CTRLDIR" mask="0x04" text="" icon=""/>
 859             <bitfield name="CURRBK" mask="0x03" text="" icon=""/>
 860           </reg>
 861           <reg size="1" name="UESTA0X" offset="0xEE" text="" icon="io_flag.bmp">
 862             <bitfield name="CFGOK" mask="0x80" text="" icon=""/>
 863             <bitfield name="OVERFI" mask="0x40" text="" icon=""/>
 864             <bitfield name="UNDERFI" mask="0x20" text="" icon=""/>
 865             <bitfield name="DTSEQ" mask="0x0C" text="" icon=""/>
 866             <bitfield name="NBUSYBK" mask="0x03" text="" icon=""/>
 867           </reg>
 868           <reg size="1" name="UECFG1X" offset="0xED" text="" icon="io_flag.bmp">
 869             <bitfield name="EPSIZE" mask="0x70" text="" icon=""/>
 870             <bitfield name="EPBK" mask="0x0C" text="" icon=""/>
 871             <bitfield name="ALLOC" mask="0x02" text="" icon=""/>
 872           </reg>
 873           <reg size="1" name="UECFG0X" offset="0xEC" text="" icon="io_flag.bmp">
 874             <bitfield name="EPTYPE" mask="0xC0" text="" icon=""/>
 875             <bitfield name="EPDIR" mask="0x01" text="" icon=""/>
 876           </reg>
 877           <reg size="1" name="UECONX" offset="0xEB" text="" icon="io_flag.bmp">
 878             <bitfield name="STALLRQ" mask="0x20" text="" icon=""/>
 879             <bitfield name="STALLRQC" mask="0x10" text="" icon=""/>
 880             <bitfield name="RSTDT" mask="0x08" text="" icon=""/>
 881             <bitfield name="EPEN" mask="0x01" text="" icon=""/>
 882           </reg>
 883           <reg size="1" name="UERST" offset="0xEA" text="" icon="io_flag.bmp">
 884             <bitfield name="EPRST" mask="0x7F" text="" icon=""/>
 885           </reg>
 886           <reg size="1" name="UENUM" offset="0xE9" text="" icon="io_flag.bmp" mask="0x07"/>
 887           <reg size="1" name="UEINTX" offset="0xE8" text="" icon="io_flag.bmp">
 888             <bitfield name="FIFOCON" mask="0x80" text="" icon=""/>
 889             <bitfield name="NAKINI" mask="0x40" text="" icon=""/>
 890             <bitfield name="RWAL" mask="0x20" text="" icon=""/>
 891             <bitfield name="NAKOUTI" mask="0x10" text="" icon=""/>
 892             <bitfield name="RXSTPI" mask="0x08" text="" icon=""/>
 893             <bitfield name="RXOUTI" mask="0x04" text="" icon=""/>
 894             <bitfield name="STALLEDI" mask="0x02" text="" icon=""/>
 895             <bitfield name="TXINI" mask="0x01" text="" icon=""/>
 896           </reg>
 897           <reg size="1" name="UDMFN" offset="0xE6" text="" icon="io_flag.bmp">
 898             <bitfield name="FNCERR" mask="0x10" text="" icon=""/>
 899           </reg>
 900           <reg size="2" name="UDFNUM" offset="0xE4" text="" icon="io_flag.bmp" mask="0x07FF"/>
 901           <reg size="1" name="UDADDR" offset="0xE3" text="" icon="io_flag.bmp">
 902             <bitfield name="ADDEN" mask="0x80" text="" icon=""/>
 903             <bitfield name="UADD" mask="0x7F" text="" icon=""/>
 904           </reg>
 905           <reg size="1" name="UDIEN" offset="0xE2" text="" icon="io_flag.bmp">
 906             <bitfield name="UPRSME" mask="0x40" text="" icon=""/>
 907             <bitfield name="EORSME" mask="0x20" text="" icon=""/>
 908             <bitfield name="WAKEUPE" mask="0x10" text="" icon=""/>
 909             <bitfield name="EORSTE" mask="0x08" text="" icon=""/>
 910             <bitfield name="SOFE" mask="0x04" text="" icon=""/>
 911             <bitfield name="SUSPE" mask="0x01" text="" icon=""/>
 912           </reg>
 913           <reg size="1" name="UDINT" offset="0xE1" text="" icon="io_flag.bmp">
 914             <bitfield name="UPRSMI" mask="0x40" text="" icon=""/>
 915             <bitfield name="EORSMI" mask="0x20" text="" icon=""/>
 916             <bitfield name="WAKEUPI" mask="0x10" text="" icon=""/>
 917             <bitfield name="EORSTI" mask="0x08" text="" icon=""/>
 918             <bitfield name="SOFI" mask="0x04" text="" icon=""/>
 919             <bitfield name="SUSPI" mask="0x01" text="" icon=""/>
 920           </reg>
 921           <reg size="1" name="UDCON" offset="0xE0" text="" icon="io_flag.bmp">
 922             <bitfield name="LSM" mask="0x04" text="USB low speed mode" icon=""/>
 923             <bitfield name="RSTCPU" mask="0x08" text="" icon=""/>
 924             <bitfield name="RMWKUP" mask="0x02" text="" icon=""/>
 925             <bitfield name="DETACH" mask="0x01" text="" icon=""/>
 926           </reg>
 927           <reg size="1" name="USBCON" offset="0xD8" text="USB General Control Register" icon="io_flag.bmp">
 928             <bitfield name="USBE" mask="0x80" text="" icon=""/>
 929             <bitfield name="FRZCLK" mask="0x20" text="" icon=""/>
 930             <bitfield name="OTGPADE" mask="0x10" text="" icon=""/>
 931             <bitfield name="VBUSTE" mask="0x01" text="" icon=""/>
 932           </reg>
 933           <reg size="1" name="USBINT" offset="0xDA" text="" icon="io_flag.bmp">
 934             <bitfield name="VBUSTI" mask="0x01" text="" icon=""/>
 935           </reg>
 936           <reg size="1" name="USBSTA" offset="0xD9" text="" icon="io_flag.bmp">
 937             <bitfield name="SPEED" mask="0x08" text="" icon=""/>
 938             <bitfield name="VBUS" mask="0x01" text="" icon=""/>
 939           </reg>
 940           <reg size="1" name="UHWCON" offset="0xD7" text="" icon="io_flag.bmp">
 941             <bitfield name="UVREGE" mask="0x01" text="" icon=""/>
 942           </reg>
 943         </registers>
 944     </module>
 945   </hardware>
 946 </device>