devices/atmega32c1

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="32768"/>
   6     <iospace start="$0020" stop="$00FF"/>
   7     <sram size="2048"/>
   8     <eram size="2048"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="PINB" address="$03"/>
  12     <ioreg name="DDRB" address="$04"/>
  13     <ioreg name="PORTB" address="$05"/>
  14     <ioreg name="PINC" address="$06"/>
  15     <ioreg name="DDRC" address="$07"/>
  16     <ioreg name="PORTC" address="$08"/>
  17     <ioreg name="PIND" address="$09"/>
  18     <ioreg name="DDRD" address="$0A"/>
  19     <ioreg name="PORTD" address="$0B"/>
  20     <ioreg name="PINE" address="$0C"/>
  21     <ioreg name="DDRE" address="$0D"/>
  22     <ioreg name="PORTE" address="$0E"/>
  23     <ioreg name="TIFR0" address="$15"/>
  24     <ioreg name="TIFR1" address="$16"/>
  25     <ioreg name="GPIOR1" address="$19"/>
  26     <ioreg name="GPIOR2" address="$1A"/>
  27     <ioreg name="PCIFR" address="$1B"/>
  28     <ioreg name="EIFR" address="$1C"/>
  29     <ioreg name="EIMSK" address="$1D"/>
  30     <ioreg name="GPIOR0" address="$1E"/>
  31     <ioreg name="EECR" address="$1F"/>
  32     <ioreg name="EEDR" address="$20"/>
  33     <ioreg name="EEARL" address="$21"/>
  34     <ioreg name="EEARH" address="$22"/>
  35     <ioreg name="GTCCR" address="$23"/>
  36     <ioreg name="TCCR0A" address="$24"/>
  37     <ioreg name="TCCR0B" address="$25"/>
  38     <ioreg name="TCNT0" address="$26"/>
  39     <ioreg name="OCR0A" address="$27"/>
  40     <ioreg name="OCR0B" address="$28"/>
  41     <ioreg name="PLLCSR" address="$29"/>
  42     <ioreg name="SPCR" address="$2C"/>
  43     <ioreg name="SPSR" address="$2D"/>
  44     <ioreg name="SPDR" address="$2E"/>
  45     <ioreg name="ACSR" address="$30"/>
  46     <ioreg name="DWDR" address="$31"/>
  47     <ioreg name="SMCR" address="$33"/>
  48     <ioreg name="MCUSR" address="$34"/>
  49     <ioreg name="MCUCR" address="$35"/>
  50     <ioreg name="SPMCSR" address="$37"/>
  51     <ioreg name="SPL" address="$3D"/>
  52     <ioreg name="SPH" address="$3E"/>
  53     <ioreg name="SREG" address="$3F"/>
  54     <ioreg name="WDTCSR" address="$60"/>
  55     <ioreg name="CLKPR" address="$61"/>
  56     <ioreg name="PRR" address="$64"/>
  57     <ioreg name="OSCCAL" address="$66"/>
  58     <ioreg name="EICRA" address="$69"/>
  59     <ioreg name="PCMSK0" address="$6A"/>
  60     <ioreg name="PCMSK1" address="$6B"/>
  61     <ioreg name="PCMSK2" address="$6C"/>
  62     <ioreg name="PCMSK3" address="$6D"/>
  63     <ioreg name="TIMSK0" address="$6E"/>
  64     <ioreg name="TIMSK1" address="$6F"/>
  65     <ioreg name="AMP0CSR" address="$75"/>
  66     <ioreg name="AMP1CSR" address="$76"/>
  67     <ioreg name="AMP2CSR" address="$77"/>
  68     <ioreg name="ADCL" address="$78"/>
  69     <ioreg name="ADCH" address="$79"/>
  70     <ioreg name="ADCSRA" address="$7A"/>
  71     <ioreg name="ADCSRB" address="$7B"/>
  72     <ioreg name="ADMUX" address="$7C"/>
  73     <ioreg name="DIDR0" address="$7E"/>
  74     <ioreg name="DIDR1" address="$7F"/>
  75     <ioreg name="TCCR1A" address="$80"/>
  76     <ioreg name="TCCR1B" address="$81"/>
  77     <ioreg name="TCCR1C" address="$82"/>
  78     <ioreg name="TCNT1L" address="$84"/>
  79     <ioreg name="TCNT1H" address="$85"/>
  80     <ioreg name="ICR1L" address="$86"/>
  81     <ioreg name="ICR1H" address="$87"/>
  82     <ioreg name="OCR1AL" address="$88"/>
  83     <ioreg name="OCR1AH" address="$89"/>
  84     <ioreg name="OCR1BL" address="$8A"/>
  85     <ioreg name="OCR1BH" address="$8B"/>
  86     <ioreg name="DACON" address="$90"/>
  87     <ioreg name="DACL" address="$91"/>
  88     <ioreg name="DACH" address="$92"/>
  89     <ioreg name="AC0CON" address="$94"/>
  90     <ioreg name="AC1CON" address="$95"/>
  91     <ioreg name="AC2CON" address="$96"/>
  92     <ioreg name="AC3CON" address="$97"/>
  93     <ioreg name="CANPAGE" address="$ED"/>
  94     <ioreg name="CANSTMOB" address="$EE"/>
  95     <ioreg name="CANCDMOB" address="$EF"/>
  96     <ioreg name="CANIDT4" address="$F0"/>
  97     <ioreg name="CANIDT3" address="$F1"/>
  98     <ioreg name="CANIDT2" address="$F2"/>
  99     <ioreg name="CANIDT1" address="$F3"/>
 100     <ioreg name="CANIDM4" address="$F4"/>
 101     <ioreg name="CANIDM3" address="$F5"/>
 102     <ioreg name="CANIDM2" address="$F6"/>
 103     <ioreg name="CANIDM1" address="$F7"/>
 104     <ioreg name="CANSTML" address="$F8"/>
 105     <ioreg name="CANSTMH" address="$F9"/>
 106     <ioreg name="CANMSG" address="$FA"/>
 107     <ioreg name="LINCR" address="0xC8"/>
 108     <ioreg name="LINSIR" address="0xC9"/>
 109     <ioreg name="LINENIR" address="0xCA"/>
 110     <ioreg name="LINERR" address="0xCB"/>
 111     <ioreg name="LINBTR" address="0xCC"/>
 112     <ioreg name="LINBRRL" address="0xCD"/>
 113     <ioreg name="LINBRRH" address="0xCE"/>
 114     <ioreg name="LINDLR" address="0xCF"/>
 115     <ioreg name="LINIDR" address="0xD0"/>
 116     <ioreg name="LINSEL" address="0xD1"/>
 117     <ioreg name="LINDAT" address="0xD2"/>
 118     <ioreg name="CANGCON" address="0xD8"/>
 119     <ioreg name="CANGSTA" address="0xD9"/>
 120     <ioreg name="CANGIT" address="0xDA"/>
 121     <ioreg name="CANGIE" address="0xDB"/>
 122     <ioreg name="CANEN2" address="0xDC"/>
 123     <ioreg name="CANEN1" address="0xDD"/>
 124     <ioreg name="CANIE2" address="0xDE"/>
 125     <ioreg name="CANIE1" address="0xDF"/>
 126     <ioreg name="CANSIT2" address="0xE0"/>
 127     <ioreg name="CANSIT1" address="0xE1"/>
 128     <ioreg name="CANBT1" address="0xE2"/>
 129     <ioreg name="CANBT2" address="0xE3"/>
 130     <ioreg name="CANBT3" address="0xE4"/>
 131     <ioreg name="CANTCON" address="0xE5"/>
 132     <ioreg name="CANTIML" address="0xE6"/>
 133     <ioreg name="CANTIMH" address="0xE7"/>
 134     <ioreg name="CANTTCL" address="0xE8"/>
 135     <ioreg name="CANTTCH" address="0xE9"/>
 136     <ioreg name="CANTEC" address="0xEA"/>
 137     <ioreg name="CANREC" address="0xEB"/>
 138     <ioreg name="CANHPMOB" address="0xEC"/>
 139   </ioregisters>
 140   <interrupts num="31">
 141     <interrupt vector="1" address="$0000" name="RESET">External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</interrupt>
 142     <interrupt vector="2" address="$0002" name="ANACOMP0">Analog Comparator 0</interrupt>
 143     <interrupt vector="3" address="$0004" name="ANACOMP1">Analog Comparator 1</interrupt>
 144     <interrupt vector="4" address="$0006" name="ANACOMP2">Analog Comparator 2</interrupt>
 145     <interrupt vector="5" address="$0008" name="ANACOMP3">Analog Comparator 3</interrupt>
 146     <interrupt vector="6" address="$000A" name="PSC FAULT">PSC Fault</interrupt>
 147     <interrupt vector="7" address="$000C" name="PSC EC">PSC End of Cycle</interrupt>
 148     <interrupt vector="8" address="$000E" name="INT0">External Interrupt Request 0</interrupt>
 149     <interrupt vector="9" address="$0010" name="INT1">External Interrupt Request 1</interrupt>
 150     <interrupt vector="10" address="$0012" name="INT2">External Interrupt Request 2</interrupt>
 151     <interrupt vector="11" address="$0014" name="INT3">External Interrupt Request 3</interrupt>
 152     <interrupt vector="12" address="$0016" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
 153     <interrupt vector="13" address="$0018" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
 154     <interrupt vector="14" address="$001A" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
 155     <interrupt vector="15" address="$001C" name="TIMER1 OVF">Timer1/Counter1 Overflow</interrupt>
 156     <interrupt vector="16" address="$001E" name="TIMER0 COMPA">Timer/Counter0 Compare Match A</interrupt>
 157     <interrupt vector="17" address="$0020" name="TIMER0 COMPB">Timer/Counter0 Compare Match B</interrupt>
 158     <interrupt vector="18" address="$0022" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
 159     <interrupt vector="19" address="$0024" name="CAN INT">CAN MOB, Burst, General Errors</interrupt>
 160     <interrupt vector="20" address="$0026" name="CAN TOVF">CAN Timer Overflow</interrupt>
 161     <interrupt vector="21" address="$0028" name="LIN TC">LIN Transfer Complete</interrupt>
 162     <interrupt vector="22" address="$002A" name="LIN ERR">LIN Error</interrupt>
 163     <interrupt vector="23" address="$002C" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
 164     <interrupt vector="24" address="$002E" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
 165     <interrupt vector="25" address="$0030" name="PCINT2">Pin Change Interrupt Request 2</interrupt>
 166     <interrupt vector="26" address="$0032" name="PCINT3">Pin Change Interrupt Request 3</interrupt>
 167     <interrupt vector="27" address="$0034" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
 168     <interrupt vector="28" address="$0036" name="ADC">ADC Conversion Complete</interrupt>
 169     <interrupt vector="29" address="$0038" name="WDT">Watchdog Time-Out Interrupt</interrupt>
 170     <interrupt vector="30" address="$003A" name="EE READY">EEPROM Ready</interrupt>
 171     <interrupt vector="31" address="$003C" name="SPM READY">Store Program Memory Read</interrupt>
 172   </interrupts>
 173   <packages>
 174     <package name="TQFP" pins="32">
 175       <pin id="1" name="[PD2:OC1A:MISO_A:PCINT18]"/>
 176       <pin id="2" name="[PD3:TXD:TXLIN:OC0A:SS:MOSI_A:PCINT19]"/>
 177       <pin id="3" name="[PC1:OC1B:SS_A:PCINT9]"/>
 178       <pin id="4" name="[VCC]"/>
 179       <pin id="5" name="[GND]"/>
 180       <pin id="6" name="[PC2:T0:TXCAN:PCINT10]"/>
 181       <pin id="7" name="[PC3:T1:RXCAN:ICP1B:PCINT11]"/>
 182       <pin id="8" name="[PB0:MISO:PCINT0]"/>
 183       <pin id="9" name="[PB1:MOSI:PCINT1]"/>
 184       <pin id="10" name="[PE1:OC0B:XTAL1:PCINT25]"/>
 185       <pin id="11" name="[PE2:ADC0:XTAL2:PCINT26]"/>
 186       <pin id="12" name="[PD4:ADC1:RXD:RXLIN:ICP1A:SCK_A:PCINT20]"/>
 187       <pin id="13" name="[PD5:ADC2:ACMP2:PCINT21]"/>
 188       <pin id="14" name="[PD6:ADC3:ACMPN2:INT0:PCINT22]"/>
 189       <pin id="15" name="[PD7:ACMP0:PCINT23]"/>
 190       <pin id="16" name="[PB2:ADC5:INT1:ACMPN0:PCINT2]"/>
 191       <pin id="17" name="[PC4:ADC8:AMP1-:ACMPN3:PCINT12]"/>
 192       <pin id="18" name="[PC5:ADC9:AMP1+:ACMP3:PCINT13]"/>
 193       <pin id="19" name="[AVCC]"/>
 194       <pin id="20" name="[AGND]"/>
 195       <pin id="21" name="[AREF]"/>
 196       <pin id="22" name="[PC6:ADC10:ACMP1:PCINT14]"/>
 197       <pin id="23" name="[PB3:AMP0-:PCINT3]"/>
 198       <pin id="24" name="[PB4:AMP0+:PCINT4]"/>
 199       <pin id="25" name="[PC7:D2A:AMP2+:PCINT15]"/>
 200       <pin id="26" name="[PB5:ADC6:INT2:ACMPN1:AMP2-:PCINT5]"/>
 201       <pin id="27" name="[PB6:ADC7:PCINT6]"/>
 202       <pin id="28" name="[PB7:ADC4:SCK:PCINT7]"/>
 203       <pin id="29" name="[PD0:PCINT16]"/>
 204       <pin id="30" name="[PC0:INT3:PCINT8]"/>
 205       <pin id="31" name="[PE0:RESET:OCD:PCINT24]"/>
 206       <pin id="32" name="[PD1:CLK0:PCINT17]"/>
 207     </package>
 208   </packages>
 209   <hardware>
 210 <!--Everything after this needs editing!!!-->
 211     <module class="FUSE">
 212       <registers name="FUSE" memspace="FUSE">
 213           <reg size="1" name="EXTENDED" offset="0x02">
 214             <bitfield name="PSCRB" mask="0x20" text="PSC Reset Behavior" icon=""/>
 215             <bitfield name="PSCRVA" mask="0x10" text="PSCOUTnA Reset Value" icon=""/>
 216             <bitfield name="PSCRVB" mask="0x08" text="PSC0UTnB Reset Value" icon=""/>
 217             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector Trigger Level" icon="" enum="ENUM_BODLEVEL"/>
 218           </reg>
 219           <reg size="1" name="HIGH" offset="0x01">
 220             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PC6 as i/o pin)" icon=""/>
 221             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 222             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 223             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
 224             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 225             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 226             <bitfield name="BOOTRST" mask="0x01" text="Select Reset Vector" icon=""/>
 227           </reg>
 228           <reg size="1" name="LOW" offset="0x00">
 229             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 230             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTD1" icon=""/>
 231             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 232           </reg>
 233         </registers>
 234     </module>
 235     <module class="LOCKBIT">
 236       <registers name="LOCKBIT" memspace="LOCKBIT">
 237           <reg size="1" name="LOCKBIT" offset="0x00">
 238             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 239             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 240             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 241           </reg>
 242         </registers>
 243     </module>
 244     <module class="PORTB">
 245       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 246           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 247           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 248           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 249         </registers>
 250     </module>
 251     <module class="PORTC">
 252       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 253           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 254           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 255           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 256         </registers>
 257     </module>
 258     <module class="PORTD">
 259       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 260           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 261           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 262           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 263         </registers>
 264     </module>
 265     <module class="BOOT_LOAD">
 266       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 267           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 268             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 269             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 270             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 271             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 272             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 273             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 274             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 275           </reg>
 276         </registers>
 277     </module>
 278     <module class="CAN">
 279       <registers name="CAN" memspace="DATAMEM" text="" icon="io_com.bmp">
 280           <reg size="1" name="CANGCON" offset="0xD8" text="CAN General Control Register" icon="register.bmp">
 281             <bitfield name="ABRQ" mask="0x80" text="Abort Request" icon=""/>
 282             <bitfield name="OVRQ" mask="0x40" text="Overload Frame Request" icon=""/>
 283             <bitfield name="TTC" mask="0x20" text="Time Trigger Communication" icon=""/>
 284             <bitfield name="SYNTTC" mask="0x10" text="Synchronization of TTC" icon=""/>
 285             <bitfield name="LISTEN" mask="0x08" text="Listening Mode" icon=""/>
 286             <bitfield name="TEST" mask="0x04" text="Test Mode" icon=""/>
 287             <bitfield name="ENASTB" mask="0x02" text="Enable / Standby" icon=""/>
 288             <bitfield name="SWRES" mask="0x01" text="Software Reset Request" icon=""/>
 289           </reg>
 290           <reg size="1" name="CANGSTA" offset="0xD9" text="CAN General Status Register" icon="io_flag.bmp">
 291             <bitfield name="OVFG" mask="0x40" text="Overload Frame Flag" icon=""/>
 292             <bitfield name="TXBSY" mask="0x10" text="Transmitter Busy" icon=""/>
 293             <bitfield name="RXBSY" mask="0x08" text="Receiver Busy" icon=""/>
 294             <bitfield name="ENFG" mask="0x04" text="Enable Flag" icon=""/>
 295             <bitfield name="BOFF" mask="0x02" text="Bus Off Mode" icon=""/>
 296             <bitfield name="ERRP" mask="0x01" text="Error Passive Mode" icon=""/>
 297           </reg>
 298           <reg size="1" name="CANGIT" offset="0xDA" text="CAN General Interrupt Register Flags" icon="io_flag.bmp">
 299             <bitfield name="CANIT" mask="0x80" text="General Interrupt Flag" icon=""/>
 300             <bitfield name="BOFFIT" mask="0x40" text="Bus Off Interrupt Flag" icon=""/>
 301             <bitfield name="OVRTIM" mask="0x20" text="Overrun CAN Timer Flag" icon=""/>
 302             <bitfield name="BXOK" mask="0x10" text="Burst Receive Interrupt Flag" icon=""/>
 303             <bitfield name="SERG" mask="0x08" text="Stuff Error General Flag" icon=""/>
 304             <bitfield name="CERG" mask="0x04" text="CRC Error General Flag" icon=""/>
 305             <bitfield name="FERG" mask="0x02" text="Form Error General Flag" icon=""/>
 306             <bitfield name="AERG" mask="0x01" text="Ackknowledgement Error General Flag" icon=""/>
 307           </reg>
 308           <reg size="1" name="CANGIE" offset="0xDB" text="CAN General Interrupt Enable Register" icon="register.bmp">
 309             <bitfield name="ENIT" mask="0x80" text="Enable all Interrupts" icon=""/>
 310             <bitfield name="ENBOFF" mask="0x40" text="Enable Bus Off Interrupt" icon=""/>
 311             <bitfield name="ENRX" mask="0x20" text="Enable Receive Interrupt" icon=""/>
 312             <bitfield name="ENTX" mask="0x10" text="Enable Transmitt Interrupt" icon=""/>
 313             <bitfield name="ENERR" mask="0x08" text="Enable MOb Error Interrupt" icon=""/>
 314             <bitfield name="ENBX" mask="0x04" text="Enable Burst Receive Interrupt" icon=""/>
 315             <bitfield name="ENERG" mask="0x02" text="Enable General Error Interrupt" icon=""/>
 316             <bitfield name="ENOVRT" mask="0x01" text="Enable CAN Timer Overrun Interrupt" icon=""/>
 317           </reg>
 318           <reg size="1" name="CANEN2" offset="0xDC" text="Enable MOb Register 2" icon="register.bmp">
 319             <bitfield name="ENMOB" mask="0x3F" text="Enable MObs" icon=""/>
 320           </reg>
 321           <reg size="1" name="CANEN1" offset="0xDD" text="Enable MOb Register 1(empty)" icon="register.bmp" mask="0x00"/>
 322           <reg size="1" name="CANIE2" offset="0xDE" text="Enable Interrupt MOb Register 2" icon="register.bmp">
 323             <bitfield name="IEMOB" mask="0x3F" text="Interrupt Enable  MObs" icon=""/>
 324           </reg>
 325           <reg size="1" name="CANIE1" offset="0xDF" text="Enable Interrupt MOb Register 1 (empty)" icon="register.bmp" mask="0x00"/>
 326           <reg size="1" name="CANSIT2" offset="0xE0" text="CAN Status Interrupt MOb Register 2" icon="io_flag.bmp">
 327             <bitfield name="SIT" mask="0x3F" text="Status of Interrupt MObs" icon=""/>
 328           </reg>
 329           <reg size="1" name="CANSIT1" offset="0xE1" text="CAN Status Interrupt MOb Register 1 (empty)" icon="io_flag.bmp" mask="0x00"/>
 330           <reg size="1" name="CANBT1" offset="0xE2" text="CAN Bit Timing Register 1" icon="register.bmp">
 331             <bitfield name="BRP" mask="0x7E" text="Baud Rate Prescaler bits" icon=""/>
 332           </reg>
 333           <reg size="1" name="CANBT2" offset="0xE3" text="CAN Bit Timing Register 2" icon="register.bmp">
 334             <bitfield name="SJW" mask="0x60" text="Re-Sync Jump Width bits" icon=""/>
 335             <bitfield name="PRS" mask="0x0E" text="Propagation Time Segment bits" icon=""/>
 336           </reg>
 337           <reg size="1" name="CANBT3" offset="0xE4" text="CAN Bit Timing Register 3" icon="register.bmp">
 338             <bitfield name="PHS2" mask="0x70" text="Phase Segment 2 bits" icon=""/>
 339             <bitfield name="PHS1" mask="0x0E" text="Phase Segment 1 bits" icon=""/>
 340             <bitfield name="SMP" mask="0x01" text="Sample Type" icon=""/>
 341           </reg>
 342           <reg size="1" name="CANTCON" offset="0xE5" text="Timer Control Register" icon="register.bmp" mask="0x00"/>
 343           <reg size="1" name="CANTIML" offset="0xE6" text="Timer Register Low" icon="register.bmp" mask="0x00"/>
 344           <reg size="1" name="CANTIMH" offset="0xE7" text="Timer Register High" icon="register.bmp" mask="0x00"/>
 345           <reg size="1" name="CANTTCL" offset="0xE8" text="TTC Timer Register Low" icon="register.bmp" mask="0x00"/>
 346           <reg size="1" name="CANTTCH" offset="0xE9" text="TTC Timer Register High" icon="register.bmp" mask="0x00"/>
 347           <reg size="1" name="CANTEC" offset="0xEA" text="Transmit Error Counter Register" icon="register.bmp" mask="0x00"/>
 348           <reg size="1" name="CANREC" offset="0xEB" text="Receive Error Counter Register" icon="register.bmp" mask="0x00"/>
 349           <reg size="1" name="CANHPMOB" offset="0xEC" text="Highest Priority MOb Register" icon="register.bmp">
 350             <bitfield name="HPMOB" mask="0xF0" text="Highest Priority MOb Number bits" icon=""/>
 351             <bitfield name="CGP" mask="0x0F" text="CAN General Purpose bits" icon=""/>
 352           </reg>
 353           <reg size="1" name="CANPAGE" offset="0xED" text="Page MOb Register" icon="register.bmp">
 354             <bitfield name="MOBNB" mask="0xF0" text="MOb Number bits" icon=""/>
 355             <bitfield name="AINC" mask="0x08" text="MOb Data Buffer Auto Increment (Active Low)" icon=""/>
 356             <bitfield name="INDX" mask="0x07" text="Data Buffer Index bits" icon=""/>
 357           </reg>
 358           <reg size="1" name="CANSTMOB" offset="0xEE" text="MOb Status Register" icon="io_flag.bmp">
 359             <bitfield name="DLCW" mask="0x80" text="Data Length Code Warning on MOb" icon=""/>
 360             <bitfield name="TXOK" mask="0x40" text="Transmit OK on MOb" icon=""/>
 361             <bitfield name="RXOK" mask="0x20" text="Receive OK on MOb" icon=""/>
 362             <bitfield name="BERR" mask="0x10" text="Bit Error on MOb" icon=""/>
 363             <bitfield name="SERR" mask="0x08" text="Stuff Error on MOb" icon=""/>
 364             <bitfield name="CERR" mask="0x04" text="CRC Error on MOb" icon=""/>
 365             <bitfield name="FERR" mask="0x02" text="Form Error on MOb" icon=""/>
 366             <bitfield name="AERR" mask="0x01" text="Ackknowledgement Error on MOb" icon=""/>
 367           </reg>
 368           <reg size="1" name="CANCDMOB" offset="0xEF" text="MOb Control and DLC Register" icon="register.bmp">
 369             <bitfield name="CONMOB" mask="0xC0" text="MOb Config bits" icon=""/>
 370             <bitfield name="RPLV" mask="0x20" text="Reply Valid" icon=""/>
 371             <bitfield name="IDE" mask="0x10" text="Identifier Extension" icon=""/>
 372             <bitfield name="DLC" mask="0x0F" text="Data Length Code bits" icon=""/>
 373           </reg>
 374           <reg size="1" name="CANIDT4" offset="0xF0" text="Identifier Tag Register 4" icon="register.bmp">
 375             <bitfield name="IDT" mask="0xF8" text="" icon=""/>
 376             <bitfield name="RTRTAG" mask="0x04" text="" icon=""/>
 377             <bitfield name="RB1TAG" mask="0x02" text="" icon=""/>
 378             <bitfield name="RB0TAG" mask="0x01" text="" icon=""/>
 379           </reg>
 380           <reg size="1" name="CANIDT3" offset="0xF1" text="Identifier Tag Register 3" icon="register.bmp" mask="0xFF"/>
 381           <reg size="1" name="CANIDT2" offset="0xF2" text="Identifier Tag Register 2" icon="register.bmp" mask="0xFF"/>
 382           <reg size="1" name="CANIDT1" offset="0xF3" text="Identifier Tag Register 1" icon="register.bmp" mask="0xFF"/>
 383           <reg size="1" name="CANIDM4" offset="0xF4" text="Identifier Mask Register 4" icon="register.bmp" mask="0xFD"/>
 384           <reg size="1" name="CANIDM3" offset="0xF5" text="Identifier Mask Register 3" icon="register.bmp" mask="0xFF"/>
 385           <reg size="1" name="CANIDM2" offset="0xF6" text="Identifier Mask Register 2" icon="register.bmp" mask="0xFF"/>
 386           <reg size="1" name="CANIDM1" offset="0xF7" text="Identifier Mask Register 1" icon="register.bmp" mask="0xFF"/>
 387           <reg size="1" name="CANSTML" offset="0xF8" text="Time Stamp Register Low" icon="register.bmp" mask="0x00"/>
 388           <reg size="1" name="CANSTMH" offset="0xF9" text="Time Stamp Register High" icon="register.bmp" mask="0x00"/>
 389           <reg size="1" name="CANMSG" offset="0xFA" text="Message Data Register" icon="register.bmp" mask="0x00"/>
 390         </registers>
 391     </module>
 392     <module class="ANALOG_COMPARATOR">
 393       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 394           <reg size="1" name="AC0CON" offset="0x94" text="Analog Comparator 0 Control Register" icon="io_flag.bmp">
 395             <bitfield name="AC0EN" mask="0x80" text="Analog Comparator 0 Enable Bit" icon=""/>
 396             <bitfield name="AC0IE" mask="0x40" text="Analog Comparator 0 Interrupt Enable Bit" icon=""/>
 397             <bitfield name="AC0IS" mask="0x30" text="Analog Comparator 0  Interrupt Select Bits" icon=""/>
 398             <bitfield name="ACCKSEL" mask="0x08" text="Analog Comparator Clock Select" icon=""/>
 399             <bitfield name="AC0M" mask="0x07" text="Analog Comparator 0 Multiplexer Register" icon=""/>
 400           </reg>
 401           <reg size="1" name="AC1CON" offset="0x95" text="Analog Comparator 1 Control Register" icon="io_flag.bmp">
 402             <bitfield name="AC1EN" mask="0x80" text="Analog Comparator 1 Enable Bit" icon=""/>
 403             <bitfield name="AC1IE" mask="0x40" text="Analog Comparator 1 Interrupt Enable Bit" icon=""/>
 404             <bitfield name="AC1IS" mask="0x30" text="Analog Comparator 1  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 405             <bitfield name="AC1ICE" mask="0x08" text="Analog Comparator 1 Interrupt Capture Enable Bit" icon=""/>
 406             <bitfield name="AC1M" mask="0x07" text="Analog Comparator 1 Multiplexer Register" icon=""/>
 407           </reg>
 408           <reg size="1" name="AC2CON" offset="0x96" text="Analog Comparator 2 Control Register" icon="io_flag.bmp">
 409             <bitfield name="AC2EN" mask="0x80" text="Analog Comparator 2 Enable Bit" icon=""/>
 410             <bitfield name="AC2IE" mask="0x40" text="Analog Comparator 2 Interrupt Enable Bit" icon=""/>
 411             <bitfield name="AC2IS" mask="0x30" text="Analog Comparator 2  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 412             <bitfield name="AC2M" mask="0x07" text="Analog Comparator 2 Multiplexer Register" icon=""/>
 413           </reg>
 414           <reg size="1" name="AC3CON" offset="0x97" text="Analog Comparator 3 Control Register" icon="io_flag.bmp">
 415             <bitfield name="AC3EN" mask="0x80" text="Analog Comparator 3 Enable Bit" icon=""/>
 416             <bitfield name="AC3IE" mask="0x40" text="Analog Comparator 3 Interrupt Enable Bit" icon=""/>
 417             <bitfield name="AC3IS" mask="0x30" text="Analog Comparator 3  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 418             <bitfield name="AC3M" mask="0x07" text="Analog Comparator 3 Multiplexer Register" icon=""/>
 419           </reg>
 420           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Status Register" icon="io_flag.bmp">
 421             <bitfield name="AC3IF" mask="0x80" text="Analog Comparator 3 Interrupt Flag Bit" icon=""/>
 422             <bitfield name="AC2IF" mask="0x40" text="Analog Comparator 2 Interrupt Flag Bit" icon=""/>
 423             <bitfield name="AC1IF" mask="0x20" text="Analog Comparator 1  Interrupt Flag Bit" icon=""/>
 424             <bitfield name="AC0IF" mask="0x10" text="Analog Comparator 0 Interrupt Flag Bit" icon=""/>
 425             <bitfield name="AC3O" mask="0x08" text="Analog Comparator 3 Output Bit" icon=""/>
 426             <bitfield name="AC2O" mask="0x04" text="Analog Comparator 2 Output Bit" icon=""/>
 427             <bitfield name="AC1O" mask="0x02" text="Analog Comparator 1 Output Bit" icon=""/>
 428             <bitfield name="AC0O" mask="0x01" text="Analog Comparator 0 Output Bit" icon=""/>
 429           </reg>
 430         </registers>
 431     </module>
 432     <module class="DA_CONVERTER">
 433       <registers name="DA_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 434           <reg size="1" name="DACH" offset="0x92" text="DAC Data Register High Byte" icon="io_analo.bmp">
 435             <bitfield name="DACH" mask="0xFF" text="DAC Data Register High Byte Bits" icon=""/>
 436           </reg>
 437           <reg size="1" name="DACL" offset="0x91" text="DAC Data Register Low Byte" icon="io_analo.bmp">
 438             <bitfield name="DACL" mask="0xFF" text="DAC Data Register Low Byte Bits" icon=""/>
 439           </reg>
 440           <reg size="1" name="DACON" offset="0x90" text="DAC Control Register" icon="io_analo.bmp">
 441             <bitfield name="DAATE" mask="0x80" text="DAC Auto Trigger Enable Bit" icon=""/>
 442             <bitfield name="DATS" mask="0x70" text="DAC Trigger Selection Bits" icon="" enum="ANALIG_DAC_AUTO_TRIGGER"/>
 443             <bitfield name="DALA" mask="0x04" text="DAC Left Adjust" icon=""/>
 444             <bitfield name="DAEN" mask="0x01" text="DAC Enable Bit" icon=""/>
 445           </reg>
 446         </registers>
 447     </module>
 448     <module class="CPU">
 449       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 450           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 451             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 452             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 453             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 454             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 455             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 456             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 457             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 458             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 459           </reg>
 460           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 461           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 462             <bitfield name="SPIPS" mask="0x80" text="SPI Pin Select" icon=""/>
 463             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 464             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 465             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 466           </reg>
 467           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 468             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 469             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 470             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 471             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 472           </reg>
 473           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0x7F"/>
 474           <reg size="1" name="CLKPR" offset="0x61" text="" icon="io_cpu.bmp">
 475             <bitfield name="CLKPCE" mask="0x80" text="" icon=""/>
 476             <bitfield name="CLKPS" mask="0x0F" text="" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 477           </reg>
 478           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 479             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS4"/>
 480             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 481           </reg>
 482           <reg size="1" name="GPIOR2" offset="0x3A" text="General Purpose IO Register 2" icon="io_cpu.bmp">
 483             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 2 bis" icon="" lsb="20"/>
 484           </reg>
 485           <reg size="1" name="GPIOR1" offset="0x39" text="General Purpose IO Register 1" icon="io_cpu.bmp">
 486             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 1 bis" icon="" lsb="10"/>
 487           </reg>
 488           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp">
 489             <bitfield name="GPIOR07" mask="0x80" text="General Purpose IO Register 0 bit 7" icon=""/>
 490             <bitfield name="GPIOR06" mask="0x40" text="General Purpose IO Register 0 bit 6" icon=""/>
 491             <bitfield name="GPIOR05" mask="0x20" text="General Purpose IO Register 0 bit 5" icon=""/>
 492             <bitfield name="GPIOR04" mask="0x10" text="General Purpose IO Register 0 bit 4" icon=""/>
 493             <bitfield name="GPIOR03" mask="0x08" text="General Purpose IO Register 0 bit 3" icon=""/>
 494             <bitfield name="GPIOR02" mask="0x04" text="General Purpose IO Register 0 bit 2" icon=""/>
 495             <bitfield name="GPIOR01" mask="0x02" text="General Purpose IO Register 0 bit 1" icon=""/>
 496             <bitfield name="GPIOR00" mask="0x01" text="General Purpose IO Register 0 bit 0" icon=""/>
 497           </reg>
 498           <reg size="1" name="PLLCSR" offset="0x49" text="PLL Control And Status Register" icon="io_sreg.bmp">
 499             <bitfield name="PLLF" mask="0x04" text="PLL Factor" icon=""/>
 500             <bitfield name="PLLE" mask="0x02" text="PLL Enable" icon=""/>
 501             <bitfield name="PLOCK" mask="0x01" text="PLL Lock Detector" icon=""/>
 502           </reg>
 503           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 504             <bitfield name="PRCAN" mask="0x40" text="Power Reduction CAN" icon=""/>
 505             <bitfield name="PRPSC" mask="0x20" text="Power Reduction PSC" icon=""/>
 506             <bitfield name="PRTIM1" mask="0x10" text="Power Reduction Timer/Counter1" icon=""/>
 507             <bitfield name="PRTIM0" mask="0x08" text="Power Reduction Timer/Counter0" icon=""/>
 508             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 509             <bitfield name="PRLIN" mask="0x02" text="Power Reduction LIN UART" icon=""/>
 510             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 511           </reg>
 512         </registers>
 513     </module>
 514     <module class="PORTE">
 515       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 516           <reg size="1" name="PORTE" offset="0x2E" text="Port E Data Register" icon="io_port.bmp" mask="0x07"/>
 517           <reg size="1" name="DDRE" offset="0x2D" text="Port E Data Direction Register" icon="io_flag.bmp" mask="0x07"/>
 518           <reg size="1" name="PINE" offset="0x2C" text="Port E Input Pins" icon="io_port.bmp" mask="0x07"/>
 519         </registers>
 520     </module>
 521     <module class="TIMER_COUNTER_0">
 522       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 523           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 524             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 525             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 526             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 527           </reg>
 528           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 529             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 530             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 531             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 532           </reg>
 533           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 534             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 535             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 536             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 537           </reg>
 538           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 539             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 540             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 541             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 542             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 543           </reg>
 544           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 545           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 546           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 547           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 548             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 549             <bitfield name="ICPSEL1" mask="0x40" text="Timer1 Input Capture Selection Bit" icon=""/>
 550             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 551           </reg>
 552         </registers>
 553     </module>
 554     <module class="TIMER_COUNTER_1">
 555       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 556           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 557             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 558             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 559             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 560             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 561           </reg>
 562           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 563             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 564             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 565             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 566             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 567           </reg>
 568           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 569             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 570             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 571             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 572           </reg>
 573           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 574             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 575             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 576             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 577             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 578           </reg>
 579           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter1 Control Register C" icon="io_flag.bmp">
 580             <bitfield name="FOC1A" mask="0x80" text="" icon=""/>
 581             <bitfield name="FOC1B" mask="0x40" text="" icon=""/>
 582           </reg>
 583           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 584           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 585           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 586           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 587           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 588             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 589             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 590           </reg>
 591         </registers>
 592     </module>
 593     <module class="AD_CONVERTER">
 594       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 595           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 596             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 597             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 598             <bitfield name="MUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 599           </reg>
 600           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 601             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 602             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 603             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 604             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 605             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 606             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon=""/>
 607           </reg>
 608           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 609           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp" mask="0xEF"/>
 610           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp" mask="0xFF"/>
 611           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 0" icon="">
 612             <bitfield name="AMP2PD" mask="0x40" text="AMP2P Pin Digital input Disable" icon=""/>
 613             <bitfield name="ACMP0D" mask="0x20" text="ACMP0 Pin Digital input Disable" icon=""/>
 614             <bitfield name="AMP0PD" mask="0x10" text="AMP0P Pin Digital input Disable" icon=""/>
 615             <bitfield name="AMP0ND" mask="0x08" text="AMP0N Pin Digital input Disable" icon=""/>
 616             <bitfield name="ADC10D" mask="0x04" text="ADC10 Pin Digital input Disable" icon=""/>
 617             <bitfield name="ADC9D" mask="0x02" text="ADC9 Pin Digital input Disable" icon=""/>
 618             <bitfield name="ADC8D" mask="0x01" text="ADC8 Pin Digital input Disable" icon=""/>
 619           </reg>
 620           <reg size="1" name="AMP0CSR" offset="0x75" text="" icon="io_analo.bmp">
 621             <bitfield name="AMP0EN" mask="0x80" text="" icon=""/>
 622             <bitfield name="AMP0IS" mask="0x40" text="" icon=""/>
 623             <bitfield name="AMP0G" mask="0x30" text="" icon=""/>
 624             <bitfield name="AMPCMP0" mask="0x08" text="Amplifier 0 - Comparator 0 Connection" icon=""/>
 625             <bitfield name="AMP0TS" mask="0x07" text="" icon=""/>
 626           </reg>
 627           <reg size="1" name="AMP1CSR" offset="0x76" text="" icon="io_analo.bmp">
 628             <bitfield name="AMP1EN" mask="0x80" text="" icon=""/>
 629             <bitfield name="AMP1IS" mask="0x40" text="" icon=""/>
 630             <bitfield name="AMP1G" mask="0x30" text="" icon=""/>
 631             <bitfield name="AMPCMP1" mask="0x08" text="Amplifier 1 - Comparator 1 Connection" icon=""/>
 632             <bitfield name="AMP1TS" mask="0x07" text="" icon=""/>
 633           </reg>
 634           <reg size="1" name="AMP2CSR" offset="0x77" text="" icon="io_analo.bmp">
 635             <bitfield name="AMP2EN" mask="0x80" text="" icon=""/>
 636             <bitfield name="AMP2IS" mask="0x40" text="" icon=""/>
 637             <bitfield name="AMP2G" mask="0x30" text="" icon=""/>
 638             <bitfield name="AMPCMP2" mask="0x08" text="Amplifier 2 - Comparator 2 Connection" icon=""/>
 639             <bitfield name="AMP2TS" mask="0x07" text="" icon=""/>
 640           </reg>
 641         </registers>
 642     </module>
 643     <module class="LINUART">
 644       <registers name="LINUART" memspace="DATAMEM" text="" icon="io_com.bmp">
 645           <reg size="1" name="LINCR" offset="0xC8" text="LIN Control Register" icon="io_analo.bmp">
 646             <bitfield name="LSWRES" mask="0x80" text="Software Reset" icon=""/>
 647             <bitfield name="LIN13" mask="0x40" text="LIN Standard" icon=""/>
 648             <bitfield name="LCONF" mask="0x30" text="LIN Configuration bits" icon=""/>
 649             <bitfield name="LENA" mask="0x08" text="LIN or UART Enable" icon=""/>
 650             <bitfield name="LCMD" mask="0x07" text="LIN Command and Mode bits" icon=""/>
 651           </reg>
 652           <reg size="1" name="LINSIR" offset="0xC9" text="LIN Status and Interrupt Register" icon="io_flag.bmp">
 653             <bitfield name="LIDST" mask="0xE0" text="Identifier Status bits" icon=""/>
 654             <bitfield name="LBUSY" mask="0x10" text="Busy Signal" icon=""/>
 655             <bitfield name="LERR" mask="0x08" text="Error Interrupt" icon=""/>
 656             <bitfield name="LIDOK" mask="0x04" text="Identifier Interrupt" icon=""/>
 657             <bitfield name="LTXOK" mask="0x02" text="Transmit Performed Interrupt" icon=""/>
 658             <bitfield name="LRXOK" mask="0x01" text="Receive Performed Interrupt" icon=""/>
 659           </reg>
 660           <reg size="1" name="LINENIR" offset="0xCA" text="LIN Enable Interrupt Register" icon="io_analo.bmp">
 661             <bitfield name="LENERR" mask="0x08" text="Enable Error Interrupt" icon=""/>
 662             <bitfield name="LENIDOK" mask="0x04" text="Enable Identifier Interrupt" icon=""/>
 663             <bitfield name="LENTXOK" mask="0x02" text="Enable Transmit Performed Interrupt" icon=""/>
 664             <bitfield name="LENRXOK" mask="0x01" text="Enable Receive Performed Interrupt" icon=""/>
 665           </reg>
 666           <reg size="1" name="LINERR" offset="0xCB" text="LIN Error Register" icon="io_flag.bmp">
 667             <bitfield name="LABORT" mask="0x80" text="Abort Flag" icon=""/>
 668             <bitfield name="LTOERR" mask="0x40" text="Frame Time Out Error Flag" icon=""/>
 669             <bitfield name="LOVERR" mask="0x20" text="Overrun Error Flag" icon=""/>
 670             <bitfield name="LFERR" mask="0x10" text="Framing Error Flag" icon=""/>
 671             <bitfield name="LSERR" mask="0x08" text="Synchronization Error Flag" icon=""/>
 672             <bitfield name="LPERR" mask="0x04" text="Parity Error Flag" icon=""/>
 673             <bitfield name="LCERR" mask="0x02" text="Checksum Error Flag" icon=""/>
 674             <bitfield name="LBERR" mask="0x01" text="Bit Error Flag" icon=""/>
 675           </reg>
 676           <reg size="1" name="LINBTR" offset="0xCC" text="LIN Bit Timing Register" icon="io_flag.bmp">
 677             <bitfield name="LDISR" mask="0x80" text="Disable Bit Timing Resynchronization" icon=""/>
 678             <bitfield name="LBT" mask="0x3F" text="LIN Bit Timing bits" icon=""/>
 679           </reg>
 680           <reg size="1" name="LINBRRL" offset="0xCD" text="LIN Baud Rate Low Register" icon="io_timer.bmp">
 681             <bitfield name="LDIV" mask="0xFF" text="" icon=""/>
 682           </reg>
 683           <reg size="1" name="LINBRRH" offset="0xCE" text="LIN Baud Rate High Register" icon="io_timer.bmp">
 684             <bitfield name="LDIV" mask="0x0F" text="" icon="" lsb="8"/>
 685           </reg>
 686           <reg size="1" name="LINDLR" offset="0xCF" text="LIN Data Length Register" icon="io_com.bmp">
 687             <bitfield name="LTXDL" mask="0xF0" text="LIN Transmit Data Length bits" icon=""/>
 688             <bitfield name="LRXDL" mask="0x0F" text="LIN Receive Data Length bits" icon=""/>
 689           </reg>
 690           <reg size="1" name="LINIDR" offset="0xD0" text="LIN Identifier Register" icon="io_com.bmp">
 691             <bitfield name="LP" mask="0xC0" text="Parity bits" icon=""/>
 692             <bitfield name="LID" mask="0x3F" text="Identifier bit 5 or Data Length bits" icon=""/>
 693           </reg>
 694           <reg size="1" name="LINSEL" offset="0xD1" text="LIN Data Buffer Selection Register" icon="io_com.bmp">
 695             <bitfield name="LAINC" mask="0x08" text="Auto Increment of Data Buffer Index (Active Low)" icon=""/>
 696             <bitfield name="LINDX" mask="0x07" text="FIFO LIN Data Buffer Index bits" icon=""/>
 697           </reg>
 698           <reg size="1" name="LINDAT" offset="0xD2" text="LIN Data Register" icon="io_com.bmp">
 699             <bitfield name="LDATA" mask="0xFF" text="" icon=""/>
 700           </reg>
 701         </registers>
 702     </module>
 703     <module class="SPI">
 704       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 705           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 706             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 707             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 708             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 709             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 710             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 711             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 712             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 713           </reg>
 714           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 715             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 716             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 717             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 718           </reg>
 719           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 720         </registers>
 721     </module>
 722     <module class="WATCHDOG">
 723       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 724           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 725             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 726             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 727             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 728             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 729             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 730           </reg>
 731         </registers>
 732     </module>
 733     <module class="EXTERNAL_INTERRUPT">
 734       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 735           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 736             <bitfield name="ISC3" mask="0xC0" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 737             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 738             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 739             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 740           </reg>
 741           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 742             <bitfield name="INT" mask="0x0F" text="External Interrupt Request 3 Enable" icon=""/>
 743           </reg>
 744           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 745             <bitfield name="INTF" mask="0x0F" text="External Interrupt Flags" icon=""/>
 746           </reg>
 747         </registers>
 748     </module>
 749     <module class="EEPROM">
 750       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 751           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x03FF"/>
 752           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 753           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 754             <bitfield name="EEPM" mask="0x30" text="" icon="" enum="EEP_MODE"/>
 755             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 756             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 757             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 758             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 759           </reg>
 760         </registers>
 761     </module>
 762   </hardware>
 763 </device>