devices/atmega163

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="18">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt 1</interrupt>
   8     <interrupt vector="4" address="$006" name="TIMER2_COMP">Timer/Counter2 Compare Match</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2_OVF">Timer/Counter2 Overflow</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="SPI,STC">SPI Serial Transfer Complete</interrupt>
  16     <interrupt vector="12" address="$016" name="UART,RX">UART, RX Complete</interrupt>
  17     <interrupt vector="13" address="$018" name="UART,UDRE">UART Data Register Empty</interrupt>
  18     <interrupt vector="14" address="$01A" name="UART,TX">UART, TX Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="ADC">ADC Conversion Complete</interrupt>
  20     <interrupt vector="16" address="$01E" name="EE_RDY">EEPROM Ready</interrupt>
  21     <interrupt vector="17" address="$020" name="ANA_COMP">Analog Comparator</interrupt>
  22     <interrupt vector="18" address="$022" name="TWI">2-Wire Serial Interface</interrupt>
  23   </interrupts>
  24   <memory>
  25     <flash size="16384"/>
  26     <iospace start="$20" stop="$5F"/>
  27     <sram size="1024"/>
  28     <eram size="0"/>
  29   </memory>
  30   <ioregisters>
  31     <ioreg name="TWBR" address="$00"/>
  32     <ioreg name="TWSR" address="$01"/>
  33     <ioreg name="TWAR" address="$02"/>
  34     <ioreg name="TWDR" address="$03"/>
  35     <ioreg name="ADCL" address="$04"/>
  36     <ioreg name="ADCH" address="$05"/>
  37     <ioreg name="ADCSR" address="$06"/>
  38     <ioreg name="ADMUX" address="$07"/>
  39     <ioreg name="ACSR" address="$08"/>
  40     <ioreg name="UBRR" address="$09"/>
  41     <ioreg name="UCSRB" address="$0A"/>
  42     <ioreg name="UCSRA" address="$0B"/>
  43     <ioreg name="UDR" address="$0C"/>
  44     <ioreg name="SPCR" address="$0D"/>
  45     <ioreg name="SPSR" address="$0E"/>
  46     <ioreg name="SPDR" address="$0F"/>
  47     <ioreg name="PIND" address="$10"/>
  48     <ioreg name="DDRD" address="$11"/>
  49     <ioreg name="PORTD" address="$12"/>
  50     <ioreg name="PINC" address="$13"/>
  51     <ioreg name="DDRC" address="$14"/>
  52     <ioreg name="PORTC" address="$15"/>
  53     <ioreg name="PINB" address="$16"/>
  54     <ioreg name="DDRB" address="$17"/>
  55     <ioreg name="PORTB" address="$18"/>
  56     <ioreg name="PINA" address="$19"/>
  57     <ioreg name="DDRA" address="$1A"/>
  58     <ioreg name="PORTA" address="$1B"/>
  59     <ioreg name="EECR" address="$1C"/>
  60     <ioreg name="EEDR" address="$1D"/>
  61     <ioreg name="EEARL" address="$1E"/>
  62     <ioreg name="EEARH" address="$1F"/>
  63     <ioreg name="UBRRHI" address="$20"/>
  64     <ioreg name="WDTCR" address="$21"/>
  65     <ioreg name="ASSR" address="$22"/>
  66     <ioreg name="OCR2" address="$23"/>
  67     <ioreg name="TCNT2" address="$24"/>
  68     <ioreg name="TCCR2" address="$25"/>
  69     <ioreg name="ICR1L" address="$26"/>
  70     <ioreg name="ICR1H" address="$27"/>
  71     <ioreg name="OCR1BL" address="$28"/>
  72     <ioreg name="OCR1BH" address="$29"/>
  73     <ioreg name="OCR1AL" address="$2A"/>
  74     <ioreg name="OCR1AH" address="$2B"/>
  75     <ioreg name="TCNT1L" address="$2C"/>
  76     <ioreg name="TCNT1H" address="$2D"/>
  77     <ioreg name="TCCR1B" address="$2E"/>
  78     <ioreg name="TCCR1A" address="$2F"/>
  79     <ioreg name="SFIOR" address="$30"/>
  80     <ioreg name="OSCCAL" address="$31"/>
  81     <ioreg name="TCNT0" address="$32"/>
  82     <ioreg name="TCCR0" address="$33"/>
  83     <ioreg name="MCUSR" address="$34"/>
  84     <ioreg name="MCUCR" address="$35"/>
  85     <ioreg name="TWCR" address="$36"/>
  86     <ioreg name="SPMCR" address="$37"/>
  87     <ioreg name="TIFR" address="$38"/>
  88     <ioreg name="TIMSK" address="$39"/>
  89     <ioreg name="GIFR" address="$3A"/>
  90     <ioreg name="GIMSK" address="$3B"/>
  91     <ioreg name="SPL" address="$3D"/>
  92     <ioreg name="SPH" address="$3E"/>
  93     <ioreg name="SREG" address="$3F"/>
  94   </ioregisters>
  95   <packages>
  96     <package name="TQFP" pins="44">
  97       <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
  98       <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
  99       <pin id="3" name="[PB7_SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
 100       <pin id="4" name="['RESET]"/>
 101       <pin id="5" name="[VCC]"/>
 102       <pin id="6" name="[GND]"/>
 103       <pin id="7" name="[XTAL2]"/>
 104       <pin id="8" name="[XTAL1]"/>
 105       <pin id="9" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
 106       <pin id="10" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
 107       <pin id="11" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 108       <pin id="12" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 109       <pin id="13" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
 110       <pin id="14" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 111       <pin id="15" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
 112       <pin id="16" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
 113       <pin id="17" name="[VCC]"/>
 114       <pin id="18" name="[GND]"/>
 115       <pin id="19" name="[PC0:SCL]">SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal.</pin>
 116       <pin id="20" name="[PC1:SDA]">SDA, 2-wire Serial Bus Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is dis-connected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal, and the pin is driven by an open collector driver with slew rate limitation.</pin>
 117       <pin id="21" name="[PC2]"/>
 118       <pin id="22" name="[PC3]"/>
 119       <pin id="23" name="[PC4]"/>
 120       <pin id="24" name="[PC5]"/>
 121       <pin id="25" name="[PC6:TOSC1]"/>
 122       <pin id="26" name="[PC7:TOSC2]"/>
 123       <pin id="27" name="[AVCC]"/>
 124       <pin id="28" name="[AGND]"/>
 125       <pin id="29" name="[AREF]"/>
 126       <pin id="30" name="[PA7:ADC7]"/>
 127       <pin id="31" name="[PA6:ADC6]"/>
 128       <pin id="32" name="[PA5:ADc5]"/>
 129       <pin id="33" name="[PA4:ADC4]"/>
 130       <pin id="34" name="[PA3:ADC3]"/>
 131       <pin id="35" name="[PA2:ADC2]"/>
 132       <pin id="36" name="[PA1:ADC1]"/>
 133       <pin id="37" name="[PA0:ADC0]"/>
 134       <pin id="38" name="[VCC]"/>
 135       <pin id="39" name="[GND]"/>
 136       <pin id="40" name="[PB0:T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
 137       <pin id="41" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
 138       <pin id="42" name="[PB2:AIN0]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
 139       <pin id="43" name="[PB3:AIN1]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
 140       <pin id="44" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
 141     </package>
 142   </packages>
 143   <hardware>
 144 <!--Everything after this needs editing!!!-->
 145     <module class="FUSE">
 146       <registers name="FUSE" memspace="FUSE">
 147           <reg size="1" name="HIGH" offset="0x01">
 148             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 149             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
 150           </reg>
 151           <reg size="1" name="LOW" offset="0x00">
 152             <bitfield name="BODLEVEL" mask="0x80" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 153             <bitfield name="BODEN" mask="0x40" text="Brown-out detection enabled" icon=""/>
 154             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 155             <bitfield name="CKSEL" mask="0x0F" text="Select Clock Source" icon="" enum="ENUM_CKSEL"/>
 156           </reg>
 157         </registers>
 158     </module>
 159     <module class="LOCKBIT">
 160       <registers name="LOCKBIT" memspace="LOCKBIT">
 161           <reg size="1" name="LOCKBIT" offset="0x00">
 162             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 163             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 164             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 165           </reg>
 166         </registers>
 167     </module>
 168     <module class="TIMER_COUNTER_0">
 169       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 170           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 171             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 172           </reg>
 173           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 174             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 175           </reg>
 176           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 177             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon=""/>
 178             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 179             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon="" enum="CLK_SEL_3BIT_EXT"/>
 180           </reg>
 181           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 182         </registers>
 183     </module>
 184     <module class="CPU">
 185       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 186           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 187             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 188             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 189             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 190             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 191             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 192             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 193             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 194             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 195           </reg>
 196           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x07FF"/>
 197           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 198           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control register" icon="io_flag.bmp">
 199             <bitfield name="SE" mask="0x40" text="Sleep enable" icon=""/>
 200             <bitfield name="SM" mask="0x30" text="Sleep Mode Select Bits" icon="" enum="CPU_SLEEP_MODE"/>
 201             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 202             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 203           </reg>
 204           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 205             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 206             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 207             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 208             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 209           </reg>
 210           <reg size="1" name="SFIOR" offset="0x50" text="MCU Status Register" icon="io_cpu.bmp">
 211             <bitfield name="ACME" mask="0x08" text="Analog Comparator multiplexer Enable" icon=""/>
 212             <bitfield name="PUD" mask="0x04" text="Pull-up Disable" icon=""/>
 213             <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
 214             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 215           </reg>
 216         </registers>
 217     </module>
 218     <module class="TIMER_COUNTER_1">
 219       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 220           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 221             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 222             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 223             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 224             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 225           </reg>
 226           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 227             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 228             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 229             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 230             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 231           </reg>
 232           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 233             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 234             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 235             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
 236             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
 237             <bitfield name="PWM1" mask="0x03" text="Pulse Width Modulator Select Bits" icon="" enum="PULSE_WIDTH_MODU"/>
 238           </reg>
 239           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 240             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 241             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 242             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 243             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 244           </reg>
 245           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 246           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 247           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 248           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 249         </registers>
 250     </module>
 251     <module class="TIMER_COUNTER_2">
 252       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 253           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 254             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 255             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 256           </reg>
 257           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 258             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 259             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 260           </reg>
 261           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 262             <bitfield name="FOC2" mask="0x80" text="Force Output Compare" icon=""/>
 263             <bitfield name="WGM20" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 264             <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon=""/>
 265             <bitfield name="WGM21" mask="0x08" text="Clear Timer/Counter2 on Compare Match" icon=""/>
 266             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 267           </reg>
 268           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 269           <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 270           <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
 271             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer/counter2" icon=""/>
 272             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 273             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 274             <bitfield name="TCR2UB" mask="0x01" text="Timer/counter Control Register2 Update Busy" icon=""/>
 275           </reg>
 276         </registers>
 277     </module>
 278     <module class="WATCHDOG">
 279       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 280           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 281             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 282             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 283             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 284           </reg>
 285         </registers>
 286     </module>
 287     <module class="EEPROM">
 288       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 289           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register  Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
 290           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 291           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 292             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 293             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 294             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 295             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 296           </reg>
 297         </registers>
 298     </module>
 299     <module class="SPI">
 300       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 301           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 302           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 303             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 304             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 305             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 306           </reg>
 307           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 308             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 309             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 310             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 311             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 312             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 313             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 314             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 315           </reg>
 316         </registers>
 317     </module>
 318     <module class="UART">
 319       <registers name="UART" memspace="DATAMEM" text="" icon="io_com.bmp">
 320           <reg size="1" name="UDR" offset="0x2C" text="UART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 321           <reg size="1" name="UCSRA" offset="0x2B" text="UART Control and Status register A" icon="io_flag.bmp">
 322             <bitfield name="RXC" mask="0x80" text="UART Receive Complete" icon=""/>
 323             <bitfield name="TXC" mask="0x40" text="UART Transmitt Complete" icon=""/>
 324             <bitfield name="UDRE" mask="0x20" text="UART Data Register Empty" icon=""/>
 325             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 326             <bitfield name="OR" mask="0x08" text="Overrun" icon=""/>
 327             <bitfield name="U2X" mask="0x02" text="Double the UART Transmission Speed" icon=""/>
 328             <bitfield name="MPCM" mask="0x01" text="Multi Processor Communication Mode" icon=""/>
 329           </reg>
 330           <reg size="1" name="UCSRB" offset="0x2A" text="UART Control an Status register B" icon="io_flag.bmp">
 331             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 332             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 333             <bitfield name="UDRIE" mask="0x20" text="UART Data Register Empty Interrupt Enable" icon=""/>
 334             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 335             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 336             <bitfield name="CHR9" mask="0x04" text="9-bit Characters" icon=""/>
 337             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 338             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 339           </reg>
 340           <reg size="1" name="UBRRHI" offset="0x40" text="UART Baud Rate Register High Byte" icon="io_com.bmp" mask="0x0F"/>
 341           <reg size="1" name="UBRR" offset="0x29" text="UART Baud Rate Register" icon="io_com.bmp" mask="0xFF"/>
 342         </registers>
 343     </module>
 344     <module class="TWI">
 345       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 346           <reg size="1" name="TWBR" offset="0x20" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 347           <reg size="1" name="TWCR" offset="0x56" text="TWI Control Register" icon="io_flag.bmp">
 348             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 349             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 350             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 351             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 352             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 353             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 354             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 355           </reg>
 356           <reg size="1" name="TWSR" offset="0x21" text="TWI Status Register" icon="io_flag.bmp">
 357             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 358           </reg>
 359           <reg size="1" name="TWDR" offset="0x23" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 360           <reg size="1" name="TWAR" offset="0x22" text="TWI (Slave) Address register" icon="io_com.bmp" mask="0xFF"/>
 361         </registers>
 362     </module>
 363     <module class="PORTA">
 364       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 365           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 366           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 367           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 368         </registers>
 369     </module>
 370     <module class="PORTB">
 371       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 372           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 373           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 374           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 375         </registers>
 376     </module>
 377     <module class="PORTC">
 378       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 379           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 380           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 381           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 382         </registers>
 383     </module>
 384     <module class="PORTD">
 385       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 386           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 387           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 388           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 389         </registers>
 390     </module>
 391     <module class="ANALOG_COMPARATOR">
 392       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 393           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_flag.bmp">
 394             <bitfield name="ACME" mask="0x08" text="Analog Comparator Multiplexer Enable" icon=""/>
 395           </reg>
 396           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 397             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 398             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 399             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 400             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 401             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 402             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 403             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 404           </reg>
 405         </registers>
 406     </module>
 407     <module class="AD_CONVERTER">
 408       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 409           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 410             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF"/>
 411             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 412             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 413           </reg>
 414           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 415             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 416             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 417             <bitfield name="ADFR" mask="0x20" text="ADC  Free Running Select" icon=""/>
 418             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 419             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 420             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 421           </reg>
 422           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 423         </registers>
 424     </module>
 425     <module class="EXTERNAL_INTERRUPT">
 426       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 427           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_flag.bmp">
 428             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 429           </reg>
 430           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag register" icon="io_flag.bmp">
 431             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 432           </reg>
 433         </registers>
 434     </module>
 435     <module class="BOOT_LOAD">
 436       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 437           <reg size="1" name="SPMCR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 438             <bitfield name="ASB" mask="0x40" text="Application section busy" icon=""/>
 439             <bitfield name="ASRE" mask="0x10" text="Application section read enable" icon=""/>
 440             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 441             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 442             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 443             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 444           </reg>
 445         </registers>
 446     </module>
 447   </hardware>
 448 </device>