devices/at90s2343

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="3">
   5     <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
   7     <interrupt vector="3" address="$002" name="TIMER0_OVF0">Timer/Counter0 Overflow</interrupt>
   8   </interrupts>
   9   <memory>
  10     <flash size="2048"/>
  11     <iospace start="$20" stop="$5F"/>
  12     <sram size="128"/>
  13     <eram size="0"/>
  14   </memory>
  15   <ioregisters>
  16     <ioreg name="PINB" address="$16"/>
  17     <ioreg name="DDRB" address="$17"/>
  18     <ioreg name="PORTB" address="$18"/>
  19     <ioreg name="EECR" address="$1C"/>
  20     <ioreg name="EEDR" address="$1D"/>
  21     <ioreg name="EEAR" address="$1E"/>
  22     <ioreg name="WDTCR" address="$21"/>
  23     <ioreg name="TCNT0" address="$32"/>
  24     <ioreg name="TCCR0" address="$33"/>
  25     <ioreg name="MCUSR" address="$34"/>
  26     <ioreg name="MCUCR" address="$35"/>
  27     <ioreg name="TIFR" address="$38"/>
  28     <ioreg name="TIMSK" address="$39"/>
  29     <ioreg name="GIFR" address="$3A"/>
  30     <ioreg name="GIMSK" address="$3B"/>
  31     <ioreg name="SPL" address="$3D"/>
  32     <ioreg name="SREG" address="$3F"/>
  33   </ioregisters>
  34   <packages/>
  35   <hardware>
  36 <!--Everything after this needs editing!!!-->
  37     <module class="FUSE">
  38       <registers name="FUSE" memspace="FUSE">
  39           <reg size="1" name="LOW" offset="0x00">
  40             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
  41             <bitfield name="RCEN" mask="0x01" text="Clock Source" icon="" enum="ENUM1"/>
  42           </reg>
  43         </registers>
  44     </module>
  45     <module class="LOCKBIT">
  46       <registers name="LOCKBIT" memspace="LOCKBIT">
  47           <reg size="1" name="LOCKBIT" offset="0x00">
  48             <bitfield name="LB" mask="0x06" text="Memory Lock" icon="" enum="ENUM_LB"/>
  49           </reg>
  50         </registers>
  51     </module>
  52     <module class="CPU">
  53       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.com">
  54           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
  55             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
  56             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
  57             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
  58             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
  59             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
  60             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
  61             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
  62             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
  63           </reg>
  64           <reg size="1" name="SPL" offset="0x5D" text="Stack Pointer Low" icon="" mask="0xFF"/>
  65           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_cpu.bmp">
  66             <bitfield name="SE" mask="0x20" text="Sleep Enable" icon=""/>
  67             <bitfield name="SM" mask="0x10" text="Sleep Mode" icon=""/>
  68             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
  69           </reg>
  70           <reg size="1" name="MCUSR" offset="0x54" text="" icon="io_cpu.bmp">
  71             <bitfield name="EXTRF" mask="0x02" text="Externl Reset Flag" icon=""/>
  72             <bitfield name="PORF" mask="0x01" text="Power On Reset Flag" icon=""/>
  73           </reg>
  74           <reg size="1" name="GIMSK" offset="0x5B" text="General Interrupt Mask Register" icon="io_cpu.bmp">
  75             <bitfield name="INT0" mask="0x40" text="External Interrupt Request 0 Enable" icon=""/>
  76           </reg>
  77           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_cpu.bmp">
  78             <bitfield name="INTF0" mask="0x40" text="External Interrupt Flag 0" icon=""/>
  79           </reg>
  80         </registers>
  81     </module>
  82     <module class="EEPROM">
  83       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
  84           <reg size="1" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x7F"/>
  85           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
  86           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
  87             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
  88             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
  89             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
  90           </reg>
  91         </registers>
  92     </module>
  93     <module class="WATCHDOG">
  94       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
  95           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
  96             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
  97             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
  98             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
  99           </reg>
 100         </registers>
 101     </module>
 102     <module class="PORTB">
 103       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 104           <reg size="1" name="PORTB" offset="0x38" text="Data Register, Port B" icon="io_port.bmp" mask="0x1F"/>
 105           <reg size="1" name="DDRB" offset="0x37" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x1F"/>
 106           <reg size="1" name="PINB" offset="0x36" text="Input Pins, Port B" icon="io_port.bmp" mask="0x1F"/>
 107         </registers>
 108     </module>
 109     <module class="TIMER_COUNTER_0">
 110       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 111           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 112             <bitfield name="TOIE0" mask="0x02" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 113           </reg>
 114           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 115             <bitfield name="TOV0" mask="0x02" text="Timer/Counter0 Overflow Flag" icon=""/>
 116           </reg>
 117           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 118             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon="" enum="CLK_SEL_3BIT_EXT"/>
 119             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 120             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
 121           </reg>
 122           <reg size="1" name="TCNT0" offset="0x52" text="Timer Counter 0" icon="io_timer.bmp" mask="0xFF"/>
 123         </registers>
 124     </module>
 125   </hardware>
 126 </device>