.gitignore ignores tests and eclipse
[avr-sim.git] / devices / atmega8535
blob9db7fb626e5f7b2a93afcc499c2e7b3d76f34cba
1 <?xml version="1.0"?>
2 <!DOCTYPE device SYSTEM "device.dtd">
3 <device>
4 <interrupts num="21">
5 <interrupt vector="1" address="$000" name="RESET">External Reset, Power-on Reset and Watchdog Reset</interrupt>
6 <interrupt vector="2" address="$001" name="INT0">External Interrupt 0</interrupt>
7 <interrupt vector="3" address="$002" name="INT1">External Interrupt 1</interrupt>
8 <interrupt vector="4" address="$003" name="TIMER2_COMP">Timer/Counter2 Compare Match</interrupt>
9 <interrupt vector="5" address="$004" name="TIMER2_OVF">Timer/Counter2 Overflow</interrupt>
10 <interrupt vector="6" address="$005" name="TIMER1_CAPT">Timer/Counter1 Capture Event</interrupt>
11 <interrupt vector="7" address="$006" name="TIMER1_COMPA">Timer/Counter1 Compare Match A</interrupt>
12 <interrupt vector="8" address="$007" name="TIMER1_COMPB">Timer/Counter1 Compare Match B</interrupt>
13 <interrupt vector="9" address="$008" name="TIMER1_OVF">Timer/Counter1 Overflow</interrupt>
14 <interrupt vector="10" address="$009" name="TIMER0_OVF">Timer/Counter0 Overflow</interrupt>
15 <interrupt vector="11" address="$00A" name="SPI,STC">SPI Serial Transfer Complete</interrupt>
16 <interrupt vector="12" address="$00B" name="USART,RX">USART, RX Complete</interrupt>
17 <interrupt vector="13" address="$00C" name="USART,UDRE">USART Data Register Empty</interrupt>
18 <interrupt vector="14" address="$00D" name="USART,TX">USART, TX Complete</interrupt>
19 <interrupt vector="15" address="$00E" name="ADC">ADC Conversion Complete</interrupt>
20 <interrupt vector="16" address="$00F" name="EE_RDY">EEPROM Ready</interrupt>
21 <interrupt vector="17" address="$010" name="ANA_COMP">Analog Comparator</interrupt>
22 <interrupt vector="18" address="$011" name="TWI">Two-wire Serial Interface</interrupt>
23 <interrupt vector="19" address="$012" name="INT2">External Interrupt Request 2</interrupt>
24 <interrupt vector="20" address="$013" name="TIMER0_COMP">TimerCounter0 Compare Match</interrupt>
25 <interrupt vector="21" address="$014" name="SPM_RDY">Store Program Memory Read</interrupt>
26 </interrupts>
27 <memory>
28 <flash size="8192"/>
29 <iospace start="$20" stop="$5F"/>
30 <sram size="512"/>
31 <eram size="0"/>
32 </memory>
33 <ioregisters>
34 <ioreg name="TWBR" address="$00"/>
35 <ioreg name="TWSR" address="$01"/>
36 <ioreg name="TWAR" address="$02"/>
37 <ioreg name="TWDR" address="$03"/>
38 <ioreg name="ADCL" address="$04"/>
39 <ioreg name="ADCH" address="$05"/>
40 <ioreg name="ADCSRA" address="$06"/>
41 <ioreg name="ADMUX" address="$07"/>
42 <ioreg name="ACSR" address="$08"/>
43 <ioreg name="UBRRL" address="$09"/>
44 <ioreg name="UCSRB" address="$0A"/>
45 <ioreg name="UCSRA" address="$0B"/>
46 <ioreg name="UDR" address="$0C"/>
47 <ioreg name="SPCR" address="$0D"/>
48 <ioreg name="SPSR" address="$0E"/>
49 <ioreg name="SPDR" address="$0F"/>
50 <ioreg name="PIND" address="$10"/>
51 <ioreg name="DDRD" address="$11"/>
52 <ioreg name="PORTD" address="$12"/>
53 <ioreg name="PINC" address="$13"/>
54 <ioreg name="DDRC" address="$14"/>
55 <ioreg name="PORTC" address="$15"/>
56 <ioreg name="PINB" address="$16"/>
57 <ioreg name="DDRB" address="$17"/>
58 <ioreg name="PORTB" address="$18"/>
59 <ioreg name="PINA" address="$19"/>
60 <ioreg name="DDRA" address="$1A"/>
61 <ioreg name="PORTA" address="$1B"/>
62 <ioreg name="EECR" address="$1C"/>
63 <ioreg name="EEDR" address="$1D"/>
64 <ioreg name="EEARL" address="$1E"/>
65 <ioreg name="EEARH" address="$1F"/>
66 <ioreg name="UBRRH" address="$20"/>
67 <ioreg name="UCSRC" address="$20"/>
68 <ioreg name="WDTCR" address="$21"/>
69 <ioreg name="ASSR" address="$22"/>
70 <ioreg name="OCR2" address="$23"/>
71 <ioreg name="TCNT2" address="$24"/>
72 <ioreg name="TCCR2" address="$25"/>
73 <ioreg name="ICR1L" address="$26"/>
74 <ioreg name="ICR1H" address="$27"/>
75 <ioreg name="OCR1BL" address="$28"/>
76 <ioreg name="OCR1BH" address="$29"/>
77 <ioreg name="OCR1AL" address="$2A"/>
78 <ioreg name="OCR1AH" address="$2B"/>
79 <ioreg name="TCNT1L" address="$2C"/>
80 <ioreg name="TCNT1H" address="$2D"/>
81 <ioreg name="TCCR1B" address="$2E"/>
82 <ioreg name="TCCR1A" address="$2F"/>
83 <ioreg name="SFIOR" address="$30"/>
84 <ioreg name="OSCCAL" address="$31"/>
85 <ioreg name="TCNT0" address="$32"/>
86 <ioreg name="TCCR0" address="$33"/>
87 <ioreg name="MCUCSR" address="$34"/>
88 <ioreg name="MCUCR" address="$35"/>
89 <ioreg name="TWCR" address="$36"/>
90 <ioreg name="SPMCR" address="$37"/>
91 <ioreg name="TIFR" address="$38"/>
92 <ioreg name="TIMSK" address="$39"/>
93 <ioreg name="GIFR" address="$3A"/>
94 <ioreg name="GICR" address="$3B"/>
95 <ioreg name="OCR0" address="$3C"/>
96 <ioreg name="SPL" address="$3D"/>
97 <ioreg name="SPH" address="$3E"/>
98 <ioreg name="SREG" address="$3F"/>
99 </ioregisters>
100 <packages>
101 <package name="TQFP" pins="44">
102 <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
103 <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
104 <pin id="3" name="[PB7:SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
105 <pin id="4" name="['RESET]"/>
106 <pin id="5" name="[VCC]"/>
107 <pin id="6" name="[GND]"/>
108 <pin id="7" name="[XTAL2]"/>
109 <pin id="8" name="[XTAL1]"/>
110 <pin id="9" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
111 <pin id="10" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
112 <pin id="11" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
113 <pin id="12" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
114 <pin id="13" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
115 <pin id="14" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
116 <pin id="15" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
117 <pin id="16" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
118 <pin id="17" name="[VCC]"/>
119 <pin id="18" name="[GND]"/>
120 <pin id="19" name="[PC0:SCL]"/>
121 <pin id="20" name="[PC1:SDA]"/>
122 <pin id="21" name="[PC2]"/>
123 <pin id="22" name="[PC3]"/>
124 <pin id="23" name="[PC4]"/>
125 <pin id="24" name="[PC5]"/>
126 <pin id="25" name="[PC6:TOSC1]"/>
127 <pin id="26" name="[PC7:TOSC2]"/>
128 <pin id="27" name="[AVCC]"/>
129 <pin id="28" name="[AGND]"/>
130 <pin id="29" name="[AREF]"/>
131 <pin id="30" name="[PA7:ADC7]"/>
132 <pin id="31" name="[PA6:ADC6]"/>
133 <pin id="32" name="[PA5:ADc5]"/>
134 <pin id="33" name="[PA4:ADC4]"/>
135 <pin id="34" name="[PA3:ADC3]"/>
136 <pin id="35" name="[PA2:ADC2]"/>
137 <pin id="36" name="[PA1:ADC1]"/>
138 <pin id="37" name="[PA0:ADC0]"/>
139 <pin id="38" name="[VCC]"/>
140 <pin id="39" name="[GND]"/>
141 <pin id="40" name="[PB0:XCK:T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
142 <pin id="41" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
143 <pin id="42" name="[PB2:AIN0:INT2]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
144 <pin id="43" name="[PB3:AIN1:OC0]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
145 <pin id="44" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
146 </package>
147 <package name="PDIP" pins="40">
148 <pin id="1" name="[PB0:XCK:T0]">T0: Timer/Counter0 counter source. See the timer description for further details.</pin>
149 <pin id="2" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
150 <pin id="3" name="[PB2:AIN0:INT2]">AIN0: Analog Comparator Positive Input. When configured as an input (DDB2 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB2 is cleared [zero]), this pin also serves as the positive input of the on-chip Analog Comparator.</pin>
151 <pin id="4" name="[PB3:AIN1:OC0]">AIN1: Analog Comparator Negative Input. When configured as an input (DDB3 is cleared [zero]) and with the internal MOS pull-up resistor switched off (PB3 is cleared [zero]), this pin also serves as the negative input of the on-chip Analog Comparator.</pin>
152 <pin id="5" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
153 <pin id="6" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
154 <pin id="7" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
155 <pin id="8" name="[PB7:SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
156 <pin id="9" name="['RESET]"/>
157 <pin id="10" name="[VCC]"/>
158 <pin id="11" name="[GND]"/>
159 <pin id="12" name="[XTAL2]"/>
160 <pin id="13" name="[XTAL1]"/>
161 <pin id="14" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
162 <pin id="15" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
163 <pin id="16" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
164 <pin id="17" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
165 <pin id="18" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
166 <pin id="19" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
167 <pin id="20" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
168 <pin id="21" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
169 <pin id="22" name="[PC0:SCL]"/>
170 <pin id="23" name="[PC1:SDA]"/>
171 <pin id="24" name="[PC2]"/>
172 <pin id="25" name="[PC3]"/>
173 <pin id="26" name="[PC4]"/>
174 <pin id="27" name="[PC5]"/>
175 <pin id="28" name="[PC6:TOSC1]"/>
176 <pin id="29" name="[PC7:TOSC2]"/>
177 <pin id="30" name="[AVCC]"/>
178 <pin id="31" name="[GND]"/>
179 <pin id="32" name="[AREF]"/>
180 <pin id="33" name="[PA7:ADC7]"/>
181 <pin id="34" name="[PA6:ADC6]"/>
182 <pin id="35" name="[PA5:ADc5]"/>
183 <pin id="36" name="[PA4:ADC4]"/>
184 <pin id="37" name="[PA3:ADC3]"/>
185 <pin id="38" name="[PA2:ADC2]"/>
186 <pin id="39" name="[PA1:ADC1]"/>
187 <pin id="40" name="[PA0:ADC0]"/>
188 </package>
189 </packages>
190 <hardware>
191 <!--Everything after this needs editing!!!-->
192 <module class="FUSE">
193 <registers name="FUSE" memspace="FUSE">
194 <reg size="1" name="HIGH" offset="0x01">
195 <bitfield name="S8535C" mask="0x80" text="AT90S4434/8535 compatibility mode" icon=""/>
196 <bitfield name="WDTON" mask="0x40" text="Watch-dog Timer always on" icon=""/>
197 <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
198 <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
199 <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
200 <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled" icon=""/>
201 <bitfield name="CKOPT" mask="0x10" text="CKOPT fuse (operation dependent of CKSEL fuses)" icon=""/>
202 </reg>
203 <reg size="1" name="LOW" offset="0x00">
204 <bitfield name="BODLEVEL" mask="0x80" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
205 <bitfield name="BODEN" mask="0x40" text="Brown-out detection enabled" icon=""/>
206 <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
207 </reg>
208 </registers>
209 </module>
210 <module class="LOCKBIT">
211 <registers name="LOCKBIT" memspace="LOCKBIT">
212 <reg size="1" name="LOCKBIT" offset="0x00">
213 <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
214 <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
215 <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
216 </reg>
217 </registers>
218 </module>
219 <module class="AD_CONVERTER">
220 <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
221 <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
222 <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
223 <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
224 <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
225 </reg>
226 <reg size="1" name="ADCSRA" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
227 <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
228 <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
229 <bitfield name="ADATE" mask="0x20" text="When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset." icon=""/>
230 <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
231 <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
232 <bitfield name="ADPS" mask="0x07" text="ADC Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
233 </reg>
234 <reg size="2" name="ADC" offset="0x24" text="ADC Data Register Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
235 <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
236 <bitfield name="ADTS" mask="0xE0" text="ADC Auto Trigger Sources" icon=""/>
237 </reg>
238 </registers>
239 </module>
240 <module class="ANALOG_COMPARATOR">
241 <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
242 <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
243 <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
244 <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
245 <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
246 <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
247 <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
248 <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
249 <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
250 </reg>
251 </registers>
252 </module>
253 <module class="TWI">
254 <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
255 <reg size="1" name="TWBR" offset="0x20" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
256 <reg size="1" name="TWCR" offset="0x56" text="TWI Control Register" icon="io_flag.bmp">
257 <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
258 <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
259 <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
260 <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
261 <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
262 <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
263 <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
264 </reg>
265 <reg size="1" name="TWSR" offset="0x21" text="TWI Status Register" icon="io_flag.bmp">
266 <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
267 <bitfield name="TWPS" mask="0x03" text="TWI Prescaler" icon="" enum="COMM_TWI_PRESACLE"/>
268 </reg>
269 <reg size="1" name="TWDR" offset="0x23" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
270 <reg size="1" name="TWAR" offset="0x22" text="TWI (Slave) Address register" icon="io_com.bmp">
271 <bitfield name="TWA" mask="0xFE" text="TWI (Slave) Address register Bits" icon=""/>
272 <bitfield name="TWGCE" mask="0x01" text="TWI General Call Recognition Enable Bit" icon=""/>
273 </reg>
274 </registers>
275 </module>
276 <module class="USART">
277 <registers name="USART" memspace="DATAMEM" text="" icon="io_com.bmp">
278 <reg size="1" name="UDR" offset="0x2C" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
279 <reg size="1" name="UCSRA" offset="0x2B" text="USART Control and Status Register A" icon="io_flag.bmp">
280 <bitfield name="RXC" mask="0x80" text="USART Receive Complete" icon=""/>
281 <bitfield name="TXC" mask="0x40" text="USART Transmitt Complete" icon=""/>
282 <bitfield name="UDRE" mask="0x20" text="USART Data Register Empty" icon=""/>
283 <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
284 <bitfield name="DOR" mask="0x08" text="Data overRun" icon=""/>
285 <bitfield name="UPE" mask="0x04" text="Parity Error" icon=""/>
286 <bitfield name="U2X" mask="0x02" text="Double the USART transmission speed" icon=""/>
287 <bitfield name="MPCM" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
288 </reg>
289 <reg size="1" name="UCSRB" offset="0x2A" text="USART Control and Status Register B" icon="io_flag.bmp">
290 <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
291 <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
292 <bitfield name="UDRIE" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
293 <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
294 <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
295 <bitfield name="UCSZ2" mask="0x04" text="Character Size Bit 2" icon=""/>
296 <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
297 <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
298 </reg>
299 <reg size="1" name="UCSRC" offset="0x40" text="USART Control and Status Register C" icon="io_flag.bmp">
300 <bitfield name="URSEL" mask="0x80" text="Register Select" icon=""/>
301 <bitfield name="UMSEL" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
302 <bitfield name="UPM" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
303 <bitfield name="USBS" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
304 <bitfield name="UCSZ" mask="0x06" text="Character Size Bits" icon=""/>
305 <bitfield name="UCPOL" mask="0x01" text="Clock Polarity" icon=""/>
306 </reg>
307 <reg size="1" name="UBRRH" offset="0x40" text="USART Baud Rate Register High Byte" icon="io_com.bmp">
308 <bitfield name="URSEL" mask="0x80" text="Register Select" icon=""/>
309 <bitfield name="UBRR1" mask="0x0C" text="USART Baud Rate Register bit 11" icon=""/>
310 <bitfield name="UBRR" mask="0x03" text="USART Baud Rate Register bits" icon="" lsb="8"/>
311 </reg>
312 <reg size="1" name="UBRRL" offset="0x29" text="USART Baud Rate Register Low Byte" icon="io_com.bmp" mask="0xFF"/>
313 </registers>
314 </module>
315 <module class="PORTA">
316 <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
317 <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
318 <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
319 <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
320 </registers>
321 </module>
322 <module class="PORTB">
323 <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
324 <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
325 <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
326 <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
327 </registers>
328 </module>
329 <module class="PORTC">
330 <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
331 <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
332 <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
333 <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
334 </registers>
335 </module>
336 <module class="PORTD">
337 <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
338 <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
339 <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
340 <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
341 </registers>
342 </module>
343 <module class="SPI">
344 <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
345 <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
346 <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
347 <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
348 <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
349 <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
350 </reg>
351 <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
352 <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
353 <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
354 <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
355 <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
356 <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
357 <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
358 <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
359 </reg>
360 </registers>
361 </module>
362 <module class="EEPROM">
363 <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
364 <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Address Register Bytes" icon="io_cpu.bmp" mask="0x01FF"/>
365 <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
366 <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
367 <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
368 <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
369 <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
370 <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
371 </reg>
372 </registers>
373 </module>
374 <module class="TIMER_COUNTER_0">
375 <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
376 <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter Control Register" icon="io_flag.bmp">
377 <bitfield name="FOC0" mask="0x80" text="Force Output Compare" icon=""/>
378 <bitfield name="WGM00" mask="0x40" text="Waveform Generation Mode 0" icon="" enum="WAVEFORM_GEN_MODE"/>
379 <bitfield name="COM0" mask="0x30" text="Compare Match Output Modes" icon=""/>
380 <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
381 <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
382 </reg>
383 <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
384 <reg size="1" name="OCR0" offset="0x5C" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
385 <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
386 <bitfield name="OCIE0" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt register" icon=""/>
387 <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
388 </reg>
389 <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
390 <bitfield name="OCF0" mask="0x02" text="Output Compare Flag 0" icon=""/>
391 <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
392 </reg>
393 <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
394 <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
395 </reg>
396 </registers>
397 </module>
398 <module class="TIMER_COUNTER_1">
399 <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
400 <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
401 <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
402 <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
403 <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
404 <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
405 </reg>
406 <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
407 <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
408 <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
409 <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
410 <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
411 </reg>
412 <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
413 <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
414 <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
415 <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
416 <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
417 <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
418 </reg>
419 <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
420 <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
421 <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
422 <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
423 <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
424 </reg>
425 <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1 Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
426 <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
427 <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
428 <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
429 </registers>
430 </module>
431 <module class="TIMER_COUNTER_2">
432 <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
433 <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
434 <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
435 <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
436 </reg>
437 <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
438 <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
439 <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
440 </reg>
441 <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
442 <bitfield name="FOC2" mask="0x80" text="Force Output Compare" icon=""/>
443 <bitfield name="WGM20" mask="0x40" text="Waveform Genration Mode" icon="" enum="WAVEFORM_GEN_MODE"/>
444 <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon=""/>
445 <bitfield name="WGM21" mask="0x08" text="Waveform Generation Mode" icon=""/>
446 <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
447 </reg>
448 <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
449 <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
450 <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
451 <bitfield name="AS2" mask="0x08" text="Asynchronous Timer/counter2" icon=""/>
452 <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
453 <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
454 <bitfield name="TCR2UB" mask="0x01" text="Timer/counter Control Register2 Update Busy" icon=""/>
455 </reg>
456 <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
457 <bitfield name="PSR2" mask="0x02" text="Prescaler Reset Timer/Counter2" icon=""/>
458 </reg>
459 </registers>
460 </module>
461 <module class="EXTERNAL_INTERRUPT">
462 <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
463 <reg size="1" name="GICR" offset="0x5B" text="General Interrupt Control Register" icon="io_flag.bmp">
464 <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
465 <bitfield name="INT2" mask="0x20" text="External Interrupt Request 2 Enable" icon=""/>
466 <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
467 <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
468 </reg>
469 <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_flag.bmp">
470 <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
471 <bitfield name="INTF2" mask="0x20" text="External Interrupt Flag 2" icon=""/>
472 </reg>
473 <reg size="1" name="MCUCR" offset="0x55" text="General Interrupt Control Register" icon="io_flag.bmp">
474 <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
475 <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
476 </reg>
477 <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
478 <bitfield name="ISC2" mask="0x40" text="Interrupt Sense Control 2" icon=""/>
479 </reg>
480 </registers>
481 </module>
482 <module class="WATCHDOG">
483 <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
484 <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
485 <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
486 <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
487 <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
488 </reg>
489 </registers>
490 </module>
491 <module class="CPU">
492 <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
493 <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
494 <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
495 <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
496 <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
497 <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
498 <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
499 <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
500 <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
501 <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
502 </reg>
503 <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x07FF"/>
504 <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
505 <bitfield name="SM" mask="0xB0" text="Sleep Mode Select" icon=""/>
506 <bitfield name="SE" mask="0x40" text="Sleep Enable" icon=""/>
507 <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon=""/>
508 <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon=""/>
509 </reg>
510 <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
511 <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
512 <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
513 <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
514 <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
515 </reg>
516 <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
517 <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
518 <bitfield name="ACME" mask="0x08" text="Anlog Comparator Multiplexer Enable" icon=""/>
519 <bitfield name="PUD" mask="0x04" text="Pull-up Disable" icon=""/>
520 </reg>
521 <reg size="1" name="SPMCR" offset="0x57" text="" icon="io_cpu.bmp">
522 <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
523 <bitfield name="RWWSB" mask="0x40" text="Read-While-Write Section Busy" icon=""/>
524 <bitfield name="RWWSRE" mask="0x10" text="Read-While-Write Section Read Enable" icon=""/>
525 <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
526 <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
527 <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
528 <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
529 </reg>
530 </registers>
531 </module>
532 </hardware>
533 </device>