devices/atmega323

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <interrupts num="21">
   5     <interrupt vector="1" address="$000" name="RESET">External Pin, Power-on Reset, Brown-out Reset  and Watchdog Reset</interrupt>
   6     <interrupt vector="2" address="$002" name="INT0">External Interrupt Request 0</interrupt>
   7     <interrupt vector="3" address="$004" name="INT1">External Interrupt Request 1</interrupt>
   8     <interrupt vector="4" address="$006" name="INT2">External Interrupt Request 2</interrupt>
   9     <interrupt vector="5" address="$008" name="TIMER2 COMP">Timer/Counter2 Compare Match</interrupt>
  10     <interrupt vector="6" address="$00A" name="TIMER2 OVF">Timer/Counter2 Overflow</interrupt>
  11     <interrupt vector="7" address="$00C" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
  12     <interrupt vector="8" address="$00E" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
  13     <interrupt vector="9" address="$010" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
  14     <interrupt vector="10" address="$012" name="TIMER1 OVF">Timer/Counter1 Overflow</interrupt>
  15     <interrupt vector="11" address="$014" name="TIMER0 COMP">Timer/Counter0 Compare Match</interrupt>
  16     <interrupt vector="12" address="$016" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
  17     <interrupt vector="13" address="$018" name="SPI, STC">Serial Transfer Complete</interrupt>
  18     <interrupt vector="14" address="$01A" name="USART, RXC">USART, Rx Complete</interrupt>
  19     <interrupt vector="15" address="$01C" name="USART, UDRE">USART Data Register Empty</interrupt>
  20     <interrupt vector="16" address="$01E" name="USART, TXC">USART, Tx Complete</interrupt>
  21     <interrupt vector="17" address="$020" name="ADC">ADC Conversion Complete</interrupt>
  22     <interrupt vector="18" address="$022" name="EE_RDY">EEPROM Ready</interrupt>
  23     <interrupt vector="19" address="$024" name="ANA_COMP">Analog Comparator</interrupt>
  24     <interrupt vector="20" address="$026" name="TWI">2-wire Serial Interface</interrupt>
  25     <interrupt vector="21" address="$28" name="SPM_RDY">Store Program Memory Ready</interrupt>
  26   </interrupts>
  27   <memory>
  28     <flash size="32768"/>
  29     <iospace start="$20" stop="$5F"/>
  30     <sram size="2048"/>
  31     <eram size="0"/>
  32   </memory>
  33   <ioregisters>
  34     <ioreg name="TWBR" address="$00"/>
  35     <ioreg name="TWSR" address="$01"/>
  36     <ioreg name="TWAR" address="$02"/>
  37     <ioreg name="TWDR" address="$03"/>
  38     <ioreg name="ADCL" address="$04"/>
  39     <ioreg name="ADCH" address="$05"/>
  40     <ioreg name="ADCSR" address="$06"/>
  41     <ioreg name="ADMUX" address="$07"/>
  42     <ioreg name="ACSR" address="$08"/>
  43     <ioreg name="UBRRL" address="$09"/>
  44     <ioreg name="UCSRB" address="$0A"/>
  45     <ioreg name="UCSRA" address="$0B"/>
  46     <ioreg name="UDR" address="$0C"/>
  47     <ioreg name="SPCR" address="$0D"/>
  48     <ioreg name="SPSR" address="$0E"/>
  49     <ioreg name="SPDR" address="$0F"/>
  50     <ioreg name="PIND" address="$10"/>
  51     <ioreg name="DDRD" address="$11"/>
  52     <ioreg name="PORTD" address="$12"/>
  53     <ioreg name="PINC" address="$13"/>
  54     <ioreg name="DDRC" address="$14"/>
  55     <ioreg name="PORTC" address="$15"/>
  56     <ioreg name="PINB" address="$16"/>
  57     <ioreg name="DDRB" address="$17"/>
  58     <ioreg name="PORTB" address="$18"/>
  59     <ioreg name="PINA" address="$19"/>
  60     <ioreg name="DDRA" address="$1A"/>
  61     <ioreg name="PORTA" address="$1B"/>
  62     <ioreg name="EECR" address="$1C"/>
  63     <ioreg name="EEDR" address="$1D"/>
  64     <ioreg name="EEARL" address="$1E"/>
  65     <ioreg name="EEARH" address="$1F"/>
  66     <ioreg name="UBRRH" address="$20"/>
  67     <ioreg name="UCSRC" address="$20"/>
  68     <ioreg name="WDTCR" address="$21"/>
  69     <ioreg name="ASSR" address="$22"/>
  70     <ioreg name="OCR2" address="$23"/>
  71     <ioreg name="TCNT2" address="$24"/>
  72     <ioreg name="TCCR2" address="$25"/>
  73     <ioreg name="ICR1L" address="$26"/>
  74     <ioreg name="ICR1H" address="$27"/>
  75     <ioreg name="OCR1BL" address="$28"/>
  76     <ioreg name="OCR1BH" address="$29"/>
  77     <ioreg name="OCR1AL" address="$2A"/>
  78     <ioreg name="OCR1AH" address="$2B"/>
  79     <ioreg name="TCNT1L" address="$2C"/>
  80     <ioreg name="TCNT1H" address="$2D"/>
  81     <ioreg name="TCCR1B" address="$2E"/>
  82     <ioreg name="TCCR1A" address="$2F"/>
  83     <ioreg name="SFIOR" address="$30"/>
  84     <ioreg name="OSCCAL" address="$31"/>
  85     <ioreg name="OCDR" address="$31"/>
  86     <ioreg name="TCNT0" address="$32"/>
  87     <ioreg name="TCCR0" address="$33"/>
  88     <ioreg name="MCUCSR" address="$34"/>
  89     <ioreg name="MCUCR" address="$35"/>
  90     <ioreg name="TWCR" address="$36"/>
  91     <ioreg name="SPMCR" address="$37"/>
  92     <ioreg name="TIFR" address="$38"/>
  93     <ioreg name="TIMSK" address="$39"/>
  94     <ioreg name="GIFR" address="$3A"/>
  95     <ioreg name="GICR" address="$3B"/>
  96     <ioreg name="OCR0" address="$3C"/>
  97     <ioreg name="SPL" address="$3D"/>
  98     <ioreg name="SPH" address="$3E"/>
  99     <ioreg name="SREG" address="$3F"/>
 100   </ioregisters>
 101   <packages>
 102     <package name="TQFP" pins="44">
 103       <pin id="1" name="[PB5:MOSI]">MOSI: SPI Master data output, slave data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit. See the description of the SPI port for further details.</pin>
 104       <pin id="2" name="[PB6:MISO]">MISO: Master data input, slave data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of this pin is controlled by DDB6. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB6 bit. See the description of the SPI port for further details.</pin>
 105       <pin id="3" name="[PB7_SCK]">SCK: Master clock output, slave clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a master, the data direction of this pin is con-trolled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit. See the description of the SPI port for further details.</pin>
 106       <pin id="4" name="['RESET]"/>
 107       <pin id="5" name="[VCC]"/>
 108       <pin id="6" name="[GND]"/>
 109       <pin id="7" name="[XTAL2]"/>
 110       <pin id="8" name="[XTAL1]"/>
 111       <pin id="9" name="[PD0:RXD]">Receive Data (data input pin for the UART). When the UART Receiver is enabled, this pin is configured as an input, regard-less of the value of DDD0. When the UART forces this pin to be an input, a logical “1” in PORTD0 will turn on the internal pull-up.</pin>
 112       <pin id="10" name="[PD1:TXD]">Transmit Data (data output pin for the UART). When the UART Transmitter is enabled, this pin is configured as an output, regardless of the value of DDD1.</pin>
 113       <pin id="11" name="[PD2:INT0]">INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 114       <pin id="12" name="[PD3:INT1]">INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source to the MCU. See the interrupt description for further details and how to enable the source.</pin>
 115       <pin id="13" name="[PD4:OC1B]">OC1B, Output compare matchB output: The PD4 pin can serve as an external output for the Timer/Counter1 output com-pareB. The pin has to be configured as an output (DDD4 set [one]) to serve this function. See the timer description on how to enable this function. The OC1B pin is also the output pin for the PWM mode timer function.</pin>
 116       <pin id="14" name="[PD5:OC1A]">OC1A, Output compare matchA output: The PD5 pin can serve as an external output for the Timer/Counter1 output com-pareA. The pin has to be configured as an output (DDD5 set [one]) to serve this function. See the timer description on how to enable this function. The OC1A pin is also the output pin for the PWM mode timer function.</pin>
 117       <pin id="15" name="[PD6:ICP]">ICP – Input Capture Pin: The PD6 pin can act as an input capture pin for Timer/Counter1. The pin has to be configured as an input (DDD6 cleared [zero]) to serve this function. See the timer description on how to enable this function.</pin>
 118       <pin id="16" name="[PD7:OC2]">OC2, Timer/Counter2 output compare match output: The PD7 pin can serve as an external output for the Timer/Counter2 output compare. The pin has to be configured as an output (DDD7 set [one]) to serve this function. See the timer descrip-tion on how to enable this function. The OC2 pin is also the output pin for the PWM mode timer function.</pin>
 119       <pin id="17" name="[VCC]"/>
 120       <pin id="18" name="[GND]"/>
 121       <pin id="19" name="[PC0:SCL]">SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal.</pin>
 122       <pin id="20" name="[PC1:SDA]">SDA, 2-wire Serial Bus Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PC1 is dis-connected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to capture spikes shorter than 50 ns on the input signal, and the pin is driven by an open collector driver with slew rate limitation.</pin>
 123       <pin id="21" name="[PC2:TMS]">TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. Refer to the section “JTAG Interface and the On-Chip Debug System” on page 130 for details on operation of the JTAG interface.</pin>
 124       <pin id="22" name="[PC3:TCK]">TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. Refer to the section “JTAG Interface and the On-Chip Debug System” on page 130 for details on operation of the JTAG interface.</pin>
 125       <pin id="23" name="[PC4:TDO]">TDO, JTAG Test Data Out: Serial output data from Instruction register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. Refer to the section “JTAG Interface and the On-Chip Debug System” on page 130 for details on operation of the JTAG interface.</pin>
 126       <pin id="24" name="[PC5:TDI]">TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin. Refer to the section “JTAG Interface and the On-Chip Debug System” on page 130 for details on operation of the JTAG interface.</pin>
 127       <pin id="25" name="[PC6:TOSC1]">TOSC1, Timer Oscillator pin 1: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter1, pin PC6 is disconnected from the port, and becomes the input of the inverting oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.</pin>
 128       <pin id="26" name="[PC7:TOSC2]">TOSC2, Timer Oscillator pin 2: When the AS2 bit in ASSR is set (one) to enable asynchronous clocking of Timer/Counter2, pin PC7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. In this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an I/O pin.</pin>
 129       <pin id="27" name="[AVCC]"/>
 130       <pin id="28" name="[AGND]"/>
 131       <pin id="29" name="[AREF]"/>
 132       <pin id="30" name="[PA7:ADC7]"/>
 133       <pin id="31" name="[PA6:ADC6]"/>
 134       <pin id="32" name="[PA5:ADc5]"/>
 135       <pin id="33" name="[PA4:ADC4]"/>
 136       <pin id="34" name="[PA3:ADC3]"/>
 137       <pin id="35" name="[PA2:ADC2]"/>
 138       <pin id="36" name="[PA1:ADC1]"/>
 139       <pin id="37" name="[PA0:ADC0]"/>
 140       <pin id="38" name="[VCC]"/>
 141       <pin id="39" name="[GND]"/>
 142       <pin id="40" name="[PB0:XCK:T0]">T0, Timer/Counter0 counter source. See the timer description for further details. XCK, USART external clock. See the USART description for further details.</pin>
 143       <pin id="41" name="[PB1:T1]">T1: Timer/Counter1 counter source. See the timer description for further details</pin>
 144       <pin id="42" name="[PB2:AIN0:INT2]">AIN0, Analog Comparator Positive Input. When configured as an input (DDB2 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB2 is cleared (zero)), this pin also serves as the positive input of the on-chip analog compar-ator. During power down mode, the schmitt trigger of the digital input is disconnected if INT2 is not enabled. This allows analog signals which are close to V CC /2 to be present during power down without causing excessive power consumption. INT2, External Interrupt source 2: The PB2 pin can serve as an external interrupt source to the MCU. See “MCU Control and Status Register - MCUCSR” for further details</pin>
 145       <pin id="43" name="[PB3:AIN1:OC0]">AIN1, Analog Comparator Negative Input. When configured as an input (DDB3 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB3 is cleared (zero)), this pin also serves as the negative input of the on-chip analog compar-ator. During power down mode, the schmitt trigger of the digital input is disconnected. This allows analog signals which are close to V CC /2 to be present during power down without causing excessive power consumption. OC0, Output compare match output: The PB3 pin can serve as an external output for the Timer/Counter0 compare match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. See “8-bit Timers/Counters T/C0 and T/C2” for further details, and how to enable the output. The OC0 pin is also the output pin for the PWM mode timer functio</pin>
 146       <pin id="44" name="[PB4:'SS]">SS: Slave port select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direc-tion of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit. See the description of the SPI port for further details.</pin>
 147     </package>
 148   </packages>
 149   <hardware>
 150 <!--Everything after this needs editing!!!-->
 151     <module class="FUSE">
 152       <registers name="FUSE" memspace="FUSE">
 153           <reg size="1" name="HIGH" offset="0x01">
 154             <bitfield name="OCDEN" mask="0x80" text="On-Chip Debug Enabled" icon=""/>
 155             <bitfield name="JTAGEN" mask="0x40" text="JTAG Enabled" icon=""/>
 156             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 157             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM memory during through Chip Erase Cycle" icon=""/>
 158             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 159             <bitfield name="BOOTRST" mask="0x01" text="Boot Reset vector Enabled (default address=$0000)" icon=""/>
 160           </reg>
 161           <reg size="1" name="LOW" offset="0x00">
 162             <bitfield name="BODLEVEL" mask="0x80" text="Brown out detector trigger level" icon="" enum="ENUM_BODLEVEL"/>
 163             <bitfield name="BODEN" mask="0x40" text="Brown-out detection enabled" icon=""/>
 164             <bitfield name="CKSEL" mask="0x0F" text="Select Clock Source" icon="" enum="ENUM_CKSEL"/>
 165           </reg>
 166         </registers>
 167     </module>
 168     <module class="LOCKBIT">
 169       <registers name="LOCKBIT" memspace="LOCKBIT">
 170           <reg size="1" name="LOCKBIT" offset="0x00">
 171             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 172             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 173             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 174           </reg>
 175         </registers>
 176     </module>
 177     <module class="PORTA">
 178       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 179           <reg size="1" name="PORTA" offset="0x3B" text="Port A Data Register" icon="io_port.bmp" mask="0xFF"/>
 180           <reg size="1" name="DDRA" offset="0x3A" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 181           <reg size="1" name="PINA" offset="0x39" text="Port A Input Pins" icon="io_port.bmp" mask="0xFF"/>
 182         </registers>
 183     </module>
 184     <module class="PORTB">
 185       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 186           <reg size="1" name="PORTB" offset="0x38" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 187           <reg size="1" name="DDRB" offset="0x37" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 188           <reg size="1" name="PINB" offset="0x36" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 189         </registers>
 190     </module>
 191     <module class="PORTC">
 192       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 193           <reg size="1" name="PORTC" offset="0x35" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 194           <reg size="1" name="DDRC" offset="0x34" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 195           <reg size="1" name="PINC" offset="0x33" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 196         </registers>
 197     </module>
 198     <module class="PORTD">
 199       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 200           <reg size="1" name="PORTD" offset="0x32" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 201           <reg size="1" name="DDRD" offset="0x31" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 202           <reg size="1" name="PIND" offset="0x30" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 203         </registers>
 204     </module>
 205     <module class="WATCHDOG">
 206       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 207           <reg size="1" name="WDTCR" offset="0x41" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 208             <bitfield name="WDTOE" mask="0x10" text="RW" icon=""/>
 209             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 210             <bitfield name="WDP" mask="0x07" text="Watch Dog Timer Prescaler bits" icon="" enum="WDOG_TIMER_PRESCALE_3BITS"/>
 211           </reg>
 212         </registers>
 213     </module>
 214     <module class="SPI">
 215       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 216           <reg size="1" name="SPDR" offset="0x2F" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 217           <reg size="1" name="SPSR" offset="0x2E" text="SPI Status Register" icon="io_flag.bmp">
 218             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 219             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 220             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 221           </reg>
 222           <reg size="1" name="SPCR" offset="0x2D" text="SPI Control Register" icon="io_flag.bmp">
 223             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 224             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 225             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 226             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 227             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 228             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 229             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 230           </reg>
 231         </registers>
 232     </module>
 233     <module class="USART">
 234       <registers name="USART" memspace="DATAMEM" text="" icon="io_com.bmp">
 235           <reg size="1" name="UDR" offset="0x2C" text="USART I/O Data Register" icon="io_com.bmp" mask="0xFF"/>
 236           <reg size="1" name="UCSRA" offset="0x2B" text="USART Control and Status Register A" icon="io_flag.bmp">
 237             <bitfield name="RXC" mask="0x80" text="USART Receive Complete" icon=""/>
 238             <bitfield name="TXC" mask="0x40" text="USART Transmitt Complete" icon=""/>
 239             <bitfield name="UDRE" mask="0x20" text="USART Data Register Empty" icon=""/>
 240             <bitfield name="FE" mask="0x10" text="Framing Error" icon=""/>
 241             <bitfield name="DOR" mask="0x08" text="Data overRun" icon=""/>
 242             <bitfield name="UPE" mask="0x04" text="Parity Error" icon=""/>
 243             <bitfield name="U2X" mask="0x02" text="Double the USART transmission speed" icon=""/>
 244             <bitfield name="MPCM" mask="0x01" text="Multi-processor Communication Mode" icon=""/>
 245           </reg>
 246           <reg size="1" name="UCSRB" offset="0x2A" text="USART Control and Status Register B" icon="io_flag.bmp">
 247             <bitfield name="RXCIE" mask="0x80" text="RX Complete Interrupt Enable" icon=""/>
 248             <bitfield name="TXCIE" mask="0x40" text="TX Complete Interrupt Enable" icon=""/>
 249             <bitfield name="UDRIE" mask="0x20" text="USART Data register Empty Interrupt Enable" icon=""/>
 250             <bitfield name="RXEN" mask="0x10" text="Receiver Enable" icon=""/>
 251             <bitfield name="TXEN" mask="0x08" text="Transmitter Enable" icon=""/>
 252             <bitfield name="UCSZ2" mask="0x04" text="Character Size" icon=""/>
 253             <bitfield name="RXB8" mask="0x02" text="Receive Data Bit 8" icon=""/>
 254             <bitfield name="TXB8" mask="0x01" text="Transmit Data Bit 8" icon=""/>
 255           </reg>
 256           <reg size="1" name="UCSRC" offset="0x40" text="USART Control and Status Register C" icon="io_flag.bmp">
 257             <bitfield name="URSEL" mask="0x80" text="Register Select" icon=""/>
 258             <bitfield name="UMSEL" mask="0x40" text="USART Mode Select" icon="" enum="COMM_USART_MODE"/>
 259             <bitfield name="UPM" mask="0x30" text="Parity Mode Bits" icon="" enum="COMM_UPM_PARITY_MODE"/>
 260             <bitfield name="USBS" mask="0x08" text="Stop Bit Select" icon="" enum="COMM_STOP_BIT_SEL"/>
 261             <bitfield name="UCSZ" mask="0x06" text="Character Size" icon=""/>
 262             <bitfield name="UCPOL" mask="0x01" text="Clock Polarity" icon=""/>
 263           </reg>
 264           <reg size="1" name="UBRRH" offset="0x40" text="USART Baud Rate Register Hight Byte" icon="io_com.bmp" mask="0x0F"/>
 265           <reg size="1" name="UBRRL" offset="0x29" text="USART Baud Rate Register Low Byte" icon="io_com.bmp" mask="0xFF"/>
 266         </registers>
 267     </module>
 268     <module class="AD_CONVERTER">
 269       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 270           <reg size="1" name="ADMUX" offset="0x27" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 271             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 272             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 273             <bitfield name="MUX" mask="0x1F" text="Analog Channel and Gain Selection Bits" icon=""/>
 274           </reg>
 275           <reg size="1" name="ADCSR" offset="0x26" text="The ADC Control and Status register" icon="io_flag.bmp">
 276             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 277             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 278             <bitfield name="ADATE" mask="0x20" text="When this bit is written to one,the Timer/Counter2 prescaler will be reset.The bit will be cleared by hardware after the operation is performed.Writing a zero to this bit will have no effect.This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock.If this bit is written when Timer/Counter2 is operating in asynchronous mode,the bit will remain one until the prescaler has been reset." icon=""/>
 279             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 280             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 281             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon="" enum="ANALIG_ADC_PRESCALER"/>
 282           </reg>
 283           <reg size="2" name="ADC" offset="0x24" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 284         </registers>
 285     </module>
 286     <module class="ANALOG_COMPARATOR">
 287       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 288           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_flag.bmp">
 289             <bitfield name="ACME" mask="0x08" text="Analog Comparator Multiplexer Enable" icon=""/>
 290           </reg>
 291           <reg size="1" name="ACSR" offset="0x28" text="Analog Comparator Control And Status Register" icon="io_analo.bmp">
 292             <bitfield name="ACD" mask="0x80" text="Analog Comparator Disable" icon=""/>
 293             <bitfield name="ACBG" mask="0x40" text="Analog Comparator Bandgap Select" icon=""/>
 294             <bitfield name="ACO" mask="0x20" text="Analog Compare Output" icon=""/>
 295             <bitfield name="ACI" mask="0x10" text="Analog Comparator Interrupt Flag" icon=""/>
 296             <bitfield name="ACIE" mask="0x08" text="Analog Comparator Interrupt Enable" icon=""/>
 297             <bitfield name="ACIC" mask="0x04" text="Analog Comparator Input Capture Enable" icon=""/>
 298             <bitfield name="ACIS" mask="0x03" text="Analog Comparator Interrupt Mode Select bits" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 299           </reg>
 300         </registers>
 301     </module>
 302     <module class="TWI">
 303       <registers name="TWI" memspace="DATAMEM" text="" icon="io_com.bmp">
 304           <reg size="1" name="TWBR" offset="0x20" text="TWI Bit Rate register" icon="io_com.bmp" mask="0xFF"/>
 305           <reg size="1" name="TWCR" offset="0x56" text="TWI Control Register" icon="io_flag.bmp">
 306             <bitfield name="TWINT" mask="0x80" text="TWI Interrupt Flag" icon=""/>
 307             <bitfield name="TWEA" mask="0x40" text="TWI Enable Acknowledge Bit" icon=""/>
 308             <bitfield name="TWSTA" mask="0x20" text="TWI Start Condition Bit" icon=""/>
 309             <bitfield name="TWSTO" mask="0x10" text="TWI Stop Condition Bit" icon=""/>
 310             <bitfield name="TWWC" mask="0x08" text="TWI Write Collition Flag" icon=""/>
 311             <bitfield name="TWEN" mask="0x04" text="TWI Enable Bit" icon=""/>
 312             <bitfield name="TWIE" mask="0x01" text="TWI Interrupt Enable" icon=""/>
 313           </reg>
 314           <reg size="1" name="TWSR" offset="0x21" text="TWI Status Register" icon="io_flag.bmp">
 315             <bitfield name="TWS" mask="0xF8" text="TWI Status" icon="" lsb="3"/>
 316           </reg>
 317           <reg size="1" name="TWDR" offset="0x23" text="TWI Data register" icon="io_com.bmp" mask="0xFF"/>
 318           <reg size="1" name="TWAR" offset="0x22" text="TWI (Slave) Address register" icon="io_com.bmp" mask="0xFF"/>
 319         </registers>
 320     </module>
 321     <module class="EEPROM">
 322       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 323           <reg size="2" name="EEAR" offset="0x3E" text="EEPROM Read/Write Access  Bytes" icon="io_cpu.bmp" mask="0x03FF"/>
 324           <reg size="1" name="EEDR" offset="0x3D" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 325           <reg size="1" name="EECR" offset="0x3C" text="EEPROM Control Register" icon="io_flag.bmp">
 326             <bitfield name="EERIE" mask="0x08" text="EEPROM Ready Interrupt Enable" icon=""/>
 327             <bitfield name="EEMWE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 328             <bitfield name="EEWE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 329             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 330           </reg>
 331         </registers>
 332     </module>
 333     <module class="CPU">
 334       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 335           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 336             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 337             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 338             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 339             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 340             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 341             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 342             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 343             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 344           </reg>
 345           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x0FFF"/>
 346           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 347             <bitfield name="SE" mask="0x80" text="Sleep Enable" icon=""/>
 348             <bitfield name="SM" mask="0x70" text="Sleep Mode Select" icon="" enum="CPU_SLEEP_MODE_3BITS"/>
 349             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 350             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL2"/>
 351           </reg>
 352           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 353             <bitfield name="JDT" mask="0x80" text="" icon=""/>
 354             <bitfield name="ISC2" mask="0x40" text="Interrupt Sense Control 2" icon=""/>
 355             <bitfield name="JTRF" mask="0x10" text="JTAG Reset Flag" icon=""/>
 356             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 357             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 358             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 359             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 360           </reg>
 361           <reg size="1" name="OSCCAL" offset="0x51" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 362           <reg size="1" name="SPMCR" offset="0x57" text="Store Program Memory Control Register" icon="io_cpu.bmp" mask="0x5F"/>
 363           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp" mask="0x0F"/>
 364         </registers>
 365     </module>
 366     <module class="TIMER_COUNTER_0">
 367       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 368           <reg size="1" name="TCCR0" offset="0x53" text="Timer/Counter Control Register" icon="io_flag.bmp">
 369             <bitfield name="FOC0" mask="0x80" text="Force Output Compare" icon=""/>
 370             <bitfield name="PWM0" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 371             <bitfield name="COM0" mask="0x30" text="Compare Match Output Modes" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 372             <bitfield name="WGM01" mask="0x08" text="Waveform Generation Mode 1" icon=""/>
 373             <bitfield name="CS0" mask="0x07" text="Clock Selects" icon="" enum="CLK_SEL_3BIT_EXT"/>
 374           </reg>
 375           <reg size="1" name="TCNT0" offset="0x52" text="Timer/Counter Register" icon="io_timer.bmp" mask="0xFF"/>
 376           <reg size="1" name="OCR0" offset="0x5C" text="Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 377           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 378             <bitfield name="OCIE0" mask="0x02" text="Timer/Counter0 Output Compare Match Interrupt register" icon=""/>
 379             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 380           </reg>
 381           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 382             <bitfield name="OCF0" mask="0x02" text="Output Compare Flag 0" icon=""/>
 383             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 384           </reg>
 385           <reg size="1" name="SFIOR" offset="0x50" text="Special Function IO Register" icon="io_cpu.bmp">
 386             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 387           </reg>
 388         </registers>
 389     </module>
 390     <module class="EXTERNAL_INTERRUPT">
 391       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 392           <reg size="1" name="GICR" offset="0x5B" text="General Interrupt Control Register" icon="io_flag.bmp">
 393             <bitfield name="INT" mask="0xC0" text="External Interrupt Request 1 Enable" icon=""/>
 394             <bitfield name="INT2" mask="0x20" text="External Interrupt Request 2 Enable" icon=""/>
 395             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 396             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 397           </reg>
 398           <reg size="1" name="GIFR" offset="0x5A" text="General Interrupt Flag Register" icon="io_flag.bmp">
 399             <bitfield name="INTF" mask="0xC0" text="External Interrupt Flags" icon=""/>
 400             <bitfield name="INTF2" mask="0x20" text="External Interrupt Flag 2" icon=""/>
 401           </reg>
 402           <reg size="1" name="MCUCR" offset="0x55" text="General Interrupt Control Register" icon="io_flag.bmp">
 403             <bitfield name="ISC1" mask="0x0C" text="Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 404             <bitfield name="ISC0" mask="0x03" text="Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 405           </reg>
 406           <reg size="1" name="MCUCSR" offset="0x54" text="MCU Control And Status Register" icon="io_flag.bmp">
 407             <bitfield name="ISC2" mask="0x40" text="Interrupt Sense Control 2" icon=""/>
 408           </reg>
 409         </registers>
 410     </module>
 411     <module class="TIMER_COUNTER_1">
 412       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 413           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 414             <bitfield name="TICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 415             <bitfield name="OCIE1A" mask="0x10" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 416             <bitfield name="OCIE1B" mask="0x08" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 417             <bitfield name="TOIE1" mask="0x04" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 418           </reg>
 419           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 420             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 421             <bitfield name="OCF1A" mask="0x10" text="Output Compare Flag 1A" icon=""/>
 422             <bitfield name="OCF1B" mask="0x08" text="Output Compare Flag 1B" icon=""/>
 423             <bitfield name="TOV1" mask="0x04" text="Timer/Counter1 Overflow Flag" icon=""/>
 424           </reg>
 425           <reg size="1" name="TCCR1A" offset="0x4F" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 426             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 427             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 428             <bitfield name="FOC1A" mask="0x08" text="Force Output Compare 1A" icon=""/>
 429             <bitfield name="FOC1B" mask="0x04" text="Force Output Compare 1B" icon=""/>
 430             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 431           </reg>
 432           <reg size="1" name="TCCR1B" offset="0x4E" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 433             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 434             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 435             <bitfield name="CTC1" mask="0x08" text="Clear Timer/Counter1 on Compare Match" icon=""/>
 436             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 437           </reg>
 438           <reg size="2" name="TCNT1" offset="0x4C" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 439           <reg size="2" name="OCR1A" offset="0x4A" text="Timer/Counter1 Outbut Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 440           <reg size="2" name="OCR1B" offset="0x48" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 441           <reg size="2" name="ICR1" offset="0x46" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 442         </registers>
 443     </module>
 444     <module class="TIMER_COUNTER_2">
 445       <registers name="TIMER_COUNTER_2" memspace="DATAMEM" text="" icon="io_timer.bmp">
 446           <reg size="1" name="TIMSK" offset="0x59" text="Timer/Counter Interrupt Mask register" icon="io_flag.bmp">
 447             <bitfield name="OCIE2" mask="0x80" text="Timer/Counter2 Output Compare Match Interrupt Enable" icon=""/>
 448             <bitfield name="TOIE2" mask="0x40" text="Timer/Counter2 Overflow Interrupt Enable" icon=""/>
 449           </reg>
 450           <reg size="1" name="TIFR" offset="0x58" text="Timer/Counter Interrupt Flag Register" icon="io_flag.bmp">
 451             <bitfield name="OCF2" mask="0x80" text="Output Compare Flag 2" icon=""/>
 452             <bitfield name="TOV2" mask="0x40" text="Timer/Counter2 Overflow Flag" icon=""/>
 453           </reg>
 454           <reg size="1" name="TCCR2" offset="0x45" text="Timer/Counter2 Control Register" icon="io_flag.bmp">
 455             <bitfield name="FOC2" mask="0x80" text="Force Output Compare" icon=""/>
 456             <bitfield name="PWM2" mask="0x40" text="Pulse Width Modulator Enable" icon=""/>
 457             <bitfield name="COM2" mask="0x30" text="Compare Output Mode bits" icon="" enum="CLK_COMP_MATCH_OUT_MODE"/>
 458             <bitfield name="CTC2" mask="0x08" text="Clear Timer/Counter2 on Compare Match" icon=""/>
 459             <bitfield name="CS2" mask="0x07" text="Clock Select bits" icon="" enum="CLK_SEL_3BIT"/>
 460           </reg>
 461           <reg size="1" name="TCNT2" offset="0x44" text="Timer/Counter2" icon="io_timer.bmp" mask="0xFF"/>
 462           <reg size="1" name="OCR2" offset="0x43" text="Timer/Counter2 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 463           <reg size="1" name="ASSR" offset="0x42" text="Asynchronous Status Register" icon="io_flag.bmp">
 464             <bitfield name="AS2" mask="0x08" text="Asynchronous Timer/counter2" icon=""/>
 465             <bitfield name="TCN2UB" mask="0x04" text="Timer/Counter2 Update Busy" icon=""/>
 466             <bitfield name="OCR2UB" mask="0x02" text="Output Compare Register2 Update Busy" icon=""/>
 467             <bitfield name="TCR2UB" mask="0x01" text="Timer/counter Control Register2 Update Busy" icon=""/>
 468           </reg>
 469         </registers>
 470     </module>
 471   </hardware>
 472 </device>