devices/atmega16hva

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="16384"/>
   6     <iospace start="$20" stop="$FF"/>
   7     <sram size="512"/>
   8     <eram size="NA"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="PINA" address="0x00"/>
  12     <ioreg name="DDRA" address="0x01"/>
  13     <ioreg name="PORTA" address="0x02"/>
  14     <ioreg name="PINB" address="0x03"/>
  15     <ioreg name="DDRB" address="0x04"/>
  16     <ioreg name="PORTB" address="0x05"/>
  17     <ioreg name="PINC" address="0x06"/>
  18     <ioreg name="PORTC" address="0x08"/>
  19     <ioreg name="TIFR0" address="0x15"/>
  20     <ioreg name="TIFR1" address="0x16"/>
  21     <ioreg name="OSICSR" address="0x17"/>
  22     <ioreg name="EIFR" address="0x1C"/>
  23     <ioreg name="EIMSK" address="0x1D"/>
  24     <ioreg name="GPIOR0" address="0x1E"/>
  25     <ioreg name="EECR" address="0x1F"/>
  26     <ioreg name="EEDR" address="0x20"/>
  27     <ioreg name="EEAR" address="0x21"/>
  28     <ioreg name="GTCCR" address="0x23"/>
  29     <ioreg name="TCCR0A" address="0x24"/>
  30     <ioreg name="TCCR0B" address="0x25"/>
  31     <ioreg name="TCNT0L" address="0x26"/>
  32     <ioreg name="TCNT0H" address="0x27"/>
  33     <ioreg name="OCR0A" address="0x28"/>
  34     <ioreg name="OCR0B" address="0x29"/>
  35     <ioreg name="GPIOR1" address="0x2A"/>
  36     <ioreg name="GPIOR2" address="0x2B"/>
  37     <ioreg name="SPCR" address="0x2c"/>
  38     <ioreg name="SPSR" address="0x2d"/>
  39     <ioreg name="SPDR" address="0x2e"/>
  40     <ioreg name="DWDR" address="0x31"/>
  41     <ioreg name="SMCR" address="0x33"/>
  42     <ioreg name="MCUSR" address="0x34"/>
  43     <ioreg name="MCUCR" address="0x35"/>
  44     <ioreg name="SPMCSR" address="0x37"/>
  45     <ioreg name="SPL" address="0x3D"/>
  46     <ioreg name="SPH" address="0x3E"/>
  47     <ioreg name="SREG" address="0x3F"/>
  48     <ioreg name="WDTCSR" address="0x60"/>
  49     <ioreg name="CLKPR" address="0x61"/>
  50     <ioreg name="PRR0" address="0x64"/>
  51     <ioreg name="FOSCCAL" address="0x66"/>
  52     <ioreg name="EICRA" address="0x69"/>
  53     <ioreg name="TIMSK0" address="0x6E"/>
  54     <ioreg name="TIMSK1" address="0x6F"/>
  55     <ioreg name="VADCL" address="0x78"/>
  56     <ioreg name="VADCH" address="0x79"/>
  57     <ioreg name="VADCSR" address="0x7A"/>
  58     <ioreg name="VADMUX" address="0x7C"/>
  59     <ioreg name="DIDR0" address="0x7E"/>
  60     <ioreg name="TCCR1A" address="0x80"/>
  61     <ioreg name="TCCR1B" address="0x81"/>
  62     <ioreg name="TCNT1L" address="0x84"/>
  63     <ioreg name="TCNT1H" address="0x85"/>
  64     <ioreg name="OCR1A" address="0x88"/>
  65     <ioreg name="OCR1B" address="0x89"/>
  66     <ioreg name="ROCR" address="0xC8"/>
  67     <ioreg name="BGCCR" address="0xD0"/>
  68     <ioreg name="BGCRR" address="0xD1"/>
  69     <ioreg name="CADAC0" address="0xE0"/>
  70     <ioreg name="CADAC1" address="0xE1"/>
  71     <ioreg name="CADAC2" address="0xE2"/>
  72     <ioreg name="CADAC3" address="0xE3"/>
  73     <ioreg name="CADCSRA" address="0xE4"/>
  74     <ioreg name="CADCSRB" address="0xE5"/>
  75     <ioreg name="CADRC" address="0xE6"/>
  76     <ioreg name="CADICL" address="0xE8"/>
  77     <ioreg name="CADICH" address="0xE9"/>
  78     <ioreg name="FCSR" address="0xF0"/>
  79     <ioreg name="BPIMSK" address="0xF2"/>
  80     <ioreg name="BPIFR" address="0xF3"/>
  81     <ioreg name="BPSCD" address="0xF5"/>
  82     <ioreg name="BPDOCD" address="0xF6"/>
  83     <ioreg name="BPCOCD" address="0xF7"/>
  84     <ioreg name="BPDHCD" address="0xF8"/>
  85     <ioreg name="BPCHCD" address="0xF9"/>
  86     <ioreg name="BPSCTR" address="0xFA"/>
  87     <ioreg name="BPOCTR" address="0xFB"/>
  88     <ioreg name="BPHCTR" address="0xFC"/>
  89     <ioreg name="BPCR" address="0xFD"/>
  90     <ioreg name="BPPLR" address="0xFE"/>
  91   </ioregisters>
  92   <packages/>
  93   <interrupts num="21">
  94     <interrupt vector="1" address="$0000" name="RESET">External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset</interrupt>
  95     <interrupt vector="2" address="$0002" name="BPINT">Battery Protection Interrupt</interrupt>
  96     <interrupt vector="3" address="$0004" name="VREGMON">Voltage regulator monitor interrupt</interrupt>
  97     <interrupt vector="4" address="$0006" name="INT0">External Interrupt Request 0</interrupt>
  98     <interrupt vector="5" address="$0008" name="INT1">External Interrupt Request 1</interrupt>
  99     <interrupt vector="6" address="$000A" name="INT2">External Interrupt Request 2</interrupt>
 100     <interrupt vector="7" address="$000C" name="WDT">Watchdog Timeout Interrupt</interrupt>
 101     <interrupt vector="8" address="$000E" name="TIMER1_IC">Timer 1 Input capture</interrupt>
 102     <interrupt vector="9" address="$0010" name="TIMER1_COMPA">Timer 1 Compare Match A</interrupt>
 103     <interrupt vector="10" address="$0012" name="TIMER1_COMPB">Timer 1 Compare Match B</interrupt>
 104     <interrupt vector="11" address="$0014" name="TIMER1_OVF">Timer 1 overflow</interrupt>
 105     <interrupt vector="12" address="$0016" name="TIMER0_IC">Timer 0 Input Capture</interrupt>
 106     <interrupt vector="13" address="$0018" name="TIMER0_COMPA">Timer 0 Comapre Match A</interrupt>
 107     <interrupt vector="14" address="$001A" name="TIMER0_COMPB">Timer 0 Compare Match B</interrupt>
 108     <interrupt vector="15" address="$001C" name="TIMER0_OVF">Timer 0 Overflow</interrupt>
 109     <interrupt vector="16" address="$001E" name="SPI;STC">SPI Serial transfer complete</interrupt>
 110     <interrupt vector="17" address="$0020" name="VADC">Voltage ADC Conversion Complete</interrupt>
 111     <interrupt vector="18" address="$0022" name="CCADC_CONV">Coulomb Counter ADC Conversion Complete</interrupt>
 112     <interrupt vector="19" address="$0024" name="CCADC_REG_CUR">Coloumb Counter ADC Regular Current</interrupt>
 113     <interrupt vector="20" address="$0026" name="CCADC_ACC">Coloumb Counter ADC Accumulator</interrupt>
 114     <interrupt vector="21" address="$028" name="EE READY">EEPROM Ready</interrupt>
 115   </interrupts>
 116   <hardware>
 117 <!--Everything after this needs editing!!!-->
 118     <module class="FUSE">
 119       <registers name="FUSE" memspace="FUSE">
 120           <reg size="1" name="LOW" offset="0x00">
 121             <bitfield name="WDTON" mask="0x80" text="Watch-dog Timer always on" icon=""/>
 122             <bitfield name="EESAVE" mask="0x40" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 123             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 124             <bitfield name="DWEN" mask="0x10" text="Debug Wire enable" icon=""/>
 125             <bitfield name="SELFPRGEN" mask="0x08" text="Self Programming enable" icon=""/>
 126             <bitfield name="SUT" mask="0x07" text="Select start-up time" icon="" enum="ENUM_SUT"/>
 127           </reg>
 128         </registers>
 129     </module>
 130     <module class="LOCKBIT">
 131       <registers name="LOCKBIT" memspace="LOCKBIT">
 132           <reg size="1" name="LOCKBIT" offset="0x00">
 133             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 134           </reg>
 135         </registers>
 136     </module>
 137     <module class="AD_CONVERTER">
 138       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 139           <reg size="1" name="VADMUX" offset="0x7C" text="The VADC multiplexer Selection Register" icon="io_analo.bmp">
 140             <bitfield name="VADMUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 141           </reg>
 142           <reg size="2" name="VADC" offset="0x78" text="VADC Data Register  Bytes" icon="io_analo.bmp" mask="0x0FFF"/>
 143           <reg size="1" name="VADCSR" offset="0x7A" text="The VADC Control and Status register" icon="io_flag.bmp">
 144             <bitfield name="VADEN" mask="0x08" text="VADC Enable" icon=""/>
 145             <bitfield name="VADSC" mask="0x04" text="VADC Satrt Conversion" icon=""/>
 146             <bitfield name="VADCCIF" mask="0x02" text="VADC Conversion Complete Interrupt Flag" icon=""/>
 147             <bitfield name="VADCCIE" mask="0x01" text="VADC Conversion Complete Interrupt Enable" icon=""/>
 148           </reg>
 149         </registers>
 150     </module>
 151     <module class="WATCHDOG">
 152       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 153           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 154             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 155             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 156             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 157             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 158             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 159           </reg>
 160         </registers>
 161     </module>
 162     <module class="BANDGAP">
 163       <registers name="BANDGAP" memspace="DATAMEM" text="" icon="io_analo.bmp">
 164           <reg size="1" name="BGCRR" offset="0xD1" text="Bandgap Calibration of Resistor Ladder" icon="io_analo.bmp" mask="0xFF"/>
 165           <reg size="1" name="BGCCR" offset="0xD0" text="Bandgap Calibration Register" icon="io_analo.bmp">
 166             <bitfield name="BGD" mask="0x80" text="Setting the BGD bit to one will disable the bandgap voltage reference. This bit must be cleared before enabling CC-ADC or V-ADC, and must remain unset while either ADC is enabled." icon=""/>
 167             <bitfield name="BGCC" mask="0x3F" text="BG Calibration of PTAT Current Bits" icon=""/>
 168           </reg>
 169         </registers>
 170     </module>
 171     <module class="EXTERNAL_INTERRUPT">
 172       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 173           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register" icon="io_flag.bmp">
 174             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control 2 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 175             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control 1 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 176             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control 0 Bits" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 177           </reg>
 178           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 179             <bitfield name="INT" mask="0x07" text="External Interrupt Request 2 Enable" icon=""/>
 180           </reg>
 181           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 182             <bitfield name="INTF" mask="0x07" text="External Interrupt Flags" icon=""/>
 183           </reg>
 184         </registers>
 185     </module>
 186     <module class="PORTC">
 187       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 188           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0x01"/>
 189           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0x01"/>
 190         </registers>
 191     </module>
 192     <module class="PORTA">
 193       <registers name="PORTA" memspace="DATAMEM" text="" icon="io_port.bmp">
 194           <reg size="1" name="PORTA" offset="0x22" text="Port A Data Register" icon="io_port.bmp" mask="0x03"/>
 195           <reg size="1" name="DDRA" offset="0x21" text="Port A Data Direction Register" icon="io_flag.bmp" mask="0x03"/>
 196           <reg size="1" name="PINA" offset="0x20" text="Port A Input Pins" icon="io_port.bmp" mask="0x03"/>
 197         </registers>
 198     </module>
 199     <module class="FET">
 200       <registers name="FET" memspace="DATAMEM" text="" icon="io_analo.bmp">
 201           <reg size="1" name="FCSR" offset="0xF0" text="FET Control and Status Register" icon="io_analo.bmp">
 202             <bitfield name="DUVRD" mask="0x08" text="Deep Under-Voltage Recovery Disable" icon=""/>
 203             <bitfield name="CPS" mask="0x04" text="Current Protection Status" icon=""/>
 204             <bitfield name="DFE" mask="0x02" text="Discharge FET Enable" icon=""/>
 205             <bitfield name="CFE" mask="0x01" text="Charge FET Enable" icon=""/>
 206           </reg>
 207         </registers>
 208     </module>
 209     <module class="SPI">
 210       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 211           <reg size="1" name="SPCR" offset="0x4c" text="SPI Control Register" icon="io_flag.bmp">
 212             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 213             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 214             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 215             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 216             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 217             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 218             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 219           </reg>
 220           <reg size="1" name="SPSR" offset="0x4d" text="SPI Status Register" icon="io_flag.bmp">
 221             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 222             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 223             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 224           </reg>
 225           <reg size="1" name="SPDR" offset="0x4e" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 226         </registers>
 227     </module>
 228     <module class="BOOT_LOAD">
 229       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 230           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control and Status Register" icon="io_flag.bmp">
 231             <bitfield name="SIGRD" mask="0x20" text="Signature Row Read" icon=""/>
 232             <bitfield name="CTPB" mask="0x10" text="Clear Temporary Page Buffer" icon=""/>
 233             <bitfield name="RFLB" mask="0x08" text="Read Fuse and Lock Bits" icon=""/>
 234             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 235             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 236             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 237           </reg>
 238         </registers>
 239     </module>
 240     <module class="PORTB">
 241       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 242           <reg size="1" name="PORTB" offset="0x25" text="Data Register, Port B" icon="io_port.bmp" mask="0x0F"/>
 243           <reg size="1" name="DDRB" offset="0x24" text="Data Direction Register, Port B" icon="io_flag.bmp" mask="0x0F"/>
 244           <reg size="1" name="PINB" offset="0x23" text="Input Pins, Port B" icon="io_port.bmp" mask="0x0F"/>
 245         </registers>
 246     </module>
 247     <module class="CPU">
 248       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 249           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 250             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 251             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 252             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 253             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 254             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 255             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 256             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 257             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 258           </reg>
 259           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0x03FF"/>
 260           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 261             <bitfield name="CKOE" mask="0x20" text="Clock Output Enable" icon=""/>
 262             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 263           </reg>
 264           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 265             <bitfield name="OCDRF" mask="0x10" text="OCD Reset Flag" icon=""/>
 266             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 267             <bitfield name="BODRF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 268             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 269             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 270           </reg>
 271           <reg size="1" name="FOSCCAL" offset="0x66" text="Fast Oscillator Calibration Value" icon="io_cpu.bmp" mask="0xFF"/>
 272           <reg size="1" name="OSICSR" offset="0x37" text="Oscillator Sampling Interface Control and Status Register" icon="io_cpu.bmp">
 273             <bitfield name="OSISEL0" mask="0x10" text="Oscillator Sampling Interface Select 0" icon=""/>
 274             <bitfield name="OSIST" mask="0x02" text="Oscillator Sampling Interface Status" icon=""/>
 275             <bitfield name="OSIEN" mask="0x01" text="Oscillator Sampling Interface Enable" icon=""/>
 276           </reg>
 277           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 278             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon=""/>
 279             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 280           </reg>
 281           <reg size="1" name="GPIOR2" offset="0x4B" text="General Purpose IO Register 2" icon="io_cpu.bmp" mask="0xFF"/>
 282           <reg size="1" name="GPIOR1" offset="0x4A" text="General Purpose IO Register 1" icon="io_cpu.bmp" mask="0xFF"/>
 283           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp" mask="0xFF"/>
 284           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register" icon="io_cpu.bmp">
 285             <bitfield name="PA1DID" mask="0x02" text="When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled." icon=""/>
 286             <bitfield name="PA0DID" mask="0x01" text="When this bit is written logic one, the digital input buffer of the corresponding V_ADC pin is disabled." icon=""/>
 287           </reg>
 288           <reg size="1" name="PRR0" offset="0x64" text="Power Reduction Register 0" icon="io_cpu.bmp">
 289             <bitfield name="PRVRM" mask="0x20" text="Power Reduction Voltage Regulator Monitor" icon=""/>
 290             <bitfield name="PRSPI" mask="0x08" text="Power reduction SPI" icon=""/>
 291             <bitfield name="PRTIM1" mask="0x04" text="Power Reduction Timer/Counter1" icon=""/>
 292             <bitfield name="PRTIM0" mask="0x02" text="Power Reduction Timer/Counter0" icon=""/>
 293             <bitfield name="PRVADC" mask="0x01" text="Power Reduction V-ADC" icon=""/>
 294           </reg>
 295           <reg size="1" name="CLKPR" offset="0x61" text="Clock Prescale Register" icon="io_cpu.bmp">
 296             <bitfield name="CLKPCE" mask="0x80" text="Clock Prescaler Change Enable" icon=""/>
 297             <bitfield name="CLKPS" mask="0x03" text="Clock Prescaler Select Bits" icon=""/>
 298           </reg>
 299         </registers>
 300     </module>
 301     <module class="BATTERY_PROTECTION">
 302       <registers name="BATTERY_PROTECTION" memspace="DATAMEM" text="" icon="io_analo.bmp">
 303           <reg size="1" name="BPPLR" offset="0xFE" text="Battery Protection Parameter Lock Register" icon="io_analo.bmp">
 304             <bitfield name="BPPLE" mask="0x02" text="Battery Protection Parameter Lock Enable" icon=""/>
 305             <bitfield name="BPPL" mask="0x01" text="Battery Protection Parameter Lock" icon=""/>
 306           </reg>
 307           <reg size="1" name="BPCR" offset="0xFD" text="Battery Protection Control Register" icon="io_analo.bmp">
 308             <bitfield name="SCD" mask="0x10" text="Short Circuit Protection Disabled" icon=""/>
 309             <bitfield name="DOCD" mask="0x08" text="Discharge Over-current Protection Disabled" icon=""/>
 310             <bitfield name="COCD" mask="0x04" text="Charge Over-current Protection Disabled" icon=""/>
 311             <bitfield name="DHCD" mask="0x02" text="Discharge High-current Protection Disable" icon=""/>
 312             <bitfield name="CHCD" mask="0x01" text="Charge High-current Protection Disable" icon=""/>
 313           </reg>
 314           <reg size="1" name="BPHCTR" offset="0xFC" text="Battery Protection Short-current Timing Register" icon="io_analo.bmp" mask="0x3F"/>
 315           <reg size="1" name="BPOCTR" offset="0xFB" text="Battery Protection Over-current Timing Register" icon="io_analo.bmp" mask="0x3F"/>
 316           <reg size="1" name="BPSCTR" offset="0xFA" text="Battery Protection Short-current Timing Register" icon="io_analo.bmp" mask="0x7F"/>
 317           <reg size="1" name="BPCHCD" offset="0xF9" text="Battery Protection Charge-High-current Detection Level Register" icon="io_analo.bmp" mask="0xFF"/>
 318           <reg size="1" name="BPDHCD" offset="0xF8" text="Battery Protection Discharge-High-current Detection Level Register" icon="io_analo.bmp" mask="0xFF"/>
 319           <reg size="1" name="BPCOCD" offset="0xF7" text="Battery Protection Charge-Over-current Detection Level Register" icon="io_analo.bmp" mask="0xFF"/>
 320           <reg size="1" name="BPDOCD" offset="0xF6" text="Battery Protection Discharge-Over-current Detection Level Register" icon="io_analo.bmp" mask="0xFF"/>
 321           <reg size="1" name="BPSCD" offset="0xF5" text="Battery Protection Short-Circuit Detection Level Register" icon="io_analo.bmp" mask="0xFF"/>
 322           <reg size="1" name="BPIFR" offset="0xF3" text="Battery Protection Interrupt Flag Register" icon="io_analo.bmp">
 323             <bitfield name="SCIF" mask="0x10" text="Short-circuit Protection Activated Interrupt Flag" icon=""/>
 324             <bitfield name="DOCIF" mask="0x08" text="Discharge Over-current Protection Activated Interrupt Flag" icon=""/>
 325             <bitfield name="COCIF" mask="0x04" text="Charge Over-current Protection Activated Interrupt Flag" icon=""/>
 326             <bitfield name="DHCIF" mask="0x02" text="Disharge High-current Protection Activated Interrupt" icon=""/>
 327             <bitfield name="CHCIF" mask="0x01" text="Charge High-current Protection Activated Interrupt" icon=""/>
 328           </reg>
 329           <reg size="1" name="BPIMSK" offset="0xF2" text="Battery Protection Interrupt Mask Register" icon="io_analo.bmp">
 330             <bitfield name="SCIE" mask="0x10" text="Short-circuit Protection Activated Interrupt Enable" icon=""/>
 331             <bitfield name="DOCIE" mask="0x08" text="Discharge Over-current Protection Activated Interrupt Enable" icon=""/>
 332             <bitfield name="COCIE" mask="0x04" text="Charge Over-current Protection Activated Interrupt Enable" icon=""/>
 333             <bitfield name="DHCIE" mask="0x02" text="Discharger High-current Protection Activated Interrupt" icon=""/>
 334             <bitfield name="CHCIE" mask="0x01" text="Charger High-current Protection Activated Interrupt" icon=""/>
 335           </reg>
 336         </registers>
 337     </module>
 338     <module class="EEPROM">
 339       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 340           <reg size="1" name="EEAR" offset="0x41" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0xFF"/>
 341           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 342           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 343             <bitfield name="EEPM" mask="0x30" text="" icon="" enum="EEP_MODE"/>
 344             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 345             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 346             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 347             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 348           </reg>
 349         </registers>
 350     </module>
 351     <module class="TIMER_COUNTER_1">
 352       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 353           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 354             <bitfield name="CS" mask="0x07" text="Clock Select1 bis" icon="" lsb="10"/>
 355           </reg>
 356           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter 1 Control Register A" icon="io_flag.bmp">
 357             <bitfield name="TCW1" mask="0x80" text="Timer/Counter Width" icon=""/>
 358             <bitfield name="ICEN1" mask="0x40" text="Input Capture Mode Enable" icon=""/>
 359             <bitfield name="ICNC1" mask="0x20" text="Input Capture Noise Canceler" icon=""/>
 360             <bitfield name="ICES1" mask="0x10" text="Input Capture Edge Select" icon=""/>
 361             <bitfield name="ICS1" mask="0x08" text="Input Capture Select" icon=""/>
 362             <bitfield name="WGM10" mask="0x01" text="Waveform Generation Mode" icon=""/>
 363           </reg>
 364           <reg size="2" name="TCNT1" offset="0x84" text="Timer Counter 1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 365           <reg size="1" name="OCR1A" offset="0x88" text="Output Compare Register 1A" icon="io_timer.bmp" mask="0xFF"/>
 366           <reg size="1" name="OCR1B" offset="0x89" text="Output Compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 367           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 368             <bitfield name="ICIE1" mask="0x08" text="Timer/Counter n Input Capture Interrupt Enable" icon=""/>
 369             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output Compare B Interrupt Enable" icon=""/>
 370             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output Compare A Interrupt Enable" icon=""/>
 371             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 372           </reg>
 373           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 374             <bitfield name="ICF1" mask="0x08" text="Timer/Counter 1 Input Capture Flag" icon=""/>
 375             <bitfield name="OCF1B" mask="0x04" text="Timer/Counter1 Output Compare Flag B" icon=""/>
 376             <bitfield name="OCF1A" mask="0x02" text="Timer/Counter1 Output Compare Flag A" icon=""/>
 377             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 378           </reg>
 379           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 380             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 381             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset" icon=""/>
 382           </reg>
 383         </registers>
 384     </module>
 385     <module class="COULOMB_COUNTER">
 386       <registers name="COULOMB_COUNTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 387           <reg size="1" name="CADCSRA" offset="0xE4" text="CC-ADC Control and Status Register A" icon="io_analo.bmp">
 388             <bitfield name="CADEN" mask="0x80" text="When the CADEN bit is cleared (zero), the CC-ADC is disabled. When the CADEN bit is set (one), the CC-ADC will continuously measure the voltage drop over the external sense resistor RSENSE. In Power-down, only the Regular Current detection is active. In Power-off, the CC-ADC is always disabled." icon=""/>
 389             <bitfield name="CADPOL" mask="0x40" text="" icon=""/>
 390             <bitfield name="CADUB" mask="0x20" text="CC_ADC Update Busy" icon=""/>
 391             <bitfield name="CADAS" mask="0x18" text="CC_ADC Accumulate Current Select Bits" icon=""/>
 392             <bitfield name="CADSI" mask="0x06" text="The CADSI bits determine the current sampling interval for the Regular Current detection in Power-down mode. The actual settings remain to be determined." icon=""/>
 393             <bitfield name="CADSE" mask="0x01" text="When the CADSE bit is written to one, the ongoing CC-ADC conversion is aborted, and the CC-ADC enters Regular Current detection mode." icon=""/>
 394           </reg>
 395           <reg size="1" name="CADCSRB" offset="0xE5" text="CC-ADC Control and Status Register B" icon="io_analo.bmp">
 396             <bitfield name="CADACIE" mask="0x40" text="" icon=""/>
 397             <bitfield name="CADRCIE" mask="0x20" text="Regular Current Interrupt Enable" icon=""/>
 398             <bitfield name="CADICIE" mask="0x10" text="CAD Instantenous Current Interrupt Enable" icon=""/>
 399             <bitfield name="CADACIF" mask="0x04" text="CC-ADC Accumulate Current Interrupt Flag" icon=""/>
 400             <bitfield name="CADRCIF" mask="0x02" text="CC-ADC Accumulate Current Interrupt Flag" icon=""/>
 401             <bitfield name="CADICIF" mask="0x01" text="CC-ADC Instantaneous Current Interrupt Flag" icon=""/>
 402           </reg>
 403           <reg size="2" name="CADIC" offset="0xE8" text="CC-ADC Instantaneous Current" icon="io_analo.bmp" mask="0xFFFF"/>
 404           <reg size="1" name="CADAC3" offset="0xE3" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 405           <reg size="1" name="CADAC2" offset="0xE2" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 406           <reg size="1" name="CADAC1" offset="0xE1" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 407           <reg size="1" name="CADAC0" offset="0xE0" text="ADC Accumulate Current" icon="io_analo.bmp" mask="0xFF"/>
 408           <reg size="1" name="CADRC" offset="0xE6" text="CC-ADC Regular Current" icon="io_analo.bmp" mask="0xFF"/>
 409         </registers>
 410     </module>
 411     <module class="TIMER_COUNTER_0">
 412       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 413           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 414             <bitfield name="TCW0" mask="0x80" text="Timer/Counter Width" icon=""/>
 415             <bitfield name="ICEN0" mask="0x40" text="Input Capture Mode Enable" icon=""/>
 416             <bitfield name="ICNC0" mask="0x20" text="Input Capture Noise Canceler" icon=""/>
 417             <bitfield name="ICES0" mask="0x10" text="Input Capture Edge Select" icon=""/>
 418             <bitfield name="ICS0" mask="0x08" text="Input Capture Select" icon=""/>
 419             <bitfield name="WGM00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
 420           </reg>
 421           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter0 Control Register" icon="io_flag.bmp">
 422             <bitfield name="CS02" mask="0x04" text="Clock Select0 bit 2" icon=""/>
 423             <bitfield name="CS01" mask="0x02" text="Clock Select0 bit 1" icon=""/>
 424             <bitfield name="CS00" mask="0x01" text="Clock Select0 bit 0" icon=""/>
 425           </reg>
 426           <reg size="2" name="TCNT0" offset="0x46" text="Timer Counter 0  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 427           <reg size="1" name="OCR0A" offset="0x48" text="Output compare Register A" icon="io_timer.bmp" mask="0xFF"/>
 428           <reg size="1" name="OCR0B" offset="0x49" text="Output compare Register B" icon="io_timer.bmp" mask="0xFF"/>
 429           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 430             <bitfield name="ICIE0" mask="0x08" text="Timer/Counter n Input Capture Interrupt Enable" icon=""/>
 431             <bitfield name="OCIE0B" mask="0x04" text="Output Compare Interrupt Enable" icon=""/>
 432             <bitfield name="OCIE0A" mask="0x02" text="Output Compare Interrupt Enable" icon=""/>
 433             <bitfield name="TOIE0" mask="0x01" text="Overflow Interrupt Enable" icon=""/>
 434           </reg>
 435           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 436             <bitfield name="ICF0" mask="0x08" text="Timer/Counter Interrupt Flag Register" icon=""/>
 437             <bitfield name="OCF0B" mask="0x04" text="Output Compare Flag" icon=""/>
 438             <bitfield name="OCF0A" mask="0x02" text="Output Compare Flag" icon=""/>
 439             <bitfield name="TOV0" mask="0x01" text="Overflow Flag" icon=""/>
 440           </reg>
 441         </registers>
 442     </module>
 443     <module class="VOLTAGE_REGULATOR">
 444       <registers name="VOLTAGE_REGULATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 445           <reg size="1" name="ROCR" offset="0xC8" text="Regulator Operating Condition Register" icon="io_analo.bmp">
 446             <bitfield name="ROCS" mask="0x80" text="ROC Status" icon=""/>
 447             <bitfield name="ROCWIF" mask="0x02" text="ROC Warning Interrupt Flag" icon=""/>
 448             <bitfield name="ROCWIE" mask="0x01" text="ROC Warning Interrupt Enable" icon=""/>
 449           </reg>
 450         </registers>
 451     </module>
 452   </hardware>
 453 </device>