devices/atmega32m1

   1 <?xml version="1.0"?>
   2 <!DOCTYPE device SYSTEM "device.dtd">
   3 <device>
   4   <memory>
   5     <flash size="32768"/>
   6     <iospace start="$0020" stop="$00FF"/>
   7     <sram size="2048"/>
   8     <eram size="2048"/>
   9   </memory>
  10   <ioregisters>
  11     <ioreg name="PINB" address="$03"/>
  12     <ioreg name="DDRB" address="$04"/>
  13     <ioreg name="PORTB" address="$05"/>
  14     <ioreg name="PINC" address="$06"/>
  15     <ioreg name="DDRC" address="$07"/>
  16     <ioreg name="PORTC" address="$08"/>
  17     <ioreg name="PIND" address="$09"/>
  18     <ioreg name="DDRD" address="$0A"/>
  19     <ioreg name="PORTD" address="$0B"/>
  20     <ioreg name="PINE" address="$0C"/>
  21     <ioreg name="DDRE" address="$0D"/>
  22     <ioreg name="PORTE" address="$0E"/>
  23     <ioreg name="TIFR0" address="$15"/>
  24     <ioreg name="TIFR1" address="$16"/>
  25     <ioreg name="GPIOR1" address="$19"/>
  26     <ioreg name="GPIOR2" address="$1A"/>
  27     <ioreg name="PCIFR" address="$1B"/>
  28     <ioreg name="EIFR" address="$1C"/>
  29     <ioreg name="EIMSK" address="$1D"/>
  30     <ioreg name="GPIOR0" address="$1E"/>
  31     <ioreg name="EECR" address="$1F"/>
  32     <ioreg name="EEDR" address="$20"/>
  33     <ioreg name="EEARL" address="$21"/>
  34     <ioreg name="EEARH" address="$22"/>
  35     <ioreg name="GTCCR" address="$23"/>
  36     <ioreg name="TCCR0A" address="$24"/>
  37     <ioreg name="TCCR0B" address="$25"/>
  38     <ioreg name="TCNT0" address="$26"/>
  39     <ioreg name="OCR0A" address="$27"/>
  40     <ioreg name="OCR0B" address="$28"/>
  41     <ioreg name="PLLCSR" address="$29"/>
  42     <ioreg name="SPCR" address="$2C"/>
  43     <ioreg name="SPSR" address="$2D"/>
  44     <ioreg name="SPDR" address="$2E"/>
  45     <ioreg name="ACSR" address="$30"/>
  46     <ioreg name="DWDR" address="$31"/>
  47     <ioreg name="SMCR" address="$33"/>
  48     <ioreg name="MCUSR" address="$34"/>
  49     <ioreg name="MCUCR" address="$35"/>
  50     <ioreg name="SPMCSR" address="$37"/>
  51     <ioreg name="SPL" address="$3D"/>
  52     <ioreg name="SPH" address="$3E"/>
  53     <ioreg name="SREG" address="$3F"/>
  54     <ioreg name="WDTCSR" address="$60"/>
  55     <ioreg name="CLKPR" address="$61"/>
  56     <ioreg name="PRR" address="$64"/>
  57     <ioreg name="OSCCAL" address="$66"/>
  58     <ioreg name="EICRA" address="$69"/>
  59     <ioreg name="PCMSK0" address="$6A"/>
  60     <ioreg name="PCMSK1" address="$6B"/>
  61     <ioreg name="PCMSK2" address="$6C"/>
  62     <ioreg name="PCMSK3" address="$6D"/>
  63     <ioreg name="TIMSK0" address="$6E"/>
  64     <ioreg name="TIMSK1" address="$6F"/>
  65     <ioreg name="AMP0CSR" address="$75"/>
  66     <ioreg name="AMP1CSR" address="$76"/>
  67     <ioreg name="AMP2CSR" address="$77"/>
  68     <ioreg name="ADCL" address="$78"/>
  69     <ioreg name="ADCH" address="$79"/>
  70     <ioreg name="ADCSRA" address="$7A"/>
  71     <ioreg name="ADCSRB" address="$7B"/>
  72     <ioreg name="ADMUX" address="$7C"/>
  73     <ioreg name="DIDR0" address="$7E"/>
  74     <ioreg name="DIDR1" address="$7F"/>
  75     <ioreg name="TCCR1A" address="$80"/>
  76     <ioreg name="TCCR1B" address="$81"/>
  77     <ioreg name="TCCR1C" address="$82"/>
  78     <ioreg name="TCNT1L" address="$84"/>
  79     <ioreg name="TCNT1H" address="$85"/>
  80     <ioreg name="ICR1L" address="$86"/>
  81     <ioreg name="ICR1H" address="$87"/>
  82     <ioreg name="OCR1AL" address="$88"/>
  83     <ioreg name="OCR1AH" address="$89"/>
  84     <ioreg name="OCR1BL" address="$8A"/>
  85     <ioreg name="OCR1BH" address="$8B"/>
  86     <ioreg name="DACON" address="$90"/>
  87     <ioreg name="DACL" address="$91"/>
  88     <ioreg name="DACH" address="$92"/>
  89     <ioreg name="AC0CON" address="$94"/>
  90     <ioreg name="AC1CON" address="$95"/>
  91     <ioreg name="AC2CON" address="$96"/>
  92     <ioreg name="AC3CON" address="$97"/>
  93     <ioreg name="POCR0SAL" address="$A0"/>
  94     <ioreg name="POCR0SAH" address="$A1"/>
  95     <ioreg name="POCR0RAL" address="$A2"/>
  96     <ioreg name="POCR0RAH" address="$A3"/>
  97     <ioreg name="POCR0SBL" address="$A4"/>
  98     <ioreg name="POCR0SBH" address="$A5"/>
  99     <ioreg name="POCR1SAL" address="$A6"/>
 100     <ioreg name="POCR1SAH" address="$A7"/>
 101     <ioreg name="POCR1RAL" address="$A8"/>
 102     <ioreg name="POCR1RAH" address="$A9"/>
 103     <ioreg name="POCR1SBL" address="$AA"/>
 104     <ioreg name="POCR1SBH" address="$AB"/>
 105     <ioreg name="POCR2SAL" address="$AC"/>
 106     <ioreg name="POCR2SAH" address="$AD"/>
 107     <ioreg name="POCR2RAL" address="$AE"/>
 108     <ioreg name="POCR2RAH" address="$AF"/>
 109     <ioreg name="POCR2SBL" address="$B0"/>
 110     <ioreg name="POCR2SBH" address="$B1"/>
 111     <ioreg name="POCR_RBL" address="$B2"/>
 112     <ioreg name="POCR_RBH" address="$B3"/>
 113     <ioreg name="PSYNC" address="$B4"/>
 114     <ioreg name="PCNF" address="$B5"/>
 115     <ioreg name="POC" address="$B6"/>
 116     <ioreg name="PCTL" address="$B7"/>
 117     <ioreg name="PMIC0" address="$B8"/>
 118     <ioreg name="PMIC1" address="$B9"/>
 119     <ioreg name="PMIC2" address="$BA"/>
 120     <ioreg name="PIM" address="$BB"/>
 121     <ioreg name="PIFR" address="$BC"/>
 122     <ioreg name="CANPAGE" address="$ED"/>
 123     <ioreg name="CANSTMOB" address="$EE"/>
 124     <ioreg name="CANCDMOB" address="$EF"/>
 125     <ioreg name="CANIDT4" address="$F0"/>
 126     <ioreg name="CANIDT3" address="$F1"/>
 127     <ioreg name="CANIDT2" address="$F2"/>
 128     <ioreg name="CANIDT1" address="$F3"/>
 129     <ioreg name="CANIDM4" address="$F4"/>
 130     <ioreg name="CANIDM3" address="$F5"/>
 131     <ioreg name="CANIDM2" address="$F6"/>
 132     <ioreg name="CANIDM1" address="$F7"/>
 133     <ioreg name="CANSTML" address="$F8"/>
 134     <ioreg name="CANSTMH" address="$F9"/>
 135     <ioreg name="CANMSG" address="$FA"/>
 136     <ioreg name="LINCR" address="0xC8"/>
 137     <ioreg name="LINSIR" address="0xC9"/>
 138     <ioreg name="LINENIR" address="0xCA"/>
 139     <ioreg name="LINERR" address="0xCB"/>
 140     <ioreg name="LINBTR" address="0xCC"/>
 141     <ioreg name="LINBRRL" address="0xCD"/>
 142     <ioreg name="LINBRRH" address="0xCE"/>
 143     <ioreg name="LINDLR" address="0xCF"/>
 144     <ioreg name="LINIDR" address="0xD0"/>
 145     <ioreg name="LINSEL" address="0xD1"/>
 146     <ioreg name="LINDAT" address="0xD2"/>
 147     <ioreg name="CANGCON" address="0xD8"/>
 148     <ioreg name="CANGSTA" address="0xD9"/>
 149     <ioreg name="CANGIT" address="0xDA"/>
 150     <ioreg name="CANGIE" address="0xDB"/>
 151     <ioreg name="CANEN2" address="0xDC"/>
 152     <ioreg name="CANEN1" address="0xDD"/>
 153     <ioreg name="CANIE2" address="0xDE"/>
 154     <ioreg name="CANIE1" address="0xDF"/>
 155     <ioreg name="CANSIT2" address="0xE0"/>
 156     <ioreg name="CANSIT1" address="0xE1"/>
 157     <ioreg name="CANBT1" address="0xE2"/>
 158     <ioreg name="CANBT2" address="0xE3"/>
 159     <ioreg name="CANBT3" address="0xE4"/>
 160     <ioreg name="CANTCON" address="0xE5"/>
 161     <ioreg name="CANTIML" address="0xE6"/>
 162     <ioreg name="CANTIMH" address="0xE7"/>
 163     <ioreg name="CANTTCL" address="0xE8"/>
 164     <ioreg name="CANTTCH" address="0xE9"/>
 165     <ioreg name="CANTEC" address="0xEA"/>
 166     <ioreg name="CANREC" address="0xEB"/>
 167     <ioreg name="CANHPMOB" address="0xEC"/>
 168   </ioregisters>
 169   <interrupts num="31">
 170     <interrupt vector="1" address="$0000" name="RESET">External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset and JTAG AVR Reset</interrupt>
 171     <interrupt vector="2" address="$0002" name="ANACOMP0">Analog Comparator 0</interrupt>
 172     <interrupt vector="3" address="$0004" name="ANACOMP1">Analog Comparator 1</interrupt>
 173     <interrupt vector="4" address="$0006" name="ANACOMP2">Analog Comparator 2</interrupt>
 174     <interrupt vector="5" address="$0008" name="ANACOMP3">Analog Comparator 3</interrupt>
 175     <interrupt vector="6" address="$000A" name="PSC FAULT">PSC Fault</interrupt>
 176     <interrupt vector="7" address="$000C" name="PSC EC">PSC End of Cycle</interrupt>
 177     <interrupt vector="8" address="$000E" name="INT0">External Interrupt Request 0</interrupt>
 178     <interrupt vector="9" address="$0010" name="INT1">External Interrupt Request 1</interrupt>
 179     <interrupt vector="10" address="$0012" name="INT2">External Interrupt Request 2</interrupt>
 180     <interrupt vector="11" address="$0014" name="INT3">External Interrupt Request 3</interrupt>
 181     <interrupt vector="12" address="$0016" name="TIMER1 CAPT">Timer/Counter1 Capture Event</interrupt>
 182     <interrupt vector="13" address="$0018" name="TIMER1 COMPA">Timer/Counter1 Compare Match A</interrupt>
 183     <interrupt vector="14" address="$001A" name="TIMER1 COMPB">Timer/Counter1 Compare Match B</interrupt>
 184     <interrupt vector="15" address="$001C" name="TIMER1 OVF">Timer1/Counter1 Overflow</interrupt>
 185     <interrupt vector="16" address="$001E" name="TIMER0 COMPA">Timer/Counter0 Compare Match A</interrupt>
 186     <interrupt vector="17" address="$0020" name="TIMER0 COMPB">Timer/Counter0 Compare Match B</interrupt>
 187     <interrupt vector="18" address="$0022" name="TIMER0 OVF">Timer/Counter0 Overflow</interrupt>
 188     <interrupt vector="19" address="$0024" name="CAN INT">CAN MOB, Burst, General Errors</interrupt>
 189     <interrupt vector="20" address="$0026" name="CAN TOVF">CAN Timer Overflow</interrupt>
 190     <interrupt vector="21" address="$0028" name="LIN TC">LIN Transfer Complete</interrupt>
 191     <interrupt vector="22" address="$002A" name="LIN ERR">LIN Error</interrupt>
 192     <interrupt vector="23" address="$002C" name="PCINT0">Pin Change Interrupt Request 0</interrupt>
 193     <interrupt vector="24" address="$002E" name="PCINT1">Pin Change Interrupt Request 1</interrupt>
 194     <interrupt vector="25" address="$0030" name="PCINT2">Pin Change Interrupt Request 2</interrupt>
 195     <interrupt vector="26" address="$0032" name="PCINT3">Pin Change Interrupt Request 3</interrupt>
 196     <interrupt vector="27" address="$0034" name="SPI, STC">SPI Serial Transfer Complete</interrupt>
 197     <interrupt vector="28" address="$0036" name="ADC">ADC Conversion Complete</interrupt>
 198     <interrupt vector="29" address="$0038" name="WDT">Watchdog Time-Out Interrupt</interrupt>
 199     <interrupt vector="30" address="$003A" name="EE READY">EEPROM Ready</interrupt>
 200     <interrupt vector="31" address="$003C" name="SPM READY">Store Program Memory Read</interrupt>
 201   </interrupts>
 202   <packages>
 203     <package name="TQFP" pins="32">
 204       <pin id="1" name="[PD2:PSCIN2:OC1A:MISO_A:PCINT18]"/>
 205       <pin id="2" name="[PD3:TXD:TXLIN:OC0A:SS:MOSI_A:PCINT19]"/>
 206       <pin id="3" name="[PC1:PSCIN1:OC1B:SS_A:PCINT9]"/>
 207       <pin id="4" name="[VCC]"/>
 208       <pin id="5" name="[GND]"/>
 209       <pin id="6" name="[PC2:T0:TXCAN:PCINT10]"/>
 210       <pin id="7" name="[PC3:T1:RXCAN:ICP1B:PCINT11]"/>
 211       <pin id="8" name="[PB0:MISO:PSCOUT2A:PCINT0]"/>
 212       <pin id="9" name="[PB1:MOSI:PSCOUT2B:PCINT1]"/>
 213       <pin id="10" name="[PE1:OC0B:XTAL1:PCINT25]"/>
 214       <pin id="11" name="[PE2:ADC0:XTAL2:PCINT26]"/>
 215       <pin id="12" name="[PD4:ADC1:RXD:RXLIN:ICP1A:SCK_A:PCINT20]"/>
 216       <pin id="13" name="[PD5:ADC2:ACMP2:PCINT21]"/>
 217       <pin id="14" name="[PD6:ADC3:ACMPN2:INT0:PCINT22]"/>
 218       <pin id="15" name="[PD7:ACMP0:PCINT23]"/>
 219       <pin id="16" name="[PB2:ADC5:INT1:ACMPN0:PCINT2]"/>
 220       <pin id="17" name="[PC4:ADC8:AMP1-:ACMPN3:PCINT12]"/>
 221       <pin id="18" name="[PC5:ADC9:AMP1+:ACMP3:PCINT13]"/>
 222       <pin id="19" name="[AVCC]"/>
 223       <pin id="20" name="[AGND]"/>
 224       <pin id="21" name="[AREF]"/>
 225       <pin id="22" name="[PC6:ADC10:ACMP1:PCINT14]"/>
 226       <pin id="23" name="[PB3:AMP0-:PCINT3]"/>
 227       <pin id="24" name="[PB4:AMP0+:PCINT4]"/>
 228       <pin id="25" name="[PC7:D2A:AMP2+:PCINT15]"/>
 229       <pin id="26" name="[PB5:ADC6:INT2:ACMPN1:AMP2-:PCINT5]"/>
 230       <pin id="27" name="[PB6:ADC7:PSCOUT1B:PCINT6]"/>
 231       <pin id="28" name="[PB7:ADC4:PSCOUT0B:SCK:PCINT7]"/>
 232       <pin id="29" name="[PD0:PSCOUT0A:PCINT16]"/>
 233       <pin id="30" name="[PC0:INT3:PSCOUT1A:PCINT8]"/>
 234       <pin id="31" name="[PE0:RESET:OCD:PCINT24]"/>
 235       <pin id="32" name="[PD1:PSCIN0:CLK0:PCINT17]"/>
 236     </package>
 237   </packages>
 238   <hardware>
 239 <!--Everything after this needs editing!!!-->
 240     <module class="FUSE">
 241       <registers name="FUSE" memspace="FUSE">
 242           <reg size="1" name="EXTENDED" offset="0x02">
 243             <bitfield name="PSCRB" mask="0x20" text="PSC Reset Behavior" icon=""/>
 244             <bitfield name="PSCRVA" mask="0x10" text="PSCOUTnA Reset Value" icon=""/>
 245             <bitfield name="PSCRVB" mask="0x08" text="PSC0UTnB Reset Value" icon=""/>
 246             <bitfield name="BODLEVEL" mask="0x07" text="Brown-out Detector Trigger Level" icon="" enum="ENUM_BODLEVEL"/>
 247           </reg>
 248           <reg size="1" name="HIGH" offset="0x01">
 249             <bitfield name="RSTDISBL" mask="0x80" text="Reset Disabled (Enable PC6 as i/o pin)" icon=""/>
 250             <bitfield name="DWEN" mask="0x40" text="Debug Wire enable" icon=""/>
 251             <bitfield name="SPIEN" mask="0x20" text="Serial program downloading (SPI) enabled" icon=""/>
 252             <bitfield name="WDTON" mask="0x10" text="Watch-dog Timer always on" icon=""/>
 253             <bitfield name="EESAVE" mask="0x08" text="Preserve EEPROM through the Chip Erase cycle" icon=""/>
 254             <bitfield name="BOOTSZ" mask="0x06" text="Select Boot Size" icon="" enum="ENUM_BOOTSZ"/>
 255             <bitfield name="BOOTRST" mask="0x01" text="Select Reset Vector" icon=""/>
 256           </reg>
 257           <reg size="1" name="LOW" offset="0x00">
 258             <bitfield name="CKDIV8" mask="0x80" text="Divide clock by 8 internally" icon=""/>
 259             <bitfield name="CKOUT" mask="0x40" text="Clock output on PORTD1" icon=""/>
 260             <bitfield name="SUT_CKSEL" mask="0x3F" text="Select Clock Source" icon="" enum="ENUM_SUT_CKSEL"/>
 261           </reg>
 262         </registers>
 263     </module>
 264     <module class="LOCKBIT">
 265       <registers name="LOCKBIT" memspace="LOCKBIT">
 266           <reg size="1" name="LOCKBIT" offset="0x00">
 267             <bitfield name="LB" mask="0x03" text="Memory Lock" icon="" enum="ENUM_LB"/>
 268             <bitfield name="BLB0" mask="0x0C" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB"/>
 269             <bitfield name="BLB1" mask="0x30" text="Boot Loader Protection Mode" icon="" enum="ENUM_BLB2"/>
 270           </reg>
 271         </registers>
 272     </module>
 273     <module class="PORTB">
 274       <registers name="PORTB" memspace="DATAMEM" text="" icon="io_port.bmp">
 275           <reg size="1" name="PORTB" offset="0x25" text="Port B Data Register" icon="io_port.bmp" mask="0xFF"/>
 276           <reg size="1" name="DDRB" offset="0x24" text="Port B Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 277           <reg size="1" name="PINB" offset="0x23" text="Port B Input Pins" icon="io_port.bmp" mask="0xFF"/>
 278         </registers>
 279     </module>
 280     <module class="PORTC">
 281       <registers name="PORTC" memspace="DATAMEM" text="" icon="io_port.bmp">
 282           <reg size="1" name="PORTC" offset="0x28" text="Port C Data Register" icon="io_port.bmp" mask="0xFF"/>
 283           <reg size="1" name="DDRC" offset="0x27" text="Port C Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 284           <reg size="1" name="PINC" offset="0x26" text="Port C Input Pins" icon="io_port.bmp" mask="0xFF"/>
 285         </registers>
 286     </module>
 287     <module class="PORTD">
 288       <registers name="PORTD" memspace="DATAMEM" text="" icon="io_port.bmp">
 289           <reg size="1" name="PORTD" offset="0x2B" text="Port D Data Register" icon="io_port.bmp" mask="0xFF"/>
 290           <reg size="1" name="DDRD" offset="0x2A" text="Port D Data Direction Register" icon="io_flag.bmp" mask="0xFF"/>
 291           <reg size="1" name="PIND" offset="0x29" text="Port D Input Pins" icon="io_port.bmp" mask="0xFF"/>
 292         </registers>
 293     </module>
 294     <module class="BOOT_LOAD">
 295       <registers name="BOOT_LOAD" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 296           <reg size="1" name="SPMCSR" offset="0x57" text="Store Program Memory Control Register" icon="io_flag.bmp">
 297             <bitfield name="SPMIE" mask="0x80" text="SPM Interrupt Enable" icon=""/>
 298             <bitfield name="RWWSB" mask="0x40" text="Read While Write Section Busy" icon=""/>
 299             <bitfield name="RWWSRE" mask="0x10" text="Read While Write section read enable" icon=""/>
 300             <bitfield name="BLBSET" mask="0x08" text="Boot Lock Bit Set" icon=""/>
 301             <bitfield name="PGWRT" mask="0x04" text="Page Write" icon=""/>
 302             <bitfield name="PGERS" mask="0x02" text="Page Erase" icon=""/>
 303             <bitfield name="SPMEN" mask="0x01" text="Store Program Memory Enable" icon=""/>
 304           </reg>
 305         </registers>
 306     </module>
 307     <module class="CAN">
 308       <registers name="CAN" memspace="DATAMEM" text="" icon="io_com.bmp">
 309           <reg size="1" name="CANGCON" offset="0xD8" text="CAN General Control Register" icon="register.bmp">
 310             <bitfield name="ABRQ" mask="0x80" text="Abort Request" icon=""/>
 311             <bitfield name="OVRQ" mask="0x40" text="Overload Frame Request" icon=""/>
 312             <bitfield name="TTC" mask="0x20" text="Time Trigger Communication" icon=""/>
 313             <bitfield name="SYNTTC" mask="0x10" text="Synchronization of TTC" icon=""/>
 314             <bitfield name="LISTEN" mask="0x08" text="Listening Mode" icon=""/>
 315             <bitfield name="TEST" mask="0x04" text="Test Mode" icon=""/>
 316             <bitfield name="ENASTB" mask="0x02" text="Enable / Standby" icon=""/>
 317             <bitfield name="SWRES" mask="0x01" text="Software Reset Request" icon=""/>
 318           </reg>
 319           <reg size="1" name="CANGSTA" offset="0xD9" text="CAN General Status Register" icon="io_flag.bmp">
 320             <bitfield name="OVFG" mask="0x40" text="Overload Frame Flag" icon=""/>
 321             <bitfield name="TXBSY" mask="0x10" text="Transmitter Busy" icon=""/>
 322             <bitfield name="RXBSY" mask="0x08" text="Receiver Busy" icon=""/>
 323             <bitfield name="ENFG" mask="0x04" text="Enable Flag" icon=""/>
 324             <bitfield name="BOFF" mask="0x02" text="Bus Off Mode" icon=""/>
 325             <bitfield name="ERRP" mask="0x01" text="Error Passive Mode" icon=""/>
 326           </reg>
 327           <reg size="1" name="CANGIT" offset="0xDA" text="CAN General Interrupt Register Flags" icon="io_flag.bmp">
 328             <bitfield name="CANIT" mask="0x80" text="General Interrupt Flag" icon=""/>
 329             <bitfield name="BOFFIT" mask="0x40" text="Bus Off Interrupt Flag" icon=""/>
 330             <bitfield name="OVRTIM" mask="0x20" text="Overrun CAN Timer Flag" icon=""/>
 331             <bitfield name="BXOK" mask="0x10" text="Burst Receive Interrupt Flag" icon=""/>
 332             <bitfield name="SERG" mask="0x08" text="Stuff Error General Flag" icon=""/>
 333             <bitfield name="CERG" mask="0x04" text="CRC Error General Flag" icon=""/>
 334             <bitfield name="FERG" mask="0x02" text="Form Error General Flag" icon=""/>
 335             <bitfield name="AERG" mask="0x01" text="Ackknowledgement Error General Flag" icon=""/>
 336           </reg>
 337           <reg size="1" name="CANGIE" offset="0xDB" text="CAN General Interrupt Enable Register" icon="register.bmp">
 338             <bitfield name="ENIT" mask="0x80" text="Enable all Interrupts" icon=""/>
 339             <bitfield name="ENBOFF" mask="0x40" text="Enable Bus Off Interrupt" icon=""/>
 340             <bitfield name="ENRX" mask="0x20" text="Enable Receive Interrupt" icon=""/>
 341             <bitfield name="ENTX" mask="0x10" text="Enable Transmitt Interrupt" icon=""/>
 342             <bitfield name="ENERR" mask="0x08" text="Enable MOb Error Interrupt" icon=""/>
 343             <bitfield name="ENBX" mask="0x04" text="Enable Burst Receive Interrupt" icon=""/>
 344             <bitfield name="ENERG" mask="0x02" text="Enable General Error Interrupt" icon=""/>
 345             <bitfield name="ENOVRT" mask="0x01" text="Enable CAN Timer Overrun Interrupt" icon=""/>
 346           </reg>
 347           <reg size="1" name="CANEN2" offset="0xDC" text="Enable MOb Register 2" icon="register.bmp">
 348             <bitfield name="ENMOB" mask="0x3F" text="Enable MObs" icon=""/>
 349           </reg>
 350           <reg size="1" name="CANEN1" offset="0xDD" text="Enable MOb Register 1(empty)" icon="register.bmp" mask="0x00"/>
 351           <reg size="1" name="CANIE2" offset="0xDE" text="Enable Interrupt MOb Register 2" icon="register.bmp">
 352             <bitfield name="IEMOB" mask="0x3F" text="Interrupt Enable  MObs" icon=""/>
 353           </reg>
 354           <reg size="1" name="CANIE1" offset="0xDF" text="Enable Interrupt MOb Register 1 (empty)" icon="register.bmp" mask="0x00"/>
 355           <reg size="1" name="CANSIT2" offset="0xE0" text="CAN Status Interrupt MOb Register 2" icon="io_flag.bmp">
 356             <bitfield name="SIT" mask="0x3F" text="Status of Interrupt MObs" icon=""/>
 357           </reg>
 358           <reg size="1" name="CANSIT1" offset="0xE1" text="CAN Status Interrupt MOb Register 1 (empty)" icon="io_flag.bmp" mask="0x00"/>
 359           <reg size="1" name="CANBT1" offset="0xE2" text="CAN Bit Timing Register 1" icon="register.bmp">
 360             <bitfield name="BRP" mask="0x7E" text="Baud Rate Prescaler bits" icon=""/>
 361           </reg>
 362           <reg size="1" name="CANBT2" offset="0xE3" text="CAN Bit Timing Register 2" icon="register.bmp">
 363             <bitfield name="SJW" mask="0x60" text="Re-Sync Jump Width bits" icon=""/>
 364             <bitfield name="PRS" mask="0x0E" text="Propagation Time Segment bits" icon=""/>
 365           </reg>
 366           <reg size="1" name="CANBT3" offset="0xE4" text="CAN Bit Timing Register 3" icon="register.bmp">
 367             <bitfield name="PHS2" mask="0x70" text="Phase Segment 2 bits" icon=""/>
 368             <bitfield name="PHS1" mask="0x0E" text="Phase Segment 1 bits" icon=""/>
 369             <bitfield name="SMP" mask="0x01" text="Sample Type" icon=""/>
 370           </reg>
 371           <reg size="1" name="CANTCON" offset="0xE5" text="Timer Control Register" icon="register.bmp" mask="0x00"/>
 372           <reg size="1" name="CANTIML" offset="0xE6" text="Timer Register Low" icon="register.bmp" mask="0x00"/>
 373           <reg size="1" name="CANTIMH" offset="0xE7" text="Timer Register High" icon="register.bmp" mask="0x00"/>
 374           <reg size="1" name="CANTTCL" offset="0xE8" text="TTC Timer Register Low" icon="register.bmp" mask="0x00"/>
 375           <reg size="1" name="CANTTCH" offset="0xE9" text="TTC Timer Register High" icon="register.bmp" mask="0x00"/>
 376           <reg size="1" name="CANTEC" offset="0xEA" text="Transmit Error Counter Register" icon="register.bmp" mask="0x00"/>
 377           <reg size="1" name="CANREC" offset="0xEB" text="Receive Error Counter Register" icon="register.bmp" mask="0x00"/>
 378           <reg size="1" name="CANHPMOB" offset="0xEC" text="Highest Priority MOb Register" icon="register.bmp">
 379             <bitfield name="HPMOB" mask="0xF0" text="Highest Priority MOb Number bits" icon=""/>
 380             <bitfield name="CGP" mask="0x0F" text="CAN General Purpose bits" icon=""/>
 381           </reg>
 382           <reg size="1" name="CANPAGE" offset="0xED" text="Page MOb Register" icon="register.bmp">
 383             <bitfield name="MOBNB" mask="0xF0" text="MOb Number bits" icon=""/>
 384             <bitfield name="AINC" mask="0x08" text="MOb Data Buffer Auto Increment (Active Low)" icon=""/>
 385             <bitfield name="INDX" mask="0x07" text="Data Buffer Index bits" icon=""/>
 386           </reg>
 387           <reg size="1" name="CANSTMOB" offset="0xEE" text="MOb Status Register" icon="io_flag.bmp">
 388             <bitfield name="DLCW" mask="0x80" text="Data Length Code Warning on MOb" icon=""/>
 389             <bitfield name="TXOK" mask="0x40" text="Transmit OK on MOb" icon=""/>
 390             <bitfield name="RXOK" mask="0x20" text="Receive OK on MOb" icon=""/>
 391             <bitfield name="BERR" mask="0x10" text="Bit Error on MOb" icon=""/>
 392             <bitfield name="SERR" mask="0x08" text="Stuff Error on MOb" icon=""/>
 393             <bitfield name="CERR" mask="0x04" text="CRC Error on MOb" icon=""/>
 394             <bitfield name="FERR" mask="0x02" text="Form Error on MOb" icon=""/>
 395             <bitfield name="AERR" mask="0x01" text="Ackknowledgement Error on MOb" icon=""/>
 396           </reg>
 397           <reg size="1" name="CANCDMOB" offset="0xEF" text="MOb Control and DLC Register" icon="register.bmp">
 398             <bitfield name="CONMOB" mask="0xC0" text="MOb Config bits" icon=""/>
 399             <bitfield name="RPLV" mask="0x20" text="Reply Valid" icon=""/>
 400             <bitfield name="IDE" mask="0x10" text="Identifier Extension" icon=""/>
 401             <bitfield name="DLC" mask="0x0F" text="Data Length Code bits" icon=""/>
 402           </reg>
 403           <reg size="1" name="CANIDT4" offset="0xF0" text="Identifier Tag Register 4" icon="register.bmp">
 404             <bitfield name="IDT" mask="0xF8" text="" icon=""/>
 405             <bitfield name="RTRTAG" mask="0x04" text="" icon=""/>
 406             <bitfield name="RB1TAG" mask="0x02" text="" icon=""/>
 407             <bitfield name="RB0TAG" mask="0x01" text="" icon=""/>
 408           </reg>
 409           <reg size="1" name="CANIDT3" offset="0xF1" text="Identifier Tag Register 3" icon="register.bmp" mask="0xFF"/>
 410           <reg size="1" name="CANIDT2" offset="0xF2" text="Identifier Tag Register 2" icon="register.bmp" mask="0xFF"/>
 411           <reg size="1" name="CANIDT1" offset="0xF3" text="Identifier Tag Register 1" icon="register.bmp" mask="0xFF"/>
 412           <reg size="1" name="CANIDM4" offset="0xF4" text="Identifier Mask Register 4" icon="register.bmp" mask="0xFD"/>
 413           <reg size="1" name="CANIDM3" offset="0xF5" text="Identifier Mask Register 3" icon="register.bmp" mask="0xFF"/>
 414           <reg size="1" name="CANIDM2" offset="0xF6" text="Identifier Mask Register 2" icon="register.bmp" mask="0xFF"/>
 415           <reg size="1" name="CANIDM1" offset="0xF7" text="Identifier Mask Register 1" icon="register.bmp" mask="0xFF"/>
 416           <reg size="1" name="CANSTML" offset="0xF8" text="Time Stamp Register Low" icon="register.bmp" mask="0x00"/>
 417           <reg size="1" name="CANSTMH" offset="0xF9" text="Time Stamp Register High" icon="register.bmp" mask="0x00"/>
 418           <reg size="1" name="CANMSG" offset="0xFA" text="Message Data Register" icon="register.bmp" mask="0x00"/>
 419         </registers>
 420     </module>
 421     <module class="ANALOG_COMPARATOR">
 422       <registers name="ANALOG_COMPARATOR" memspace="DATAMEM" text="" icon="io_analo.bmp">
 423           <reg size="1" name="AC0CON" offset="0x94" text="Analog Comparator 0 Control Register" icon="io_flag.bmp">
 424             <bitfield name="AC0EN" mask="0x80" text="Analog Comparator 0 Enable Bit" icon=""/>
 425             <bitfield name="AC0IE" mask="0x40" text="Analog Comparator 0 Interrupt Enable Bit" icon=""/>
 426             <bitfield name="AC0IS" mask="0x30" text="Analog Comparator 0  Interrupt Select Bits" icon=""/>
 427             <bitfield name="ACCKSEL" mask="0x08" text="Analog Comparator Clock Select" icon=""/>
 428             <bitfield name="AC0M" mask="0x07" text="Analog Comparator 0 Multiplexer Register" icon=""/>
 429           </reg>
 430           <reg size="1" name="AC1CON" offset="0x95" text="Analog Comparator 1 Control Register" icon="io_flag.bmp">
 431             <bitfield name="AC1EN" mask="0x80" text="Analog Comparator 1 Enable Bit" icon=""/>
 432             <bitfield name="AC1IE" mask="0x40" text="Analog Comparator 1 Interrupt Enable Bit" icon=""/>
 433             <bitfield name="AC1IS" mask="0x30" text="Analog Comparator 1  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 434             <bitfield name="AC1ICE" mask="0x08" text="Analog Comparator 1 Interrupt Capture Enable Bit" icon=""/>
 435             <bitfield name="AC1M" mask="0x07" text="Analog Comparator 1 Multiplexer Register" icon=""/>
 436           </reg>
 437           <reg size="1" name="AC2CON" offset="0x96" text="Analog Comparator 2 Control Register" icon="io_flag.bmp">
 438             <bitfield name="AC2EN" mask="0x80" text="Analog Comparator 2 Enable Bit" icon=""/>
 439             <bitfield name="AC2IE" mask="0x40" text="Analog Comparator 2 Interrupt Enable Bit" icon=""/>
 440             <bitfield name="AC2IS" mask="0x30" text="Analog Comparator 2  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 441             <bitfield name="AC2M" mask="0x07" text="Analog Comparator 2 Multiplexer Register" icon=""/>
 442           </reg>
 443           <reg size="1" name="AC3CON" offset="0x97" text="Analog Comparator 3 Control Register" icon="io_flag.bmp">
 444             <bitfield name="AC3EN" mask="0x80" text="Analog Comparator 3 Enable Bit" icon=""/>
 445             <bitfield name="AC3IE" mask="0x40" text="Analog Comparator 3 Interrupt Enable Bit" icon=""/>
 446             <bitfield name="AC3IS" mask="0x30" text="Analog Comparator 3  Interrupt Select Bit" icon="" enum="ANALOG_COMP_INTERRUPT"/>
 447             <bitfield name="AC3M" mask="0x07" text="Analog Comparator 3 Multiplexer Register" icon=""/>
 448           </reg>
 449           <reg size="1" name="ACSR" offset="0x50" text="Analog Comparator Status Register" icon="io_flag.bmp">
 450             <bitfield name="AC3IF" mask="0x80" text="Analog Comparator 3 Interrupt Flag Bit" icon=""/>
 451             <bitfield name="AC2IF" mask="0x40" text="Analog Comparator 2 Interrupt Flag Bit" icon=""/>
 452             <bitfield name="AC1IF" mask="0x20" text="Analog Comparator 1  Interrupt Flag Bit" icon=""/>
 453             <bitfield name="AC0IF" mask="0x10" text="Analog Comparator 0 Interrupt Flag Bit" icon=""/>
 454             <bitfield name="AC3O" mask="0x08" text="Analog Comparator 3 Output Bit" icon=""/>
 455             <bitfield name="AC2O" mask="0x04" text="Analog Comparator 2 Output Bit" icon=""/>
 456             <bitfield name="AC1O" mask="0x02" text="Analog Comparator 1 Output Bit" icon=""/>
 457             <bitfield name="AC0O" mask="0x01" text="Analog Comparator 0 Output Bit" icon=""/>
 458           </reg>
 459         </registers>
 460     </module>
 461     <module class="DA_CONVERTER">
 462       <registers name="DA_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 463           <reg size="1" name="DACH" offset="0x92" text="DAC Data Register High Byte" icon="io_analo.bmp">
 464             <bitfield name="DACH" mask="0xFF" text="DAC Data Register High Byte Bits" icon=""/>
 465           </reg>
 466           <reg size="1" name="DACL" offset="0x91" text="DAC Data Register Low Byte" icon="io_analo.bmp">
 467             <bitfield name="DACL" mask="0xFF" text="DAC Data Register Low Byte Bits" icon=""/>
 468           </reg>
 469           <reg size="1" name="DACON" offset="0x90" text="DAC Control Register" icon="io_analo.bmp">
 470             <bitfield name="DAATE" mask="0x80" text="DAC Auto Trigger Enable Bit" icon=""/>
 471             <bitfield name="DATS" mask="0x70" text="DAC Trigger Selection Bits" icon="" enum="ANALIG_DAC_AUTO_TRIGGER"/>
 472             <bitfield name="DALA" mask="0x04" text="DAC Left Adjust" icon=""/>
 473             <bitfield name="DAEN" mask="0x01" text="DAC Enable Bit" icon=""/>
 474           </reg>
 475         </registers>
 476     </module>
 477     <module class="CPU">
 478       <registers name="CPU" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 479           <reg size="1" name="SREG" offset="0x5F" text="Status Register" icon="io_sreg.bmp">
 480             <bitfield name="I" mask="0x80" text="Global Interrupt Enable" icon=""/>
 481             <bitfield name="T" mask="0x40" text="Bit Copy Storage" icon=""/>
 482             <bitfield name="H" mask="0x20" text="Half Carry Flag" icon=""/>
 483             <bitfield name="S" mask="0x10" text="Sign Bit" icon=""/>
 484             <bitfield name="V" mask="0x08" text="Two's Complement Overflow Flag" icon=""/>
 485             <bitfield name="N" mask="0x04" text="Negative Flag" icon=""/>
 486             <bitfield name="Z" mask="0x02" text="Zero Flag" icon=""/>
 487             <bitfield name="C" mask="0x01" text="Carry Flag" icon=""/>
 488           </reg>
 489           <reg size="2" name="SP" offset="0x5D" text="Stack Pointer " icon="io_sph.bmp" mask="0xFFFF"/>
 490           <reg size="1" name="MCUCR" offset="0x55" text="MCU Control Register" icon="io_flag.bmp">
 491             <bitfield name="SPIPS" mask="0x80" text="SPI Pin Select" icon=""/>
 492             <bitfield name="PUD" mask="0x10" text="Pull-up disable" icon=""/>
 493             <bitfield name="IVSEL" mask="0x02" text="Interrupt Vector Select" icon=""/>
 494             <bitfield name="IVCE" mask="0x01" text="Interrupt Vector Change Enable" icon=""/>
 495           </reg>
 496           <reg size="1" name="MCUSR" offset="0x54" text="MCU Status Register" icon="io_flag.bmp">
 497             <bitfield name="WDRF" mask="0x08" text="Watchdog Reset Flag" icon=""/>
 498             <bitfield name="BORF" mask="0x04" text="Brown-out Reset Flag" icon=""/>
 499             <bitfield name="EXTRF" mask="0x02" text="External Reset Flag" icon=""/>
 500             <bitfield name="PORF" mask="0x01" text="Power-on reset flag" icon=""/>
 501           </reg>
 502           <reg size="1" name="OSCCAL" offset="0x66" text="Oscillator Calibration Value" icon="io_cpu.bmp" mask="0x7F"/>
 503           <reg size="1" name="CLKPR" offset="0x61" text="" icon="io_cpu.bmp">
 504             <bitfield name="CLKPCE" mask="0x80" text="" icon=""/>
 505             <bitfield name="CLKPS" mask="0x0F" text="" icon="" enum="CPU_CLK_PRESCALE_4_BITS_SMALL"/>
 506           </reg>
 507           <reg size="1" name="SMCR" offset="0x53" text="Sleep Mode Control Register" icon="io_cpu.bmp">
 508             <bitfield name="SM" mask="0x0E" text="Sleep Mode Select bits" icon="" enum="CPU_SLEEP_MODE_3BITS4"/>
 509             <bitfield name="SE" mask="0x01" text="Sleep Enable" icon=""/>
 510           </reg>
 511           <reg size="1" name="GPIOR2" offset="0x3A" text="General Purpose IO Register 2" icon="io_cpu.bmp">
 512             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 2 bis" icon="" lsb="20"/>
 513           </reg>
 514           <reg size="1" name="GPIOR1" offset="0x39" text="General Purpose IO Register 1" icon="io_cpu.bmp">
 515             <bitfield name="GPIOR" mask="0xFF" text="General Purpose IO Register 1 bis" icon="" lsb="10"/>
 516           </reg>
 517           <reg size="1" name="GPIOR0" offset="0x3E" text="General Purpose IO Register 0" icon="io_cpu.bmp">
 518             <bitfield name="GPIOR07" mask="0x80" text="General Purpose IO Register 0 bit 7" icon=""/>
 519             <bitfield name="GPIOR06" mask="0x40" text="General Purpose IO Register 0 bit 6" icon=""/>
 520             <bitfield name="GPIOR05" mask="0x20" text="General Purpose IO Register 0 bit 5" icon=""/>
 521             <bitfield name="GPIOR04" mask="0x10" text="General Purpose IO Register 0 bit 4" icon=""/>
 522             <bitfield name="GPIOR03" mask="0x08" text="General Purpose IO Register 0 bit 3" icon=""/>
 523             <bitfield name="GPIOR02" mask="0x04" text="General Purpose IO Register 0 bit 2" icon=""/>
 524             <bitfield name="GPIOR01" mask="0x02" text="General Purpose IO Register 0 bit 1" icon=""/>
 525             <bitfield name="GPIOR00" mask="0x01" text="General Purpose IO Register 0 bit 0" icon=""/>
 526           </reg>
 527           <reg size="1" name="PLLCSR" offset="0x49" text="PLL Control And Status Register" icon="io_sreg.bmp">
 528             <bitfield name="PLLF" mask="0x04" text="PLL Factor" icon=""/>
 529             <bitfield name="PLLE" mask="0x02" text="PLL Enable" icon=""/>
 530             <bitfield name="PLOCK" mask="0x01" text="PLL Lock Detector" icon=""/>
 531           </reg>
 532           <reg size="1" name="PRR" offset="0x64" text="Power Reduction Register" icon="io_cpu.bmp">
 533             <bitfield name="PRCAN" mask="0x40" text="Power Reduction CAN" icon=""/>
 534             <bitfield name="PRPSC" mask="0x20" text="Power Reduction PSC" icon=""/>
 535             <bitfield name="PRTIM1" mask="0x10" text="Power Reduction Timer/Counter1" icon=""/>
 536             <bitfield name="PRTIM0" mask="0x08" text="Power Reduction Timer/Counter0" icon=""/>
 537             <bitfield name="PRSPI" mask="0x04" text="Power Reduction Serial Peripheral Interface" icon=""/>
 538             <bitfield name="PRLIN" mask="0x02" text="Power Reduction LIN UART" icon=""/>
 539             <bitfield name="PRADC" mask="0x01" text="Power Reduction ADC" icon=""/>
 540           </reg>
 541         </registers>
 542     </module>
 543     <module class="PORTE">
 544       <registers name="PORTE" memspace="DATAMEM" text="" icon="io_port.bmp">
 545           <reg size="1" name="PORTE" offset="0x2E" text="Port E Data Register" icon="io_port.bmp" mask="0x07"/>
 546           <reg size="1" name="DDRE" offset="0x2D" text="Port E Data Direction Register" icon="io_flag.bmp" mask="0x07"/>
 547           <reg size="1" name="PINE" offset="0x2C" text="Port E Input Pins" icon="io_port.bmp" mask="0x07"/>
 548         </registers>
 549     </module>
 550     <module class="TIMER_COUNTER_0">
 551       <registers name="TIMER_COUNTER_0" memspace="DATAMEM" text="" icon="io_timer.bmp">
 552           <reg size="1" name="TIMSK0" offset="0x6E" text="Timer/Counter0 Interrupt Mask Register" icon="io_flag.bmp">
 553             <bitfield name="OCIE0B" mask="0x04" text="Timer/Counter0 Output Compare Match B Interrupt Enable" icon=""/>
 554             <bitfield name="OCIE0A" mask="0x02" text="Timer/Counter0 Output Compare Match A Interrupt Enable" icon=""/>
 555             <bitfield name="TOIE0" mask="0x01" text="Timer/Counter0 Overflow Interrupt Enable" icon=""/>
 556           </reg>
 557           <reg size="1" name="TIFR0" offset="0x35" text="Timer/Counter0 Interrupt Flag register" icon="io_flag.bmp">
 558             <bitfield name="OCF0B" mask="0x04" text="Timer/Counter0 Output Compare Flag 0B" icon=""/>
 559             <bitfield name="OCF0A" mask="0x02" text="Timer/Counter0 Output Compare Flag 0A" icon=""/>
 560             <bitfield name="TOV0" mask="0x01" text="Timer/Counter0 Overflow Flag" icon=""/>
 561           </reg>
 562           <reg size="1" name="TCCR0A" offset="0x44" text="Timer/Counter  Control Register A" icon="io_flag.bmp">
 563             <bitfield name="COM0A" mask="0xC0" text="Compare Output Mode, Phase Correct PWM Mode" icon=""/>
 564             <bitfield name="COM0B" mask="0x30" text="Compare Output Mode, Fast PWm" icon=""/>
 565             <bitfield name="WGM0" mask="0x03" text="Waveform Generation Mode" icon=""/>
 566           </reg>
 567           <reg size="1" name="TCCR0B" offset="0x45" text="Timer/Counter Control Register B" icon="io_flag.bmp">
 568             <bitfield name="FOC0A" mask="0x80" text="Force Output Compare A" icon=""/>
 569             <bitfield name="FOC0B" mask="0x40" text="Force Output Compare B" icon=""/>
 570             <bitfield name="WGM02" mask="0x08" text="" icon=""/>
 571             <bitfield name="CS0" mask="0x07" text="Clock Select" icon="" enum="CLK_SEL_3BIT_EXT"/>
 572           </reg>
 573           <reg size="1" name="TCNT0" offset="0x46" text="Timer/Counter0" icon="io_timer.bmp" mask="0xFF"/>
 574           <reg size="1" name="OCR0A" offset="0x47" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 575           <reg size="1" name="OCR0B" offset="0x48" text="Timer/Counter0 Output Compare Register" icon="io_timer.bmp" mask="0xFF"/>
 576           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 577             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 578             <bitfield name="ICPSEL1" mask="0x40" text="Timer1 Input Capture Selection Bit" icon=""/>
 579             <bitfield name="PSR10" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 580           </reg>
 581         </registers>
 582     </module>
 583     <module class="TIMER_COUNTER_1">
 584       <registers name="TIMER_COUNTER_1" memspace="DATAMEM" text="" icon="io_timer.bmp">
 585           <reg size="1" name="TIMSK1" offset="0x6F" text="Timer/Counter Interrupt Mask Register" icon="io_flag.bmp">
 586             <bitfield name="ICIE1" mask="0x20" text="Timer/Counter1 Input Capture Interrupt Enable" icon=""/>
 587             <bitfield name="OCIE1B" mask="0x04" text="Timer/Counter1 Output CompareB Match Interrupt Enable" icon=""/>
 588             <bitfield name="OCIE1A" mask="0x02" text="Timer/Counter1 Output CompareA Match Interrupt Enable" icon=""/>
 589             <bitfield name="TOIE1" mask="0x01" text="Timer/Counter1 Overflow Interrupt Enable" icon=""/>
 590           </reg>
 591           <reg size="1" name="TIFR1" offset="0x36" text="Timer/Counter Interrupt Flag register" icon="io_flag.bmp">
 592             <bitfield name="ICF1" mask="0x20" text="Input Capture Flag 1" icon=""/>
 593             <bitfield name="OCF1B" mask="0x04" text="Output Compare Flag 1B" icon=""/>
 594             <bitfield name="OCF1A" mask="0x02" text="Output Compare Flag 1A" icon=""/>
 595             <bitfield name="TOV1" mask="0x01" text="Timer/Counter1 Overflow Flag" icon=""/>
 596           </reg>
 597           <reg size="1" name="TCCR1A" offset="0x80" text="Timer/Counter1 Control Register A" icon="io_flag.bmp">
 598             <bitfield name="COM1A" mask="0xC0" text="Compare Output Mode 1A, bits" icon=""/>
 599             <bitfield name="COM1B" mask="0x30" text="Compare Output Mode 1B, bits" icon=""/>
 600             <bitfield name="WGM1" mask="0x03" text="Waveform Generation Mode" icon=""/>
 601           </reg>
 602           <reg size="1" name="TCCR1B" offset="0x81" text="Timer/Counter1 Control Register B" icon="io_flag.bmp">
 603             <bitfield name="ICNC1" mask="0x80" text="Input Capture 1 Noise Canceler" icon=""/>
 604             <bitfield name="ICES1" mask="0x40" text="Input Capture 1 Edge Select" icon=""/>
 605             <bitfield name="WGM1" mask="0x18" text="Waveform Generation Mode" icon="" lsb="2"/>
 606             <bitfield name="CS1" mask="0x07" text="Prescaler source of Timer/Counter 1" icon="" enum="CLK_SEL_3BIT_EXT"/>
 607           </reg>
 608           <reg size="1" name="TCCR1C" offset="0x82" text="Timer/Counter1 Control Register C" icon="io_flag.bmp">
 609             <bitfield name="FOC1A" mask="0x80" text="" icon=""/>
 610             <bitfield name="FOC1B" mask="0x40" text="" icon=""/>
 611           </reg>
 612           <reg size="2" name="TCNT1" offset="0x84" text="Timer/Counter1  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 613           <reg size="2" name="OCR1A" offset="0x88" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 614           <reg size="2" name="OCR1B" offset="0x8A" text="Timer/Counter1 Output Compare Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 615           <reg size="2" name="ICR1" offset="0x86" text="Timer/Counter1 Input Capture Register  Bytes" icon="io_timer.bmp" mask="0xFFFF"/>
 616           <reg size="1" name="GTCCR" offset="0x43" text="General Timer/Counter Control Register" icon="io_flag.bmp">
 617             <bitfield name="TSM" mask="0x80" text="Timer/Counter Synchronization Mode" icon=""/>
 618             <bitfield name="PSRSYNC" mask="0x01" text="Prescaler Reset Timer/Counter1 and Timer/Counter0" icon=""/>
 619           </reg>
 620         </registers>
 621     </module>
 622     <module class="AD_CONVERTER">
 623       <registers name="AD_CONVERTER" memspace="DATAMEM" text="" icon="io_analo.bmp">
 624           <reg size="1" name="ADMUX" offset="0x7C" text="The ADC multiplexer Selection Register" icon="io_analo.bmp">
 625             <bitfield name="REFS" mask="0xC0" text="Reference Selection Bits" icon="" enum="ANALOG_ADC_V_REF2"/>
 626             <bitfield name="ADLAR" mask="0x20" text="Left Adjust Result" icon=""/>
 627             <bitfield name="MUX" mask="0x0F" text="Analog Channel and Gain Selection Bits" icon=""/>
 628           </reg>
 629           <reg size="1" name="ADCSRA" offset="0x7A" text="The ADC Control and Status register" icon="io_flag.bmp">
 630             <bitfield name="ADEN" mask="0x80" text="ADC Enable" icon=""/>
 631             <bitfield name="ADSC" mask="0x40" text="ADC Start Conversion" icon=""/>
 632             <bitfield name="ADATE" mask="0x20" text="ADC Auto Trigger Enable" icon=""/>
 633             <bitfield name="ADIF" mask="0x10" text="ADC Interrupt Flag" icon=""/>
 634             <bitfield name="ADIE" mask="0x08" text="ADC Interrupt Enable" icon=""/>
 635             <bitfield name="ADPS" mask="0x07" text="ADC  Prescaler Select Bits" icon=""/>
 636           </reg>
 637           <reg size="2" name="ADC" offset="0x78" text="ADC Data Register  Bytes" icon="io_analo.bmp" mask="0xFFFF"/>
 638           <reg size="1" name="ADCSRB" offset="0x7B" text="ADC Control and Status Register B" icon="io_analo.bmp" mask="0xEF"/>
 639           <reg size="1" name="DIDR0" offset="0x7E" text="Digital Input Disable Register 0" icon="io_analo.bmp" mask="0xFF"/>
 640           <reg size="1" name="DIDR1" offset="0x7F" text="Digital Input Disable Register 0" icon="">
 641             <bitfield name="AMP2PD" mask="0x40" text="AMP2P Pin Digital input Disable" icon=""/>
 642             <bitfield name="ACMP0D" mask="0x20" text="ACMP0 Pin Digital input Disable" icon=""/>
 643             <bitfield name="AMP0PD" mask="0x10" text="AMP0P Pin Digital input Disable" icon=""/>
 644             <bitfield name="AMP0ND" mask="0x08" text="AMP0N Pin Digital input Disable" icon=""/>
 645             <bitfield name="ADC10D" mask="0x04" text="ADC10 Pin Digital input Disable" icon=""/>
 646             <bitfield name="ADC9D" mask="0x02" text="ADC9 Pin Digital input Disable" icon=""/>
 647             <bitfield name="ADC8D" mask="0x01" text="ADC8 Pin Digital input Disable" icon=""/>
 648           </reg>
 649           <reg size="1" name="AMP0CSR" offset="0x75" text="" icon="io_analo.bmp">
 650             <bitfield name="AMP0EN" mask="0x80" text="" icon=""/>
 651             <bitfield name="AMP0IS" mask="0x40" text="" icon=""/>
 652             <bitfield name="AMP0G" mask="0x30" text="" icon=""/>
 653             <bitfield name="AMPCMP0" mask="0x08" text="Amplifier 0 - Comparator 0 Connection" icon=""/>
 654             <bitfield name="AMP0TS" mask="0x07" text="" icon=""/>
 655           </reg>
 656           <reg size="1" name="AMP1CSR" offset="0x76" text="" icon="io_analo.bmp">
 657             <bitfield name="AMP1EN" mask="0x80" text="" icon=""/>
 658             <bitfield name="AMP1IS" mask="0x40" text="" icon=""/>
 659             <bitfield name="AMP1G" mask="0x30" text="" icon=""/>
 660             <bitfield name="AMPCMP1" mask="0x08" text="Amplifier 1 - Comparator 1 Connection" icon=""/>
 661             <bitfield name="AMP1TS" mask="0x07" text="" icon=""/>
 662           </reg>
 663           <reg size="1" name="AMP2CSR" offset="0x77" text="" icon="io_analo.bmp">
 664             <bitfield name="AMP2EN" mask="0x80" text="" icon=""/>
 665             <bitfield name="AMP2IS" mask="0x40" text="" icon=""/>
 666             <bitfield name="AMP2G" mask="0x30" text="" icon=""/>
 667             <bitfield name="AMPCMP2" mask="0x08" text="Amplifier 2 - Comparator 2 Connection" icon=""/>
 668             <bitfield name="AMP2TS" mask="0x07" text="" icon=""/>
 669           </reg>
 670         </registers>
 671     </module>
 672     <module class="LINUART">
 673       <registers name="LINUART" memspace="DATAMEM" text="" icon="io_com.bmp">
 674           <reg size="1" name="LINCR" offset="0xC8" text="LIN Control Register" icon="io_analo.bmp">
 675             <bitfield name="LSWRES" mask="0x80" text="Software Reset" icon=""/>
 676             <bitfield name="LIN13" mask="0x40" text="LIN Standard" icon=""/>
 677             <bitfield name="LCONF" mask="0x30" text="LIN Configuration bits" icon=""/>
 678             <bitfield name="LENA" mask="0x08" text="LIN or UART Enable" icon=""/>
 679             <bitfield name="LCMD" mask="0x07" text="LIN Command and Mode bits" icon=""/>
 680           </reg>
 681           <reg size="1" name="LINSIR" offset="0xC9" text="LIN Status and Interrupt Register" icon="io_flag.bmp">
 682             <bitfield name="LIDST" mask="0xE0" text="Identifier Status bits" icon=""/>
 683             <bitfield name="LBUSY" mask="0x10" text="Busy Signal" icon=""/>
 684             <bitfield name="LERR" mask="0x08" text="Error Interrupt" icon=""/>
 685             <bitfield name="LIDOK" mask="0x04" text="Identifier Interrupt" icon=""/>
 686             <bitfield name="LTXOK" mask="0x02" text="Transmit Performed Interrupt" icon=""/>
 687             <bitfield name="LRXOK" mask="0x01" text="Receive Performed Interrupt" icon=""/>
 688           </reg>
 689           <reg size="1" name="LINENIR" offset="0xCA" text="LIN Enable Interrupt Register" icon="io_analo.bmp">
 690             <bitfield name="LENERR" mask="0x08" text="Enable Error Interrupt" icon=""/>
 691             <bitfield name="LENIDOK" mask="0x04" text="Enable Identifier Interrupt" icon=""/>
 692             <bitfield name="LENTXOK" mask="0x02" text="Enable Transmit Performed Interrupt" icon=""/>
 693             <bitfield name="LENRXOK" mask="0x01" text="Enable Receive Performed Interrupt" icon=""/>
 694           </reg>
 695           <reg size="1" name="LINERR" offset="0xCB" text="LIN Error Register" icon="io_flag.bmp">
 696             <bitfield name="LABORT" mask="0x80" text="Abort Flag" icon=""/>
 697             <bitfield name="LTOERR" mask="0x40" text="Frame Time Out Error Flag" icon=""/>
 698             <bitfield name="LOVERR" mask="0x20" text="Overrun Error Flag" icon=""/>
 699             <bitfield name="LFERR" mask="0x10" text="Framing Error Flag" icon=""/>
 700             <bitfield name="LSERR" mask="0x08" text="Synchronization Error Flag" icon=""/>
 701             <bitfield name="LPERR" mask="0x04" text="Parity Error Flag" icon=""/>
 702             <bitfield name="LCERR" mask="0x02" text="Checksum Error Flag" icon=""/>
 703             <bitfield name="LBERR" mask="0x01" text="Bit Error Flag" icon=""/>
 704           </reg>
 705           <reg size="1" name="LINBTR" offset="0xCC" text="LIN Bit Timing Register" icon="io_flag.bmp">
 706             <bitfield name="LDISR" mask="0x80" text="Disable Bit Timing Resynchronization" icon=""/>
 707             <bitfield name="LBT" mask="0x3F" text="LIN Bit Timing bits" icon=""/>
 708           </reg>
 709           <reg size="1" name="LINBRRL" offset="0xCD" text="LIN Baud Rate Low Register" icon="io_timer.bmp">
 710             <bitfield name="LDIV" mask="0xFF" text="" icon=""/>
 711           </reg>
 712           <reg size="1" name="LINBRRH" offset="0xCE" text="LIN Baud Rate High Register" icon="io_timer.bmp">
 713             <bitfield name="LDIV" mask="0x0F" text="" icon="" lsb="8"/>
 714           </reg>
 715           <reg size="1" name="LINDLR" offset="0xCF" text="LIN Data Length Register" icon="io_com.bmp">
 716             <bitfield name="LTXDL" mask="0xF0" text="LIN Transmit Data Length bits" icon=""/>
 717             <bitfield name="LRXDL" mask="0x0F" text="LIN Receive Data Length bits" icon=""/>
 718           </reg>
 719           <reg size="1" name="LINIDR" offset="0xD0" text="LIN Identifier Register" icon="io_com.bmp">
 720             <bitfield name="LP" mask="0xC0" text="Parity bits" icon=""/>
 721             <bitfield name="LID" mask="0x3F" text="Identifier bit 5 or Data Length bits" icon=""/>
 722           </reg>
 723           <reg size="1" name="LINSEL" offset="0xD1" text="LIN Data Buffer Selection Register" icon="io_com.bmp">
 724             <bitfield name="LAINC" mask="0x08" text="Auto Increment of Data Buffer Index (Active Low)" icon=""/>
 725             <bitfield name="LINDX" mask="0x07" text="FIFO LIN Data Buffer Index bits" icon=""/>
 726           </reg>
 727           <reg size="1" name="LINDAT" offset="0xD2" text="LIN Data Register" icon="io_com.bmp">
 728             <bitfield name="LDATA" mask="0xFF" text="" icon=""/>
 729           </reg>
 730         </registers>
 731     </module>
 732     <module class="SPI">
 733       <registers name="SPI" memspace="DATAMEM" text="" icon="io_com.bmp">
 734           <reg size="1" name="SPCR" offset="0x4C" text="SPI Control Register" icon="io_flag.bmp">
 735             <bitfield name="SPIE" mask="0x80" text="SPI Interrupt Enable" icon=""/>
 736             <bitfield name="SPE" mask="0x40" text="SPI Enable" icon=""/>
 737             <bitfield name="DORD" mask="0x20" text="Data Order" icon=""/>
 738             <bitfield name="MSTR" mask="0x10" text="Master/Slave Select" icon=""/>
 739             <bitfield name="CPOL" mask="0x08" text="Clock polarity" icon=""/>
 740             <bitfield name="CPHA" mask="0x04" text="Clock Phase" icon=""/>
 741             <bitfield name="SPR" mask="0x03" text="SPI Clock Rate Selects" icon="" enum="COMM_SCK_RATE_3BIT"/>
 742           </reg>
 743           <reg size="1" name="SPSR" offset="0x4D" text="SPI Status Register" icon="io_flag.bmp">
 744             <bitfield name="SPIF" mask="0x80" text="SPI Interrupt Flag" icon=""/>
 745             <bitfield name="WCOL" mask="0x40" text="Write Collision Flag" icon=""/>
 746             <bitfield name="SPI2X" mask="0x01" text="Double SPI Speed Bit" icon=""/>
 747           </reg>
 748           <reg size="1" name="SPDR" offset="0x4E" text="SPI Data Register" icon="io_com.bmp" mask="0xFF"/>
 749         </registers>
 750     </module>
 751     <module class="WATCHDOG">
 752       <registers name="WATCHDOG" memspace="DATAMEM" text="" icon="io_watch.bmp">
 753           <reg size="1" name="WDTCSR" offset="0x60" text="Watchdog Timer Control Register" icon="io_flag.bmp">
 754             <bitfield name="WDIF" mask="0x80" text="Watchdog Timeout Interrupt Flag" icon=""/>
 755             <bitfield name="WDIE" mask="0x40" text="Watchdog Timeout Interrupt Enable" icon=""/>
 756             <bitfield name="WDP" mask="0x27" text="Watchdog Timer Prescaler Bits" icon="" enum="WDOG_TIMER_PRESCALE_4BITS"/>
 757             <bitfield name="WDCE" mask="0x10" text="Watchdog Change Enable" icon=""/>
 758             <bitfield name="WDE" mask="0x08" text="Watch Dog Enable" icon=""/>
 759           </reg>
 760         </registers>
 761     </module>
 762     <module class="EXTERNAL_INTERRUPT">
 763       <registers name="EXTERNAL_INTERRUPT" memspace="DATAMEM" text="" icon="io_ext.bmp">
 764           <reg size="1" name="EICRA" offset="0x69" text="External Interrupt Control Register A" icon="io_flag.bmp">
 765             <bitfield name="ISC3" mask="0xC0" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 766             <bitfield name="ISC2" mask="0x30" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 767             <bitfield name="ISC1" mask="0x0C" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 768             <bitfield name="ISC0" mask="0x03" text="External Interrupt Sense Control Bit" icon="" enum="INTERRUPT_SENSE_CONTROL"/>
 769           </reg>
 770           <reg size="1" name="EIMSK" offset="0x3D" text="External Interrupt Mask Register" icon="io_flag.bmp">
 771             <bitfield name="INT" mask="0x0F" text="External Interrupt Request 3 Enable" icon=""/>
 772           </reg>
 773           <reg size="1" name="EIFR" offset="0x3C" text="External Interrupt Flag Register" icon="io_flag.bmp">
 774             <bitfield name="INTF" mask="0x0F" text="External Interrupt Flags" icon=""/>
 775           </reg>
 776         </registers>
 777     </module>
 778     <module class="EEPROM">
 779       <registers name="EEPROM" memspace="DATAMEM" text="" icon="io_cpu.bmp">
 780           <reg size="2" name="EEAR" offset="0x41" text="EEPROM Read/Write Access" icon="io_cpu.bmp" mask="0x03FF"/>
 781           <reg size="1" name="EEDR" offset="0x40" text="EEPROM Data Register" icon="io_cpu.bmp" mask="0xFF"/>
 782           <reg size="1" name="EECR" offset="0x3F" text="EEPROM Control Register" icon="io_flag.bmp">
 783             <bitfield name="EEPM" mask="0x30" text="" icon="" enum="EEP_MODE"/>
 784             <bitfield name="EERIE" mask="0x08" text="EEProm Ready Interrupt Enable" icon=""/>
 785             <bitfield name="EEMPE" mask="0x04" text="EEPROM Master Write Enable" icon=""/>
 786             <bitfield name="EEPE" mask="0x02" text="EEPROM Write Enable" icon=""/>
 787             <bitfield name="EERE" mask="0x01" text="EEPROM Read Enable" icon=""/>
 788           </reg>
 789         </registers>
 790     </module>
 791     <module class="PSC">
 792       <registers name="PSC" memspace="DATAMEM" text="" icon="io_com.bmp">
 793           <reg size="1" name="PIFR" offset="0xBC" text="PSC Interrupt Flag Register" icon="register.bmp">
 794             <bitfield name="PEV" mask="0x0E" text="PSC External Event 2 Interrupt" icon=""/>
 795             <bitfield name="PEOP" mask="0x01" text="PSC End of Cycle Interrupt" icon=""/>
 796           </reg>
 797           <reg size="1" name="PIM" offset="0xBB" text="PSC Interrupt Mask Register" icon="register.bmp">
 798             <bitfield name="PEVE" mask="0x0E" text="External Event 2 Interrupt Enable" icon=""/>
 799             <bitfield name="PEOPE" mask="0x01" text="PSC End of Cycle Interrupt Enable" icon=""/>
 800           </reg>
 801           <reg size="1" name="PMIC2" offset="0xBA" text="PSC Module 2 Input Control Register" icon="register.bmp">
 802             <bitfield name="POVEN2" mask="0x80" text="PSC Module 2 Overlap Enable" icon=""/>
 803             <bitfield name="PISEL2" mask="0x40" text="PSC Module 2 Input Select" icon=""/>
 804             <bitfield name="PELEV2" mask="0x20" text="PSC Module 2 Input Level Selector" icon=""/>
 805             <bitfield name="PFLTE2" mask="0x10" text="PSC Module 2 Input Filter Enable" icon=""/>
 806             <bitfield name="PAOC2" mask="0x08" text="PSC Module 2 Asynchronous Output Control" icon=""/>
 807             <bitfield name="PRFM2" mask="0x07" text="PSC Module 2 Input Mode bits" icon=""/>
 808           </reg>
 809           <reg size="1" name="PMIC1" offset="0xB9" text="PSC Module 1 Input Control Register" icon="register.bmp">
 810             <bitfield name="POVEN1" mask="0x80" text="PSC Module 1 Overlap Enable" icon=""/>
 811             <bitfield name="PISEL1" mask="0x40" text="PSC Module 1 Input Select" icon=""/>
 812             <bitfield name="PELEV1" mask="0x20" text="PSC Module 1 Input Level Selector" icon=""/>
 813             <bitfield name="PFLTE1" mask="0x10" text="PSC Module 1 Input Filter Enable" icon=""/>
 814             <bitfield name="PAOC1" mask="0x08" text="PSC Module 1 Asynchronous Output Control" icon=""/>
 815             <bitfield name="PRFM1" mask="0x07" text="PSC Module 1 Input Mode bits" icon=""/>
 816           </reg>
 817           <reg size="1" name="PMIC0" offset="0xB8" text="PSC Module 0 Input Control Register" icon="register.bmp">
 818             <bitfield name="POVEN0" mask="0x80" text="PSC Module 0 Overlap Enable" icon=""/>
 819             <bitfield name="PISEL0" mask="0x40" text="PSC Module 0 Input Select" icon=""/>
 820             <bitfield name="PELEV0" mask="0x20" text="PSC Module 0 Input Level Selector" icon=""/>
 821             <bitfield name="PFLTE0" mask="0x10" text="PSC Module 0 Input Filter Enable" icon=""/>
 822             <bitfield name="PAOC0" mask="0x08" text="PSC Module 0 Asynchronous Output Control" icon=""/>
 823             <bitfield name="PRFM0" mask="0x07" text="PSC Module 0 Input Mode bits" icon=""/>
 824           </reg>
 825           <reg size="1" name="PCTL" offset="0xB7" text="PSC Control Register" icon="register.bmp">
 826             <bitfield name="PPRE" mask="0xC0" text="PSC Prescaler Select bits" icon=""/>
 827             <bitfield name="PCLKSEL" mask="0x20" text="PSC Input Clock Select" icon=""/>
 828             <bitfield name="PCCYC" mask="0x02" text="PSC Complete Cycle" icon=""/>
 829             <bitfield name="PRUN" mask="0x01" text="PSC Run" icon=""/>
 830           </reg>
 831           <reg size="1" name="POC" offset="0xB6" text="PSC Output Configuration" icon="register.bmp">
 832             <bitfield name="POEN2B" mask="0x20" text="PSC Output 2B Enable" icon=""/>
 833             <bitfield name="POEN2A" mask="0x10" text="PSC Output 2A Enable" icon=""/>
 834             <bitfield name="POEN1B" mask="0x08" text="PSC Output 1B Enable" icon=""/>
 835             <bitfield name="POEN1A" mask="0x04" text="PSC Output 1A Enable" icon=""/>
 836             <bitfield name="POEN0B" mask="0x02" text="PSC Output 0B Enable" icon=""/>
 837             <bitfield name="POEN0A" mask="0x01" text="PSC Output 0A Enable" icon=""/>
 838           </reg>
 839           <reg size="1" name="PCNF" offset="0xB5" text="PSC Configuration Register" icon="register.bmp">
 840             <bitfield name="PULOCK" mask="0x20" text="PSC Update Lock" icon=""/>
 841             <bitfield name="PMODE" mask="0x10" text="PSC Mode" icon=""/>
 842             <bitfield name="POPB" mask="0x08" text="PSC Output B Polarity" icon=""/>
 843             <bitfield name="POPA" mask="0x04" text="PSC Output A Polarity" icon=""/>
 844           </reg>
 845           <reg size="1" name="PSYNC" offset="0xB4" text="PSC Synchro Configuration" icon="register.bmp">
 846             <bitfield name="PSYNC2" mask="0x30" text="Selection of Synchronization Out for ADC" icon=""/>
 847             <bitfield name="PSYNC1" mask="0x0C" text="Selection of Synchronization Out for ADC" icon=""/>
 848             <bitfield name="PSYNC0" mask="0x03" text="Selection of Synchronization Out for ADC" icon=""/>
 849           </reg>
 850           <reg size="2" name="POCR_RB" offset="0xB2" text="PSC Output Compare RB Register " icon="register.bmp" mask="0x0FFF"/>
 851           <reg size="2" name="POCR2SB" offset="0xB0" text="PSC Module 2 Output Compare SB Register " icon="register.bmp" mask="0x0FFF"/>
 852           <reg size="2" name="POCR2RA" offset="0xAE" text="PSC Module 2 Output Compare RA Register " icon="register.bmp" mask="0x0FFF"/>
 853           <reg size="2" name="POCR2SA" offset="0xAC" text="PSC Module 2 Output Compare SA Register " icon="register.bmp" mask="0x0FFF"/>
 854           <reg size="2" name="POCR1SB" offset="0xAA" text="PSC Module 1 Output Compare SB Register " icon="register.bmp" mask="0x0FFF"/>
 855           <reg size="2" name="POCR1RA" offset="0xA8" text="PSC Module 1 Output Compare RA Register " icon="register.bmp" mask="0x0FFF"/>
 856           <reg size="2" name="POCR1SA" offset="0xA6" text="PSC Output Compare SA Register " icon="register.bmp" mask="0x0FFF"/>
 857           <reg size="2" name="POCR0SB" offset="0xA4" text="PSC Output Compare SB Register " icon="register.bmp" mask="0x0FFF"/>
 858           <reg size="2" name="POCR0RA" offset="0xA2" text="PSC Module 0 Output Compare RA Register " icon="register.bmp" mask="0x0FFF"/>
 859           <reg size="2" name="POCR0SA" offset="0xA0" text="PSC Module 0 Output Compare SA Register " icon="register.bmp" mask="0x0FFF"/>
 860         </registers>
 861     </module>
 862   </hardware>
 863 </device>