hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "isa.h"
  29 #include "sysbus.h"
  30
  31 typedef uint32_t pci_addr_t;
  32 #include "pci_host.h"
  33
  34 typedef PCIHostState I440FXState;
  35
  36 typedef struct PIIX3State {
  37     PCIDevice dev;
  38     int pci_irq_levels[4];
  39 } PIIX3State;
  40
  41 typedef struct PIIX3IrqState {
  42     PIIX3State *piix3;
  43     qemu_irq *pic;
  44 } PIIX3IrqState;
  45
  46 struct PCII440FXState {
  47     PCIDevice dev;
  48     target_phys_addr_t isa_page_descs[384 / 4];
  49     uint8_t smm_enabled;
  50     PIIX3IrqState *irq_state;
  51 };
  52
  53 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  54 {
  55     I440FXState *s = opaque;
  56     s->config_reg = val;
  57 }
  58
  59 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  60 {
  61     I440FXState *s = opaque;
  62     return s->config_reg;
  63 }
  64
  65 static void piix3_set_irq(void *opaque, int irq_num, int level);
  66
  67 /* return the global irq number corresponding to a given device irq
  68    pin. We could also use the bus number to have a more precise
  69    mapping. */
  70 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  71 {
  72     int slot_addend;
  73     slot_addend = (pci_dev->devfn >> 3) - 1;
  74     return (irq_num + slot_addend) & 3;
  75 }
  76
  77 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  78 {
  79     uint32_t addr;
  80
  81     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  82     switch(r) {
  83     case 3:
  84         /* RAM */
  85         cpu_register_physical_memory(start, end - start,
  86                                      start);
  87         break;
  88     case 1:
  89         /* ROM (XXX: not quite correct) */
  90         cpu_register_physical_memory(start, end - start,
  91                                      start | IO_MEM_ROM);
  92         break;
  93     case 2:
  94     case 0:
  95         /* XXX: should distinguish read/write cases */
  96         for(addr = start; addr < end; addr += 4096) {
  97             cpu_register_physical_memory(addr, 4096,
  98                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  99         }
 100         break;
 101     }
 102 }
 103
 104 static void i440fx_update_memory_mappings(PCII440FXState *d)
 105 {
 106     int i, r;
 107     uint32_t smram, addr;
 108
 109     update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
 110     for(i = 0; i < 12; i++) {
 111         r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
 112         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 113     }
 114     smram = d->dev.config[0x72];
 115     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 116         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 117     } else {
 118         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 119             cpu_register_physical_memory(addr, 4096,
 120                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 121         }
 122     }
 123 }
 124
 125 void i440fx_set_smm(PCII440FXState *d, int val)
 126 {
 127     val = (val != 0);
 128     if (d->smm_enabled != val) {
 129         d->smm_enabled = val;
 130         i440fx_update_memory_mappings(d);
 131     }
 132 }
 133
 134
 135 /* XXX: suppress when better memory API. We make the assumption that
 136    no device (in particular the VGA) changes the memory mappings in
 137    the 0xa0000-0x100000 range */
 138 void i440fx_init_memory_mappings(PCII440FXState *d)
 139 {
 140     int i;
 141     for(i = 0; i < 96; i++) {
 142         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 143     }
 144 }
 145
 146 static void i440fx_write_config(PCIDevice *dev,
 147                                 uint32_t address, uint32_t val, int len)
 148 {
 149     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 150
 151     /* XXX: implement SMRAM.D_LOCK */
 152     pci_default_write_config(dev, address, val, len);
 153     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 154         i440fx_update_memory_mappings(d);
 155 }
 156
 157 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 158 {
 159     PCII440FXState *d = opaque;
 160     int ret, i;
 161
 162     ret = pci_device_load(&d->dev, f);
 163     if (ret < 0)
 164         return ret;
 165     i440fx_update_memory_mappings(d);
 166     qemu_get_8s(f, &d->smm_enabled);
 167
 168     if (version_id == 2)
 169         for (i = 0; i < 4; i++)
 170             d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 171
 172     return 0;
 173 }
 174
 175 static int i440fx_after_load(void *opaque)
 176 {
 177     PCII440FXState *d = opaque;
 178
 179     i440fx_update_memory_mappings(d);
 180     return 0;
 181 }
 182
 183 static const VMStateDescription vmstate_i440fx = {
 184     .name = "I440FX",
 185     .version_id = 3,
 186     .minimum_version_id = 3,
 187     .minimum_version_id_old = 1,
 188     .load_state_old = i440fx_load_old,
 189     .run_after_load = i440fx_after_load,
 190     .fields      = (VMStateField []) {
 191         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 192         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 193         VMSTATE_END_OF_LIST()
 194     }
 195 };
 196
 197 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 198 {
 199     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 200
 201     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 202     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 203
 204     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 205     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 206     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 207     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 208     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 209     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 210     return 0;
 211 }
 212
 213 static int i440fx_initfn(PCIDevice *dev)
 214 {
 215     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 216
 217     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 218     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 219     d->dev.config[0x08] = 0x02; // revision
 220     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 221     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 222
 223     d->dev.config[0x72] = 0x02; /* SMRAM */
 224
 225     vmstate_register(0, &vmstate_i440fx, d);
 226     return 0;
 227 }
 228
 229 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 230 {
 231     DeviceState *dev;
 232     PCIBus *b;
 233     PCIDevice *d;
 234     I440FXState *s;
 235     PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
 236
 237     irq_state->pic = pic;
 238     dev = qdev_create(NULL, "i440FX-pcihost");
 239     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 240     b = pci_register_bus(&s->busdev.qdev, "pci.0",
 241                          piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
 242     s->bus = b;
 243     qdev_init(dev);
 244
 245     d = pci_create_simple(b, 0, "i440FX");
 246     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 247     (*pi440fx_state)->irq_state = irq_state;
 248
 249     irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
 250                                  pci_create_simple(b, -1, "PIIX3"));
 251     *piix3_devfn = irq_state->piix3->dev.devfn;
 252
 253     return b;
 254 }
 255
 256 /* PIIX3 PCI to ISA bridge */
 257
 258 static void piix3_set_irq(void *opaque, int irq_num, int level)
 259 {
 260     int i, pic_irq, pic_level;
 261     PIIX3IrqState *irq_state = opaque;
 262
 263     irq_state->piix3->pci_irq_levels[irq_num] = level;
 264
 265     /* now we change the pic irq level according to the piix irq mappings */
 266     /* XXX: optimize */
 267     pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
 268     if (pic_irq < 16) {
 269         /* The pic level is the logical OR of all the PCI irqs mapped
 270            to it */
 271         pic_level = 0;
 272         for (i = 0; i < 4; i++) {
 273             if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
 274                 pic_level |= irq_state->piix3->pci_irq_levels[i];
 275         }
 276         qemu_set_irq(irq_state->pic[pic_irq], pic_level);
 277     }
 278 }
 279
 280 static void piix3_reset(void *opaque)
 281 {
 282     PIIX3State *d = opaque;
 283     uint8_t *pci_conf = d->dev.config;
 284
 285     pci_conf[0x04] = 0x07; // master, memory and I/O
 286     pci_conf[0x05] = 0x00;
 287     pci_conf[0x06] = 0x00;
 288     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 289     pci_conf[0x4c] = 0x4d;
 290     pci_conf[0x4e] = 0x03;
 291     pci_conf[0x4f] = 0x00;
 292     pci_conf[0x60] = 0x80;
 293     pci_conf[0x61] = 0x80;
 294     pci_conf[0x62] = 0x80;
 295     pci_conf[0x63] = 0x80;
 296     pci_conf[0x69] = 0x02;
 297     pci_conf[0x70] = 0x80;
 298     pci_conf[0x76] = 0x0c;
 299     pci_conf[0x77] = 0x0c;
 300     pci_conf[0x78] = 0x02;
 301     pci_conf[0x79] = 0x00;
 302     pci_conf[0x80] = 0x00;
 303     pci_conf[0x82] = 0x00;
 304     pci_conf[0xa0] = 0x08;
 305     pci_conf[0xa2] = 0x00;
 306     pci_conf[0xa3] = 0x00;
 307     pci_conf[0xa4] = 0x00;
 308     pci_conf[0xa5] = 0x00;
 309     pci_conf[0xa6] = 0x00;
 310     pci_conf[0xa7] = 0x00;
 311     pci_conf[0xa8] = 0x0f;
 312     pci_conf[0xaa] = 0x00;
 313     pci_conf[0xab] = 0x00;
 314     pci_conf[0xac] = 0x00;
 315     pci_conf[0xae] = 0x00;
 316
 317     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 318 }
 319
 320 static const VMStateDescription vmstate_piix3 = {
 321     .name = "PIIX3",
 322     .version_id = 3,
 323     .minimum_version_id = 2,
 324     .minimum_version_id_old = 2,
 325     .fields      = (VMStateField []) {
 326         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 327         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 328         VMSTATE_END_OF_LIST()
 329     }
 330 };
 331
 332 static int piix3_initfn(PCIDevice *dev)
 333 {
 334     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 335     uint8_t *pci_conf;
 336
 337     isa_bus_new(&d->dev.qdev);
 338     vmstate_register(0, &vmstate_piix3, d);
 339
 340     pci_conf = d->dev.config;
 341     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 342     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 343     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 344     pci_conf[PCI_HEADER_TYPE] =
 345         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 346
 347     piix3_reset(d);
 348     qemu_register_reset(piix3_reset, d);
 349     return 0;
 350 }
 351
 352 static PCIDeviceInfo i440fx_info[] = {
 353     {
 354         .qdev.name    = "i440FX",
 355         .qdev.desc    = "Host bridge",
 356         .qdev.size    = sizeof(PCII440FXState),
 357         .qdev.no_user = 1,
 358         .init         = i440fx_initfn,
 359         .config_write = i440fx_write_config,
 360     },{
 361         .qdev.name    = "PIIX3",
 362         .qdev.desc    = "ISA bridge",
 363         .qdev.size    = sizeof(PIIX3State),
 364         .qdev.no_user = 1,
 365         .init         = piix3_initfn,
 366     },{
 367         /* end of list */
 368     }
 369 };
 370
 371 static SysBusDeviceInfo i440fx_pcihost_info = {
 372     .init         = i440fx_pcihost_initfn,
 373     .qdev.name    = "i440FX-pcihost",
 374     .qdev.size    = sizeof(I440FXState),
 375     .qdev.no_user = 1,
 376 };
 377
 378 static void i440fx_register(void)
 379 {
 380     sysbus_register_withprop(&i440fx_pcihost_info);
 381     pci_qdev_register_many(i440fx_info);
 382 }
 383 device_init(i440fx_register);