hw/piix_pci.c

   1 /*
   2  * QEMU i440FX/PIIX3 PCI Bridge Emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pci.h"
  28 #include "isa.h"
  29 #include "sysbus.h"
  30
  31 typedef uint32_t pci_addr_t;
  32 #include "pci_host.h"
  33
  34 typedef PCIHostState I440FXState;
  35
  36 typedef struct PIIX3State {
  37     PCIDevice dev;
  38     int pci_irq_levels[4];
  39     qemu_irq *pic;
  40 } PIIX3State;
  41
  42 struct PCII440FXState {
  43     PCIDevice dev;
  44     target_phys_addr_t isa_page_descs[384 / 4];
  45     uint8_t smm_enabled;
  46     PIIX3State *piix3;
  47 };
  48
  49 static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
  50 {
  51     I440FXState *s = opaque;
  52     s->config_reg = val;
  53 }
  54
  55 static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr)
  56 {
  57     I440FXState *s = opaque;
  58     return s->config_reg;
  59 }
  60
  61 static void piix3_set_irq(void *opaque, int irq_num, int level);
  62
  63 /* return the global irq number corresponding to a given device irq
  64    pin. We could also use the bus number to have a more precise
  65    mapping. */
  66 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
  67 {
  68     int slot_addend;
  69     slot_addend = (pci_dev->devfn >> 3) - 1;
  70     return (irq_num + slot_addend) & 3;
  71 }
  72
  73 static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r)
  74 {
  75     uint32_t addr;
  76
  77     //    printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
  78     switch(r) {
  79     case 3:
  80         /* RAM */
  81         cpu_register_physical_memory(start, end - start,
  82                                      start);
  83         break;
  84     case 1:
  85         /* ROM (XXX: not quite correct) */
  86         cpu_register_physical_memory(start, end - start,
  87                                      start | IO_MEM_ROM);
  88         break;
  89     case 2:
  90     case 0:
  91         /* XXX: should distinguish read/write cases */
  92         for(addr = start; addr < end; addr += 4096) {
  93             cpu_register_physical_memory(addr, 4096,
  94                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
  95         }
  96         break;
  97     }
  98 }
  99
 100 static void i440fx_update_memory_mappings(PCII440FXState *d)
 101 {
 102     int i, r;
 103     uint32_t smram, addr;
 104
 105     update_pam(d, 0xf0000, 0x100000, (d->dev.config[0x59] >> 4) & 3);
 106     for(i = 0; i < 12; i++) {
 107         r = (d->dev.config[(i >> 1) + 0x5a] >> ((i & 1) * 4)) & 3;
 108         update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r);
 109     }
 110     smram = d->dev.config[0x72];
 111     if ((d->smm_enabled && (smram & 0x08)) || (smram & 0x40)) {
 112         cpu_register_physical_memory(0xa0000, 0x20000, 0xa0000);
 113     } else {
 114         for(addr = 0xa0000; addr < 0xc0000; addr += 4096) {
 115             cpu_register_physical_memory(addr, 4096,
 116                                          d->isa_page_descs[(addr - 0xa0000) >> 12]);
 117         }
 118     }
 119 }
 120
 121 void i440fx_set_smm(PCII440FXState *d, int val)
 122 {
 123     val = (val != 0);
 124     if (d->smm_enabled != val) {
 125         d->smm_enabled = val;
 126         i440fx_update_memory_mappings(d);
 127     }
 128 }
 129
 130
 131 /* XXX: suppress when better memory API. We make the assumption that
 132    no device (in particular the VGA) changes the memory mappings in
 133    the 0xa0000-0x100000 range */
 134 void i440fx_init_memory_mappings(PCII440FXState *d)
 135 {
 136     int i;
 137     for(i = 0; i < 96; i++) {
 138         d->isa_page_descs[i] = cpu_get_physical_page_desc(0xa0000 + i * 0x1000);
 139     }
 140 }
 141
 142 static void i440fx_write_config(PCIDevice *dev,
 143                                 uint32_t address, uint32_t val, int len)
 144 {
 145     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 146
 147     /* XXX: implement SMRAM.D_LOCK */
 148     pci_default_write_config(dev, address, val, len);
 149     if ((address >= 0x59 && address <= 0x5f) || address == 0x72)
 150         i440fx_update_memory_mappings(d);
 151 }
 152
 153 static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
 154 {
 155     PCII440FXState *d = opaque;
 156     int ret, i;
 157
 158     ret = pci_device_load(&d->dev, f);
 159     if (ret < 0)
 160         return ret;
 161     i440fx_update_memory_mappings(d);
 162     qemu_get_8s(f, &d->smm_enabled);
 163
 164     if (version_id == 2)
 165         for (i = 0; i < 4; i++)
 166             d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
 167
 168     return 0;
 169 }
 170
 171 static int i440fx_post_load(void *opaque, int version_id)
 172 {
 173     PCII440FXState *d = opaque;
 174
 175     i440fx_update_memory_mappings(d);
 176     return 0;
 177 }
 178
 179 static const VMStateDescription vmstate_i440fx = {
 180     .name = "I440FX",
 181     .version_id = 3,
 182     .minimum_version_id = 3,
 183     .minimum_version_id_old = 1,
 184     .load_state_old = i440fx_load_old,
 185     .post_load = i440fx_post_load,
 186     .fields      = (VMStateField []) {
 187         VMSTATE_PCI_DEVICE(dev, PCII440FXState),
 188         VMSTATE_UINT8(smm_enabled, PCII440FXState),
 189         VMSTATE_END_OF_LIST()
 190     }
 191 };
 192
 193 static int i440fx_pcihost_initfn(SysBusDevice *dev)
 194 {
 195     I440FXState *s = FROM_SYSBUS(I440FXState, dev);
 196
 197     register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s);
 198     register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s);
 199
 200     register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s);
 201     register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s);
 202     register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s);
 203     register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s);
 204     register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s);
 205     register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s);
 206     return 0;
 207 }
 208
 209 static int i440fx_initfn(PCIDevice *dev)
 210 {
 211     PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev);
 212
 213     pci_config_set_vendor_id(d->dev.config, PCI_VENDOR_ID_INTEL);
 214     pci_config_set_device_id(d->dev.config, PCI_DEVICE_ID_INTEL_82441);
 215     d->dev.config[0x08] = 0x02; // revision
 216     pci_config_set_class(d->dev.config, PCI_CLASS_BRIDGE_HOST);
 217     d->dev.config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 218
 219     d->dev.config[0x72] = 0x02; /* SMRAM */
 220
 221     vmstate_register(0, &vmstate_i440fx, d);
 222     return 0;
 223 }
 224
 225 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic)
 226 {
 227     DeviceState *dev;
 228     PCIBus *b;
 229     PCIDevice *d;
 230     I440FXState *s;
 231     PIIX3State *piix3;
 232
 233     dev = qdev_create(NULL, "i440FX-pcihost");
 234     s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
 235     b = pci_bus_new(&s->busdev.qdev, NULL, 0);
 236     s->bus = b;
 237     qdev_init_nofail(dev);
 238
 239     d = pci_create_simple(b, 0, "i440FX");
 240     *pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
 241
 242     piix3 = DO_UPCAST(PIIX3State, dev,
 243                                  pci_create_simple(b, -1, "PIIX3"));
 244     piix3->pic = pic;
 245     pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
 246     (*pi440fx_state)->piix3 = piix3;
 247
 248     *piix3_devfn = piix3->dev.devfn;
 249
 250     return b;
 251 }
 252
 253 /* PIIX3 PCI to ISA bridge */
 254
 255 static void piix3_set_irq(void *opaque, int irq_num, int level)
 256 {
 257     int i, pic_irq, pic_level;
 258     PIIX3State *piix3 = opaque;
 259
 260     piix3->pci_irq_levels[irq_num] = level;
 261
 262     /* now we change the pic irq level according to the piix irq mappings */
 263     /* XXX: optimize */
 264     pic_irq = piix3->dev.config[0x60 + irq_num];
 265     if (pic_irq < 16) {
 266         /* The pic level is the logical OR of all the PCI irqs mapped
 267            to it */
 268         pic_level = 0;
 269         for (i = 0; i < 4; i++) {
 270             if (pic_irq == piix3->dev.config[0x60 + i])
 271                 pic_level |= piix3->pci_irq_levels[i];
 272         }
 273         qemu_set_irq(piix3->pic[pic_irq], pic_level);
 274     }
 275 }
 276
 277 static void piix3_reset(void *opaque)
 278 {
 279     PIIX3State *d = opaque;
 280     uint8_t *pci_conf = d->dev.config;
 281
 282     pci_conf[0x04] = 0x07; // master, memory and I/O
 283     pci_conf[0x05] = 0x00;
 284     pci_conf[0x06] = 0x00;
 285     pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
 286     pci_conf[0x4c] = 0x4d;
 287     pci_conf[0x4e] = 0x03;
 288     pci_conf[0x4f] = 0x00;
 289     pci_conf[0x60] = 0x80;
 290     pci_conf[0x61] = 0x80;
 291     pci_conf[0x62] = 0x80;
 292     pci_conf[0x63] = 0x80;
 293     pci_conf[0x69] = 0x02;
 294     pci_conf[0x70] = 0x80;
 295     pci_conf[0x76] = 0x0c;
 296     pci_conf[0x77] = 0x0c;
 297     pci_conf[0x78] = 0x02;
 298     pci_conf[0x79] = 0x00;
 299     pci_conf[0x80] = 0x00;
 300     pci_conf[0x82] = 0x00;
 301     pci_conf[0xa0] = 0x08;
 302     pci_conf[0xa2] = 0x00;
 303     pci_conf[0xa3] = 0x00;
 304     pci_conf[0xa4] = 0x00;
 305     pci_conf[0xa5] = 0x00;
 306     pci_conf[0xa6] = 0x00;
 307     pci_conf[0xa7] = 0x00;
 308     pci_conf[0xa8] = 0x0f;
 309     pci_conf[0xaa] = 0x00;
 310     pci_conf[0xab] = 0x00;
 311     pci_conf[0xac] = 0x00;
 312     pci_conf[0xae] = 0x00;
 313
 314     memset(d->pci_irq_levels, 0, sizeof(d->pci_irq_levels));
 315 }
 316
 317 static const VMStateDescription vmstate_piix3 = {
 318     .name = "PIIX3",
 319     .version_id = 3,
 320     .minimum_version_id = 2,
 321     .minimum_version_id_old = 2,
 322     .fields      = (VMStateField []) {
 323         VMSTATE_PCI_DEVICE(dev, PIIX3State),
 324         VMSTATE_INT32_ARRAY_V(pci_irq_levels, PIIX3State, 4, 3),
 325         VMSTATE_END_OF_LIST()
 326     }
 327 };
 328
 329 static int piix3_initfn(PCIDevice *dev)
 330 {
 331     PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev);
 332     uint8_t *pci_conf;
 333
 334     isa_bus_new(&d->dev.qdev);
 335     vmstate_register(0, &vmstate_piix3, d);
 336
 337     pci_conf = d->dev.config;
 338     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 339     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
 340     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA);
 341     pci_conf[PCI_HEADER_TYPE] =
 342         PCI_HEADER_TYPE_NORMAL | PCI_HEADER_TYPE_MULTI_FUNCTION; // header_type = PCI_multifunction, generic
 343
 344     piix3_reset(d);
 345     qemu_register_reset(piix3_reset, d);
 346     return 0;
 347 }
 348
 349 static PCIDeviceInfo i440fx_info[] = {
 350     {
 351         .qdev.name    = "i440FX",
 352         .qdev.desc    = "Host bridge",
 353         .qdev.size    = sizeof(PCII440FXState),
 354         .qdev.no_user = 1,
 355         .init         = i440fx_initfn,
 356         .config_write = i440fx_write_config,
 357     },{
 358         .qdev.name    = "PIIX3",
 359         .qdev.desc    = "ISA bridge",
 360         .qdev.size    = sizeof(PIIX3State),
 361         .qdev.no_user = 1,
 362         .init         = piix3_initfn,
 363     },{
 364         /* end of list */
 365     }
 366 };
 367
 368 static SysBusDeviceInfo i440fx_pcihost_info = {
 369     .init         = i440fx_pcihost_initfn,
 370     .qdev.name    = "i440FX-pcihost",
 371     .qdev.size    = sizeof(I440FXState),
 372     .qdev.no_user = 1,
 373 };
 374
 375 static void i440fx_register(void)
 376 {
 377     sysbus_register_withprop(&i440fx_pcihost_info);
 378     pci_qdev_register_many(i440fx_info);
 379 }
 380 device_init(i440fx_register);